In test_memory_send the variable i is of unsigned type, so
it is never negative. If i is 0, the result of i-- is
4294967295. Don't know what happens if trying to
access composite->address_range_array[4294967295].
Made i a signed integer.
Signed-off-by: Thomas Viehweger <Thomas.Viehweger@rohde-schwarz.com>
Change-Id: I8b4e532749b5e86e4b5acd238e72c3f88e309ff2
* changes:
feat(spmd): map SPMC manifest region as EL3_PAS
feat(fvp): update device tree with load addresses of TOS_FW config
refactor(fvp): rename the DTB info structure member
feat(fconf): rename 'ns-load-address' to 'secondary-load-address'
There were some late comments to the prior change (18635) which are
address in this commit. There was also an invalid return value check
which was changed and the wrong result was being returned via the SMC
call for loading OP-TEE which is now fixed.
Signed-off-by: Jeffrey Kardatzke <jkardatzke@google.com>
Change-Id: I883ddf966662549a3ef9c801a2d4f47709422332
SAVE_KEYS is set to '0' by default, causing cert_create to
show the 'Key filename not specified' message on each run
even though this is perfectly normal. Show the message only
in the VERBOSE log level.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Change-Id: I472cdec2670055ab0edd99d172f79d01ad575972
Adds a pre-commit git hook to keep track of copyright year.
Checks staged files for Arm copyright header and suggests a change if
the year is outdated. Works with both single-year format and
from_year-to_year format.
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Change-Id: If81a0b9f5e047ec0ac401c7cf1792b9da6644926
The tos_fw_config is currently loaded into memory by BL2 and
consumed by SPMD (part of BL31) and BL32 firmwares. This does
not work in RME-enabled systems as BL31 uses the root PAS memory
and does not trust secure PAS memory.
A first attempt was made to map the TOS_FW_CONFIG region as root PAS,
and then to remap to secure PAS after SPMD consumption, but this was
not suitable for RME systems where memory encryption is enabled.
This can be solved by copying the TOS FW config (SPMC manifest) from
the Root PAS region to the Secure PAS region so that BL32 can consume
it.
Change-Id: I8eef8345366199cb0e367db883c34a5b5136465d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Enable SCXTNUM_ELx access for lower ELs in non-secure state.
Make realm context setup take this build flag into account but enable it
by default when RME is used.
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Change-Id: Ieb0186b2fdffad464bb9316fc3973772c9c28cd0
* changes:
refactor(allwinner): use fdt_node_is_enabled() in AXP driver
fix(allwinner): check RSB availability in DT on H6
refactor(fdt): introduce common fdt_node_is_enabled()
Adding AP/RSS interface for retrieving and incrementing non-volatile
counters.
The read interface implements the psa_call:
psa_call(RSS_PLATFORM_SERVICE_HANDLE,
RSS_PLATFORM_API_ID_NV_READ,
in_vec, 1, out_vec, 1);
where the in_vec indicates which of the 3 counters we want, and the
out_vec stores the counter value we get back from RSS.
The increment interface implements the psa_call:
psa_call(RSS_PLATFORM_SERVICE_HANDLE,
RSS_PLATFORM_API_ID_NV_INCREMENT,
in_vec, 1, (psa_outvec *)NULL, 0);
where, again, in_vec indicates the counter to increment, and we don't
get any output parameter from RSS.
Through this service, we will be able to get/increment any of the 3 NV
counters used on a CCA platform:
- NV counter for CCA firmware (BL2, BL31, RMM).
- NV counter for secure firmware.
- NV counter for non-secure firmware.
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Signed-off-by: Raef Coles <raef.coles@arm.com>
Change-Id: I4c1c7f4837ebff30de16bb0ce7ecd416b70b1f62
Mapped SPMC manifest region as EL3_PAS so that it will get
mapped as Root region in RME enabled system otherwise Secure
region.
Change-Id: I1af5344d7516e948d5b3664bcdb94cdfc367cd78
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Provided both the root and secure addresses for TOS_FW config
in case of RME enabled systems where root address is in Root
SRAM and secure address is in Trusted DRAM.
Non-RME systems are unaffected by this change.
Change-Id: Ifb927c90fa5a68fe5362980858b4ddc5403ac95b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
In line with the previous patch, the name of the member of the
hw_config DTB info structure has been renamed.
Change-Id: I6689e416fecd66faa515e820f1c4b23bcb65bfb1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
The 'ns-load-address' property has been renamed to 'secondary-load-
address' in order to make it more generic. It can be used to copy
the configuration to any location, be it root, secure, or non-secure.
Change-Id: I122508e155ccd99082296be3f6b8db2f908be221
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
The Allwinner AXP driver was using a private implementation of that
function, remove that in favour of our now common implementation.
Change-Id: I7bd311d73060d4bc83f93cff6bedf6c78dddd3ca
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
At the moment we access the RSB bus on all Allwinner H6 boards
unconditionally, even though some boards do not have any PMIC at all,
while others have some I2C devices connected to the same pins.
The latter case is just fragile, but the first case leads to a hang on
at least one board, as reported by Jernej.
Scan the devicetree, to check for the availability of the RSB bus node.
Proceed only if the RSB DT node is actually enabled.
Change-Id: Iea7dcfe3e085e173334d098ec4ddcb6c4b085771
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: Jernej Skrabec <jernej.skrabec@gmail.com>
There are several users in the tree which want to check whether a given
FDT node is enabled or not: the "status" property holds that
information. So far all those users provide private implementations,
some of them having issues.
Export a generic implementation of that function in fdt_wrappers.h, as
a "static inline" function to not increase code size.
Also replace the existing implementation in Arm's fconf code, which had
a tiny bug in needlessly using the property length:
"status = [6f 6b 61 79 20];" would pass the check, where it should not.
The proper solution is also simpler: status must be a string, and
strings must be NUL-terminated in a DT. strcmp() would terminate on the
first NUL in *either* of the two strings it compares, so it would never
walk beyond the property boundary in the DTB.
Change-Id: I9d89093432f127c09add6cf5c93a725bc534e5de
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Remove company name from the console messages while printing only
relevant information for the platform.
Change-Id: Id8171326e0267eb6f3a26de4eb66143970de2dbd
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
* changes:
docs(rme): update RMM-EL3 Boot Manifest structure description
feat(rme): read DRAM information from FVP DTB
feat(rme): set DRAM information in Boot Manifest platform data
Currently gicv3_rdistif_probe() is called per CPU. In case of maxcpus=1,
only 1 core is initialized and gicr_base_addrs initialized for CPU 0
only. Because of this assertion is raised during Linux system suspend.
During Linux suspend, platform callback saves GIC v3 state which
internally invokes arm_gicv3_distif_pre_save(). This function tries to use
gicr_base for all CPUs. Since GICR base address for secondary CPUs are not
initialized, it raises assertion.
To fix the issue, populate GIC v3 rdist data statically (similar to Versal)
instead of dynamically initializing GIC v3 rdist per CPU.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I98c97c03e451d05f4ebac358e197617ab9d9b71f
Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC is used as console for
the platform.
Though DCC is not using any UART, VERSAL_NET_UART_BASE needs
to be defined in the platform code. If its not defined, build errors
are observed.
Now VERSAL_NET_UART_BASE by default points to UART0 base.
Check for valid console(pl011, pl011_0, pl011_1, dcc) is
being done in the platform makefile, the error condition in
setting the value of VERSAL_NET_UART_BASE is redundant, thus the error
message is removed from the code.
Change-Id: I1085433055abea13526230cff4d4183ff7a01477
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
This adds the ability to load the OP-TEE image via an SMC called from
non-secure userspace rather than loading it during boot. This should
only be utilized on platforms that can ensure security is maintained up
until the point the SMC is invoked as it breaks the normal barrier
between the secure and non-secure world.
Signed-off-by: Jeffrey Kardatzke <jkardatzke@google.com>
Change-Id: I21cfa9699617c493fa4190f01d1cbb714e7449cc
This patch updates description of RMM-EL3 Boot Manifest
structure and its corresponding diagram and tables with DRAM
layout data.
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I1b092bc1ad5f1c7909d25c1a0dc89c2b210ada27
This patch builds on the previous patch by implementing
support for reading NS DRAM layout of FVP model from
HW_CONFIG Device tree.
Macro _RMMD_MANIFEST_VERSION is renamed to
SET_RMMD_MANIFEST_VERSION to suppress MISRA-C
"rule MC3R1.D4.5: (advisory) Identifiers in
the same name space with overlapping visibility
should be typographically unambiguous" warning
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: Ifc2461b4441a1efdd4b7c656ab4d15e62479f77b
Fixed few typos in the measured boot POC document.
Change-Id: I122c069bbde51febed12c54e2c4a4985b009ef5f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
The current putc version test for TXEMPTY bit set (#6) instead
of waiting for TXFULL bit clear (#4), that slows the global
boot time as we are not taking benefit of the 32-byte FIFO.
We then need to implement the flush function to be sure the
transmit is complete (FIFO and shift register empty).
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Change-Id: I54873a5203e2afdc230e44ce73284e7a80985b4f
This patch add support to load HW_CONFIG in BL2 and pass it to
bootloader stages BL31 and BL33.
Signed-off-by: Patrik Berglund <patrik.berglund@arm.com>
Change-Id: I646fabed83dbca5322a59a399de5194cfef474ad
The L3 cache in the DSU supports the Memory System Resources
Partitioning and Monitoring (MPAM). The MPAM specific registers in the
DSU are accessed through utility bus of DSU that are memory mapped from
0x1_0000_1000.
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I2798181d599228e96dd4c0043a2ccd94668c7e20
