Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-15 17:14:21 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

fix(context-mgmt): enable SCXTNUM access

Browse source 
Enable SCXTNUM_ELx access for lower ELs in non-secure state.
Make realm context setup take this build flag into account but enable it
by default when RME is used.

Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Change-Id: Ieb0186b2fdffad464bb9316fc3973772c9c28cd0
This commit is contained in:
Maksims Svecovs 2023-02-02 16:10:22 +00:00
parent 35f81474fb
commit 01cf14dd41
2 changed files with 16 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
Makefile
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -153,6 +153,9 @@ ARM_ARCH_MINOR := 5
ENABLE_FEAT_ECV = 1
ENABLE_FEAT_FGT = 1
# RME enables CSV2_2 extension by default.
ENABLE_FEAT_CSV2_2 = 1
endif
# USE_SPINLOCK_CAS requires AArch64 build

14
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -169,7 +169,12 @@ static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_inf
state = get_el3state_ctx(ctx);
scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT;
scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT;
#if ENABLE_FEAT_CSV2_2
/* Enable access to the SCXTNUM_ELx registers. */
scr_el3 |= SCR_EnSCXT_BIT;
#endif
write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
}
@ -222,6 +227,11 @@ static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *
scr_el3 |= SCR_TERR_BIT;
#endif
#if ENABLE_FEAT_CSV2_2
/* Enable access to the SCXTNUM_ELx registers. */
scr_el3 |= SCR_EnSCXT_BIT;
#endif
#ifdef IMAGE_BL31
/*
* SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as