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feat(rme): read DRAM information from FVP DTB

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This patch builds on the previous patch by implementing
support for reading NS DRAM layout of FVP model from
HW_CONFIG Device tree.

Macro _RMMD_MANIFEST_VERSION is renamed to
SET_RMMD_MANIFEST_VERSION to suppress MISRA-C
"rule MC3R1.D4.5: (advisory) Identifiers in
the same name space with overlapping visibility
should be typographically unambiguous" warning

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: Ifc2461b4441a1efdd4b7c656ab4d15e62479f77b
This commit is contained in:
AlexeiFedorov 2022-12-29 15:57:40 +00:00 • committed by Soby Mathew
parent a97bfa5ff1
commit 8268590498
7 changed files with 158 additions and 57 deletions
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4
include/plat/arm/common/arm_def.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -236,7 +236,7 @@
#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
ARM_DRAM2_SIZE - 1U)
/* Number of DRAM banks */
#define ARM_DRAM_BANKS_NUM 2UL
#define ARM_DRAM_NUM_BANKS 2UL
#define ARM_IRQ_SEC_PHY_TIMER 29

48
include/services/rmm_core_manifest.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2022, Arm Limited. All rights reserved.
* Copyright (c) 2022-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -22,57 +22,57 @@
* - Bits [30:16] Major version
* - Bits [15:0] Minor version
*/
#define _RMMD_MANIFEST_VERSION(_major, _minor) \
#define SET_RMMD_MANIFEST_VERSION(_major, _minor) \
((((_major) & 0x7FFF) << 16) | ((_minor) & 0xFFFF))
#define RMMD_MANIFEST_VERSION _RMMD_MANIFEST_VERSION( \
RMMD_MANIFEST_VERSION_MAJOR, \
#define RMMD_MANIFEST_VERSION SET_RMMD_MANIFEST_VERSION( \
RMMD_MANIFEST_VERSION_MAJOR, \
RMMD_MANIFEST_VERSION_MINOR)
#define RMMD_GET_MANIFEST_VERSION_MAJOR(_version) \
#define RMMD_GET_MANIFEST_VERSION_MAJOR(_version) \
((_version >> 16) & 0x7FFF)
#define RMMD_GET_MANIFEST_VERSION_MINOR(_version) \
#define RMMD_GET_MANIFEST_VERSION_MINOR(_version) \
(_version & 0xFFFF)
/* DRAM bank structure */
struct dram_bank {
/* NS DRAM bank structure */
struct ns_dram_bank {
uintptr_t base; /* Base address */
uint64_t size; /* Size of bank */
};
CASSERT(offsetof(struct dram_bank, base) == 0,
CASSERT(offsetof(struct ns_dram_bank, base) == 0UL,
rmm_manifest_base_unaligned);
CASSERT(offsetof(struct dram_bank, size) == 8,
CASSERT(offsetof(struct ns_dram_bank, size) == 8UL,
rmm_manifest_size_unaligned);
/* DRAM layout info structure */
struct dram_info {
uint64_t banks_num; /* Number of DRAM banks */
struct dram_bank *dram_data; /* Pointer to dram_bank[] */
uint64_t check_sum; /* Checksum of dram_info data */
/* NS DRAM layout info structure */
struct ns_dram_info {
uint64_t num_banks; /* Number of NS DRAM banks */
struct ns_dram_bank *banks; /* Pointer to ns_dram_bank[] */
uint64_t checksum; /* Checksum of ns_dram_info data */
};
CASSERT(offsetof(struct dram_info, banks_num) == 0,
rmm_manifest_banks_num_unaligned);
CASSERT(offsetof(struct dram_info, dram_data) == 8,
CASSERT(offsetof(struct ns_dram_info, num_banks) == 0UL,
rmm_manifest_num_banks_unaligned);
CASSERT(offsetof(struct ns_dram_info, banks) == 8UL,
rmm_manifest_dram_data_unaligned);
CASSERT(offsetof(struct dram_info, check_sum) == 16,
rmm_manifest_check_sum_unaligned);
CASSERT(offsetof(struct ns_dram_info, checksum) == 16UL,
rmm_manifest_checksum_unaligned);
/* Boot manifest core structure as per v0.2 */
struct rmm_manifest {
uint32_t version; /* Manifest version */
uint32_t padding; /* RES0 */
uintptr_t plat_data; /* Manifest platform data */
struct dram_info plat_dram; /* Platform DRAM data */
struct ns_dram_info plat_dram; /* Platform NS DRAM data */
};
CASSERT(offsetof(struct rmm_manifest, version) == 0,
CASSERT(offsetof(struct rmm_manifest, version) == 0UL,
rmm_manifest_version_unaligned);
CASSERT(offsetof(struct rmm_manifest, plat_data) == 8,
CASSERT(offsetof(struct rmm_manifest, plat_data) == 8UL,
rmm_manifest_plat_data_unaligned);
CASSERT(offsetof(struct rmm_manifest, plat_dram) == 16,
CASSERT(offsetof(struct rmm_manifest, plat_dram) == 16UL,
rmm_manifest_plat_dram_unaligned);
#endif /* RMM_CORE_MANIFEST_H */

62
plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, Arm Limited. All rights reserved.
* Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -18,6 +18,15 @@ struct gicv3_config_t gicv3_config;
struct hw_topology_t soc_topology;
struct uart_serial_config_t uart_serial_config;
struct cpu_timer_t cpu_timer;
struct ns_dram_layout dram_layout;
/*
* Each NS DRAM bank entry is 'reg' node property which is
* a sequence of (address, length) pairs of 32-bit values.
*/
#define DRAM_ENTRY_SIZE (4UL * sizeof(uint32_t))
CASSERT(ARM_DRAM_NUM_BANKS == 2UL, ARM_DRAM_NUM_BANKS_mismatch);
#define ILLEGAL_ADDR ULL(~0)
@ -293,7 +302,58 @@ int fconf_populate_cpu_timer(uintptr_t config)
return 0;
}
int fconf_populate_dram_layout(uintptr_t config)
{
int node, len;
const uint32_t *reg;
/* Necessary to work with libfdt APIs */
const void *hw_config_dtb = (const void *)config;
/* Find 'memory' node */
node = fdt_node_offset_by_prop_value(hw_config_dtb, -1, "device_type",
"memory", sizeof("memory"));
if (node < 0) {
WARN("FCONF: Unable to locate 'memory' node\n");
return node;
}
reg = fdt_getprop(hw_config_dtb, node, "reg", &len);
if (reg == NULL) {
ERROR("FCONF failed to read 'reg' property\n");
return len;
}
switch (len) {
case DRAM_ENTRY_SIZE:
/* 1 DRAM bank */
dram_layout.num_banks = 1UL;
break;
case 2UL * DRAM_ENTRY_SIZE:
/* 2 DRAM banks */
dram_layout.num_banks = 2UL;
break;
default:
ERROR("FCONF: Invalid 'memory' node\n");
return -FDT_ERR_BADLAYOUT;
}
for (unsigned long i = 0UL; i < dram_layout.num_banks; i++) {
int err = fdt_get_reg_props_by_index(
hw_config_dtb, node, (int)i,
&dram_layout.dram_bank[i].base,
(size_t *)&dram_layout.dram_bank[i].size);
if (err < 0) {
ERROR("FCONF: Failed to read 'reg' property #%lu of 'memory' node\n", i);
return err;
}
}
return 0;
}
FCONF_REGISTER_POPULATOR(HW_CONFIG, gicv3_config, fconf_populate_gicv3_config);
FCONF_REGISTER_POPULATOR(HW_CONFIG, topology, fconf_populate_topology);
FCONF_REGISTER_POPULATOR(HW_CONFIG, uart_config, fconf_populate_uart_config);
FCONF_REGISTER_POPULATOR(HW_CONFIG, cpu_timer, fconf_populate_cpu_timer);
FCONF_REGISTER_POPULATOR(HW_CONFIG, dram_layout, fconf_populate_dram_layout);

78
plat/arm/board/fvp/fvp_common.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -12,6 +12,7 @@
#include <drivers/arm/gicv2.h>
#include <drivers/arm/sp804_delay_timer.h>
#include <drivers/generic_delay_timer.h>
#include <fconf_hw_config_getter.h>
#include <lib/mmio.h>
#include <lib/smccc.h>
#include <lib/xlat_tables/xlat_tables_compat.h>
@ -530,45 +531,72 @@ size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared)
return (size_t)RMM_SHARED_SIZE;
}
CASSERT(ARM_DRAM_BANKS_NUM == 2UL, ARM_DRAM_BANKS_NUM_mismatch);
/* FVP DRAM banks */
const struct dram_bank fvp_dram_banks[ARM_DRAM_BANKS_NUM] = {
{ARM_PAS_2_BASE, ARM_PAS_2_SIZE},
{ARM_PAS_4_BASE, ARM_PAS_4_SIZE}
};
int plat_rmmd_load_manifest(struct rmm_manifest *manifest)
{
uint64_t check_sum;
struct dram_bank *bank_ptr;
uint64_t checksum, num_banks;
struct ns_dram_bank *bank_ptr;
assert(manifest != NULL);
/* Get number of DRAM banks */
num_banks = FCONF_GET_PROPERTY(hw_config, dram_layout, num_banks);
assert(num_banks <= ARM_DRAM_NUM_BANKS);
manifest->version = RMMD_MANIFEST_VERSION;
manifest->padding = 0U; /* RES0 */
manifest->plat_data = (uintptr_t)NULL;
manifest->plat_dram.banks_num = ARM_DRAM_BANKS_NUM;
manifest->plat_dram.num_banks = num_banks;
/* Array dram_banks[] follows dram_info structure */
bank_ptr = (struct dram_bank *)
((uintptr_t)&manifest->plat_dram.check_sum +
sizeof(manifest->plat_dram.check_sum));
/*
* Array ns_dram_banks[] follows ns_dram_info structure:
*
* +-----------------------------------+
* | offset | field | comment |
* +----------+-----------+------------+
* | 0 | version | 0x00000002 |
* +----------+-----------+------------+
* | 4 | padding | 0x00000000 |
* +----------+-----------+------------+
* | 8 | plat_data | NULL |
* +----------+-----------+------------+
* | 16 | num_banks | |
* +----------+-----------+ |
* | 24 | banks | plat_dram |
* +----------+-----------+ |
* | 32 | checksum | |
* +----------+-----------+------------+
* | 40 | base 0 | |
* +----------+-----------+ bank[0] |
* | 48 | size 0 | |
* +----------+-----------+------------+
* | 56 | base 1 | |
* +----------+-----------+ bank[1] |
* | 64 | size 1 | |
* +----------+-----------+------------+
*/
bank_ptr = (struct ns_dram_bank *)
((uintptr_t)&manifest->plat_dram.checksum +
sizeof(manifest->plat_dram.checksum));
manifest->plat_dram.dram_data = bank_ptr;
manifest->plat_dram.banks = bank_ptr;
/* Copy FVP DRAM banks data to Boot Manifest */
(void)memcpy((void *)bank_ptr, &fvp_dram_banks, sizeof(fvp_dram_banks));
/* Calculate checksum of plat_dram structure */
checksum = num_banks + (uint64_t)bank_ptr;
/* Calculate check sum of plat_dram structure */
check_sum = ARM_DRAM_BANKS_NUM + (uint64_t)bank_ptr;
/* Store FVP DRAM banks data in Boot Manifest */
for (unsigned long i = 0UL; i < num_banks; i++) {
uintptr_t base = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].base);
uint64_t size = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].size);
for (unsigned long i = 0UL; i < ARM_DRAM_BANKS_NUM; i++) {
check_sum += bank_ptr[i].base + bank_ptr[i].size;
bank_ptr[i].base = base;
bank_ptr[i].size = size;
/* Update checksum */
checksum += base + size;
}
/* Check sum must be 0 */
manifest->plat_dram.check_sum = ~check_sum + 1UL;
/* Checksum must be 0 */
manifest->plat_dram.checksum = ~checksum + 1UL;
return 0;
}

14
plat/arm/board/fvp/include/fconf_hw_config_getter.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, Arm Limited. All rights reserved.
* Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -8,12 +8,16 @@
#define FCONF_HW_CONFIG_GETTER_H
#include <lib/fconf/fconf.h>
#include <services/rmm_core_manifest.h>
#include <plat/arm/common/arm_def.h>
/* Hardware Config related getter */
#define hw_config__gicv3_config_getter(prop) gicv3_config.prop
#define hw_config__topology_getter(prop) soc_topology.prop
#define hw_config__uart_serial_config_getter(prop) uart_serial_config.prop
#define hw_config__cpu_timer_getter(prop) cpu_timer.prop
#define hw_config__dram_layout_getter(prop) dram_layout.prop
struct gicv3_config_t {
uint64_t gicd_base;
@ -36,13 +40,21 @@ struct cpu_timer_t {
uint32_t clock_freq;
};
struct ns_dram_layout {
uint64_t num_banks;
struct ns_dram_bank dram_bank[ARM_DRAM_NUM_BANKS];
};
int fconf_populate_gicv3_config(uintptr_t config);
int fconf_populate_topology(uintptr_t config);
int fconf_populate_uart_config(uintptr_t config);
int fconf_populate_cpu_timer(uintptr_t config);
int fconf_populate_dram_layout(uintptr_t config);
extern struct gicv3_config_t gicv3_config;
extern struct hw_topology_t soc_topology;
extern struct uart_serial_config_t uart_serial_config;
extern struct cpu_timer_t cpu_timer;
extern struct ns_dram_layout dram_layout;
#endif /* FCONF_HW_CONFIG_GETTER_H */

3
plat/arm/board/fvp/jmptbl.i
View file

@ -1,5 +1,5 @@
#
# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -21,6 +21,7 @@ fdt fdt_getprop_namelen
fdt fdt_setprop_inplace
fdt fdt_check_header
fdt fdt_node_offset_by_compatible
fdt fdt_node_offset_by_prop_value
fdt fdt_setprop_inplace_namelen_partial
fdt fdt_first_subnode
fdt fdt_next_subnode

6
plat/arm/common/arm_bl2_setup.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -23,7 +23,9 @@
#include <lib/optee_utils.h>
#endif
#include <lib/utils.h>
#if ENABLE_RME
#include <plat/arm/common/arm_pas_def.h>
#endif
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
@ -127,7 +129,6 @@ void bl2_platform_setup(void)
}
#if ENABLE_RME
static void arm_bl2_plat_gpt_setup(void)
{
/*
@ -167,7 +168,6 @@ static void arm_bl2_plat_gpt_setup(void)
panic();
}
}
#endif /* ENABLE_RME */
/*******************************************************************************