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Merge "feat(plat/tc): enable MPAM functionality of L3 DSU cache" into integration
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commit
9dea6fa680
1 changed files with 10 additions and 1 deletions
11
fdts/tc.dts
11
fdts/tc.dts
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2020-2022, Arm Limited. All rights reserved.
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* Copyright (c) 2020-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -519,6 +519,15 @@
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};
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};
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/*
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* L3 cache in the DSU is the Memory System Component (MSC)
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* The MPAM registers are accessed through utility bus in the DSU
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*/
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msc0 {
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compatible = "arm,mpam-msc";
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reg = <0x1 0x00010000 0x0 0x2000>;
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};
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ete0 {
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compatible = "arm,embedded-trace-extension";
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cpu = <&CPU0>;
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