CryptoCell-712 and CryptoCell-713 drivers have been deprecated since
TF-A v2.9 and their removal was announced for TF-A v2.10 release.
See [1].
As the release is approaching, this patch deletes these drivers' code as
well as all references to them in the documentation and Arm platforms
code (Nuvoton platform is taken care in a subsequent patch). Associated
build options (ARM_CRYPTOCELL_INTEG and PLAT_CRYPTOCELL_BASE) have also
been removed and thus will have no effect if defined.
This is a breaking change for downstream platforms which use these
drivers.
[1] https://trustedfirmware-a.readthedocs.io/en/v2.9/about/release-information.html#removal-of-deprecated-drivers
Note that TF-A v3.0 release later got renumbered into v2.10.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Idabbc9115f6732ac1a0e52b273d3380677a39813
* changes:
feat(sgi): increase sp memmap size
feat(build): include plat header in fdt build
feat(docs): save BL32 image base and size in entry point info
feat(arm): save BL32 image base and size in entry point info
The EL3 SPMC is known to be deployed into end products and properly
tested since its introduction into TF-A v2.7.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I96bb897cfefef20c33cfc39627b10746dce5485c
With FF-A enabled on SP at SEL0 enabled, SPMC at EL3 needs more entries
to map newly added regions(SP, Rx/Tx buffer and Manifest).
Increase the PLAT_SP_IMAGE_MMAP_REGIONS to 14 and MAX_XLAT_TABLES to 9.
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I96fd291db8eb178f7aa73b5a9e38cfc67c66fa91
Include platform headers in DT build to enable build time configuration
of number of execution context supported by the platform.
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I5b9ffc9865f198a1f802fcb5e0950a5fabb48727
There is no platform function to retrieve the info in the generic code.
Populate the BL32 image base, size and max limit in arg2, arg3 and arg4.
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I35527fb41829102083b488a5150c0c707c5ede15
There is no platform function to retrieve the info in the generic code.
Populate the BL32 image base, size and max limit in arg2, arg3 and arg4.
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Id41cedd790ca1713787e5516fb84666d1ccb0b03
Introducing INIT_UNUSED_NS_EL2 macro which guards the code that
disables the unused EL2 when a platform hands off from EL3
to NS-EL1 instead of NS-EL2. Platforms without NS-EL2 in use
must enable this flag.
BREAKING CHANGE: Initialisation code for handoff from EL3 to NS-EL1
disabled by default. Platforms which do that need to enable this macro
going forward
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I61431cc4f7e2feb568d472828e5fd79cc73e51f5
Update the compiler-rt source files to the tip of llvm-project [1].
[1] https://github.com/llvm/llvm-project/commit/ab97b89d03a7
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ia72b25423896a530bf5bb68ff067184b2314e2be
Update the zlib source files to the latest tagged version 1.3 [1].
[1] https://github.com/madler/zlib/tree/v1.3
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I1eba5671efab75699e68fc2f2aa9400d0f5aba7d
As part of TF-A 2.9.0 release, libfdt version was updated to its last
tagged version (1.7.0) with commit 058e017e5. This commit has only
updated the source files of libfdt but did not update header files.
This patch updates the libfdt header files in include/lib/libfdt to
the tagged version v1.7.0
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I09a0f51435b343c3e1cac45075fe7d28cbcae867
There are various SMC calls which pass mpidr as an argument which is
currently tested at random places in SMC call path.
To make the mpidr validation check consistent across SMC calls, do
this check as part of SMC argument validation.
This patch introduce a helper function is_valid_mpidr() to validate
mpidr and call it as part of validating SMC arguments at starting of
SMC handlers (which expect mpidr as an argument).
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I11ea50e22caf17896cf4b2059b87029b2ba136b1
Failing to send a message is often not fatal and we will end up trying
to send again. This would fail as some exit paths do not release the
secure proxy xfer lock. Release this lock on all return paths.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I3939015774f819572dbd26720b2c105fba7574cb
Add a chapter "Version numbering" in release information file that
explains macros used for TF-A version. It also introduces VERSION_PATCH
macro that is used for LTS releases. A comment for this macro is also
added in Makefile.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I946b6cb91bb8454131f07b24534d28ab1aef1771
TF-A version string is passed into NT_FW_CONFIG to allow access in
UEFI.
Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I9da7b93d30c9d9230ea9a2cd2730cde897ffc580
SDS firmware version structure is added with MCC, PCC and SCP firmware
version members. These are set in NT_FW_CONFIG to provide access to
firmware version information in UEFI.
Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: Ib0c476e54ef428fb7904f0de5c6f4df6a5fbd7db
There are no existing users of pm_ioctl_set_sgmii_mode() API so
cleanup the dead code.
Change-Id: I1088d2f5c944bf54fc5fdd554360bdd321ad798a
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
Enable SME for RMM using sme_enable_per_world as well as sme_enable.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I6070f4778e507ac9cbc7442e727bedad9b40e635
Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest
Change-Id: I03897dc2a7f908937612c2b66ce7a043c1b7575d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest
Change-Id: I4d9d3760491f1e6c59b2667c16d59b99cc7979f1
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Neoverse N2 erratum 2340933 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to set
CPUACTLR5_EL1[61] to 1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest
Change-Id: I121add0dd35072c53392d33f049d893a5ff6354f
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Neoverse N2 erratum 2346952 is a Cat B erratum that applies to all
revisions <= r0p2 and is fixed in r0p3.
The workaround is to set L2 TQ size statically to it's full size.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest
Change-Id: I03c3cf1f951fbc906fdebcb99a523c5ac8ba055d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
* changes:
docs(ras): update RAS documentation
docs(el3-runtime): update BL31 exception vector handling
fix(el3-runtime): restrict lower el EA handlers in FFH mode
fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT
fix(ras): restrict ENABLE_FEAT_RAS to have only two states
feat(ras): use FEAT_IESB for error synchronization
feat(el3-runtime): modify vector entry paths
Add information about Versal NET platform for TSP and provide
the build commands.
Change-Id: Id7c9d75f8a42813ca2bfd18494bfc6b73df0af52
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Add information about Versal platform for TSP and provide
the build commands.
Change-Id: I7106ab477a881c58e1c45863bd6854d188982282
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal NET platform. TSP is a component for testing and validating
secure OS and trusted execution environments.
If a BL32 image is present, then there must be a matching Secure-EL1
Payload Dispatcher (SPD) service called TSPD, this service is
responsible for Initializing the TSP. During initialization that
service must register a function to carry out initialization of BL32
once the runtime services are fully initialized. BL31 invokes such
a registered function to initialize BL32 before running BL33.
The GICv3 driver is initialized in EL3 and does not need to be
initialized again in SEL1 GICv3 driver is initialized in EL3 This is
because the S-EL1 can use GIC system registers to manage interrupts
and does not need GIC interface base addresses to be configured.
The secure code load address is initially being pointed to 0x0 in the
handoff parameters, which is different from the default or user-provided
load address of 0x60000000. In this case, set up the PC to the
requested BL32_BASE address to ensure that the secure code is loaded
and executed from the correct location.
Change-Id: I58fe256dc9d6be5cee384c5ebb9baca2737c02a6
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal platform. TSP is a component for testing and validating
secure OS and trusted execution environments.
If a BL32 image is present, then there must be a matching Secure-
EL1 Payload Dispatcher (SPD) service called TSPD, this service
is responsible for Initializing the TSP. During initialization that
service must register a function to carry out initialization of
BL32 once the runtime services are fully initialized. BL31 invokes
such a registered function to initialize BL32 before running BL33.
The GICv3 driver is initialized in EL3 and does not need to be
initialized again in SEL1 GICv3 driver is initialized in EL3
This is because the S-EL1 can use GIC system registers to manage
interrupts and does not need GIC interface base addresses to be
configured.
The secure code load address is initially being pointed to 0x0
in the handoff parameters, which is different from the default
or user-provided load address of 0x60000000. In this case, set up
the PC to the requested BL32_BASE address to ensure that the secure
code is loaded and executed from the correct location.
Change-Id: Ida0fc6467a10bfde8927ff9b3755a83f3e16f068
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Updated the generic TSP makefile in the common path for reuse in
different platforms.
Change-Id: Idd14675bc547e0a4a95132653a181e7ff39a547a
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Commit(3547270f5 refactor(build): reorder platform Makefile
evaluation) re-ordered platform makefile inclusion before
arch_features evaluations, but then it fails to remove the dependency
that were moved and thus have double evaluation of some build
variables apparently this breaks BUILD_PLAT.
Additionally remove duplicate checks in SPMD similar checks are in
place in main level makefile.
Change-Id: I5a71624fc43977054467ec6502ce359fb1d08838
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
As per SDEI spec (section 5.1.14.1), SDEI_INTERRUPT_BIND interface
expects a valid PPI or SPI. SGI's are not allowed to be bounded.
Current check in the code only checks for an SGI and returns invalid
ID. This check is insufficient as it will not catch architecturally
invalid interrupt IDs.
Modify the check to ensure that interrupt is either PPI or SPI.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I52eb0a6d7f88a12f6816cff9b68fb3a7ca12cbb7
The error code for plat_core_pos_by_mpidr() for an invalid mpidr should
be -1 as mandated by portig guide, but for tegra t186 return value is
PSCI_E_NOT_PRESENT (-7) even though the comment at top of function says
that it should return -1.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I2b69bc1a56f7966f21b2a3c89c515ebde41e3eb8
