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fix(cpus): workaround for Neoverse N2 erratum 2346952

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Neoverse N2 erratum 2346952 is a Cat B erratum that applies to all
revisions <= r0p2 and is fixed in r0p3.
The workaround is to set L2 TQ size statically to it's full size.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: I03c3cf1f951fbc906fdebcb99a523c5ac8ba055d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
This commit is contained in:
Bipin Ravi 2023-10-17 05:56:01 -05:00 • committed by laurenw-arm
parent 857c764325
commit 6cb8be17a5
5 changed files with 30 additions and 8 deletions
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4
docs/design/cpu-specific-build-macros.rst
View file

@ -655,6 +655,10 @@ For Neoverse N2, the following errata build flags are defined :
CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
r0p1.
- ``ERRATA_N2_2346952``: This applies errata 2346952 workaround to Neoverse-N2
CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU,
it is fixed in r0p3.
- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open.

5
include/lib/cpus/aarch64/neoverse_n2.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2022, Arm Limited. All rights reserved.
* Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -65,5 +65,8 @@
#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
#define CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0)
#define CPUECTLR2_EL1_TXREQ_LSB U(0)
#define CPUECTLR2_EL1_TXREQ_WIDTH U(3)
#endif /* NEOVERSE_N2_H */

10
lib/cpus/aarch64/neoverse_n2.S
View file

@ -165,6 +165,16 @@ workaround_runtime_end neoverse_n2, ERRATUM(2326639)
check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0)
workaround_runtime_start neoverse_n2, ERRATUM(2346952), ERRATA_N2_2346952
/* Set TXREQ to STATIC and full L2 TQ size */
mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
mov x0, #CPUECTLR2_EL1_TXREQ_STATIC_FULL
bfi x1, x0, #CPUECTLR2_EL1_TXREQ_LSB, #CPUECTLR2_EL1_TXREQ_WIDTH
msr NEOVERSE_N2_CPUECTLR2_EL1, x1
workaround_runtime_end neoverse_n2, ERRATUM(2346952)
check_erratum_ls neoverse_n2, ERRATUM(2346952), CPU_REV(0, 2)
workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738
/* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM
* ST to behave like PLD/PFRM LD and not cause

4
lib/cpus/cpu-ops.mk
View file

@ -660,6 +660,10 @@ CPU_FLAG_LIST += ERRATA_N2_2280757
# applies to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2326639
# Flag to apply erratum 2346952 workaround during reset. This erratum applies
# to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
CPU_FLAG_LIST += ERRATA_N2_2346952
# Flag to apply erratum 2376738 workaround during reset. This erratum applies
# to revision r0p0, r0p1, r0p2, r0p3 of the Neoverse N2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_N2_2376738

15
services/std_svc/errata_abi/errata_abi_main.c
View file

@ -350,14 +350,15 @@ struct em_cpu_list cpu_list[] = {
[9] = {2242415, 0x00, 0x00, ERRATA_N2_2242415},
[10] = {2280757, 0x00, 0x00, ERRATA_N2_2280757},
[11] = {2326639, 0x00, 0x00, ERRATA_N2_2326639},
[12] = {2376738, 0x00, 0x03, ERRATA_N2_2376738},
[13] = {2388450, 0x00, 0x00, ERRATA_N2_2388450},
[14] = {2728475, 0x00, 0x02, ERRATA_N2_2728475, \
[12] = {2346952, 0x00, 0x02, ERRATA_N2_2346952},
[13] = {2376738, 0x00, 0x00, ERRATA_N2_2376738},
[14] = {2388450, 0x00, 0x00, ERRATA_N2_2388450},
[15] = {2728475, 0x00, 0x02, ERRATA_N2_2728475, \
ERRATA_NON_ARM_INTERCONNECT},
[15] = {2743014, 0x00, 0x02, ERRATA_N2_2743014},
[16] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
[17] = {2779511, 0x00, 0x02, ERRATA_N2_2779511},
[18 ... ERRATA_LIST_END] = UNDEF_ERRATA,
[16] = {2743014, 0x00, 0x02, ERRATA_N2_2743014},
[17] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
[18] = {2779511, 0x00, 0x02, ERRATA_N2_2779511},
[19 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_N2_H_INC */