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fix(cpus): workaround for Cortex-X2 erratum 2742423
Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all revisions <= r2p1 and is still open. The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01. SDEN documentation: https://developer.arm.com/documentation/SDEN-1775100/latest Change-Id: I03897dc2a7f908937612c2b66ce7a043c1b7575d Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
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4 changed files with 19 additions and 2 deletions
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@ -733,6 +733,10 @@ For Cortex-X2, the following errata build flags are defined :
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This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is
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still open.
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- ``ERRATA_X2_2742423``: This applies errata 2742423 workaround to Cortex-X2
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CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
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CPU and is still open.
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- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to Cortex-X2
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CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
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CPU and is still open.
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@ -118,6 +118,14 @@ workaround_reset_end cortex_x2, ERRATUM(2371105)
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check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0)
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workaround_reset_start cortex_x2, ERRATUM(2742423), ERRATA_X2_2742423
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/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
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sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(55)
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sysreg_bit_clear CORTEX_X2_CPUACTLR5_EL1, BIT(56)
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workaround_reset_end cortex_x2, ERRATUM(2742423)
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check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1)
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workaround_reset_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515
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/* dsb before isb of power down sequence */
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dsb sy
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@ -743,6 +743,10 @@ CPU_FLAG_LIST += ERRATA_X2_2371105
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# and is still open.
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CPU_FLAG_LIST += ERRATA_X2_2701952
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# Flag to apply erratum 2742423 workaround during reset. This erratum applies
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# to revisions r0p0, r1p0, r2p0 and r2p1 of the Cortex-X2 cpu and is still open.
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CPU_FLAG_LIST += ERRATA_X2_2742423
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# Flag to apply erratum 2768515 workaround during power down. This erratum
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# applies to revision r0p0, r1p0, r2p0 and r2p1 of the Cortex-X2 cpu and is
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# still open.
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@ -380,8 +380,9 @@ struct em_cpu_list cpu_list[] = {
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[8] = {2371105, 0x00, 0x20, ERRATA_X2_2371105},
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[9] = {2701952, 0x00, 0x21, ERRATA_X2_2701952, \
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ERRATA_NON_ARM_INTERCONNECT},
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[10] = {2768515, 0x00, 0x21, ERRATA_X2_2768515},
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[11 ... ERRATA_LIST_END] = UNDEF_ERRATA,
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[10] = {2742423, 0x00, 0x21, ERRATA_X2_2742423},
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[11] = {2768515, 0x00, 0x21, ERRATA_X2_2768515},
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[12 ... ERRATA_LIST_END] = UNDEF_ERRATA,
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}
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},
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#endif /* CORTEX_X2_H_INC */
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