Merge changes from topic "xlnx_tsp_feat" into integration

* changes:
  docs(versal-net): add TSP build documentation
  docs(versal): add TSP build documentation
  feat(versal-net): add tsp support
  feat(versal): add tsp support
  refactor(xilinx): add generic TSP makefile
  chore(zynqmp): reorganize tsp code into common path
  refactor(xilinx): rename platform function to generic name

docs/plat/xilinx-versal-net.rst

@@ -14,6 +14,11 @@ To build:
 make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net bl31
 ```
 
+To build bl32 TSP you have to rebuild bl31 too
+```bash
+make CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net SPD=tspd RESET_TO_BL31=1 bl31 bl32
+```
+
 To build TF-A for JTAG DCC console:
 ```bash
 make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal_net VERSAL_NET_CONSOLE=dcc bl31

docs/plat/xilinx-versal.rst

@@ -19,6 +19,11 @@ To build ATF for different platform (supported are "silicon"(default) and "versa
 make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal VERSAL_PLATFORM=versal_virt bl31
 ```
 
+To build bl32 TSP you have to rebuild bl31 too
+```bash
+make CROSS_COMPILE=aarch64-none-elf- PLAT=versal SPD=tspd RESET_TO_BL31=1 bl31 bl32
+```
+
 To build TF-A for JTAG DCC console
 ```bash
 make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal bl31 VERSAL_CONSOLE=dcc

plat/xilinx/common/tsp/tsp.mk

@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# TSP source files for AMD-Xilinx platforms
+BL32_SOURCES		+=	plat/common/aarch64/platform_mp_stack.S		\
+				plat/xilinx/common/tsp/tsp_plat_setup.c

plat/xilinx/common/tsp/tsp_plat_setup.c

@@ -1,11 +1,13 @@
 /*
  * Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2023, Advanced Micro Devices. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <common/bl_common.h>
 #include <common/debug.h>
+#include <drivers/arm/pl011.h>
 #include <drivers/console.h>
 #include <plat/arm/common/plat_arm.h>
 #include <platform_tsp.h>
@@ -22,10 +24,24 @@ void tsp_early_platform_setup(void)
 	 * messages from TSP
 	 */
 	static console_t tsp_boot_console;
-	(void)console_cdns_register(UART_BASE,
-				       get_uart_clk(),
-				       UART_BAUDRATE,
-				       &tsp_boot_console);
+	int32_t rc;
+
+#if defined(PLAT_zynqmp)
+	rc = console_cdns_register((uintptr_t)UART_BASE,
+				   (uint32_t)get_uart_clk(),
+				   (uint32_t)UART_BAUDRATE,
+				   &tsp_boot_console);
+#else
+	rc = console_pl011_register((uintptr_t)UART_BASE,
+				    (uint32_t)get_uart_clk(),
+				    (uint32_t)UART_BAUDRATE,
+				    &tsp_boot_console);
+#endif
+
+	if (rc == 0) {
+		panic();
+	}
+
 	console_set_scope(&tsp_boot_console,
 			  CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);
 }
@@ -35,8 +51,16 @@ void tsp_early_platform_setup(void)
  ******************************************************************************/
 void tsp_platform_setup(void)
 {
+/*
+ * For ZynqMP, the GICv2 driver needs to be initialized in S-EL1,
+ * and for other platforms, the GICv3 driver is initialized in EL3.
+ * This is because S-EL1 can use GIC system registers to manage
+ * interrupts and does not need to be initialized again in SEL1.
+ */
+#if defined(PLAT_zynqmp)
 	plat_arm_gic_driver_init();
 	plat_arm_gic_init();
+#endif
 }
 
 /*******************************************************************************
@@ -52,12 +76,14 @@ void tsp_plat_arch_setup(void)
 			MT_CODE | MT_SECURE),
 		MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
 			MT_RO_DATA | MT_SECURE),
+#if defined(PLAT_zynqmp) || defined(PLAT_versal)
 		MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
 			BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
 			MT_DEVICE | MT_RW | MT_SECURE),
+#endif
 		{0}
 	};
 
-	setup_page_tables(bl_regions, plat_arm_get_mmap());
+	setup_page_tables(bl_regions, plat_get_mmap());
 	enable_mmu_el1(0);
 }

plat/xilinx/versal/aarch64/versal_common.c

@@ -33,7 +33,7 @@ const mmap_region_t plat_versal_mmap[] = {
 	{ 0 }
 };
 
-const mmap_region_t *plat_versal_get_mmap(void)
+const mmap_region_t *plat_get_mmap(void)
 {
 	return plat_versal_mmap;
 }

plat/xilinx/versal/bl31_versal_setup.c

@@ -115,6 +115,19 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 		panic();
 	} else {
 		INFO("BL31: PLM to TF-A handover success %u\n", ret);
+
+		/*
+		 * The BL32 load address is indicated as 0x0 in the handoff
+		 * parameters, which is different from the default/user-provided
+		 * load address of 0x60000000 but the flags are correctly
+		 * configured. Consequently, in this scenario, set the PC
+		 * to the requested BL32_BASE address.
+		 */
+
+		/* TODO: Remove the following check once this is fixed from PLM */
+		if (bl32_image_ep_info.pc == 0 && bl32_image_ep_info.spsr != 0) {
+			bl32_image_ep_info.pc = (uintptr_t)BL32_BASE;
+		}
 	}
 
 	NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
@@ -218,6 +231,6 @@ void bl31_plat_arch_setup(void)
 		{0}
 	};
 
-	setup_page_tables(bl_regions, plat_versal_get_mmap());
+	setup_page_tables(bl_regions, plat_get_mmap());
 	enable_mmu(0);
 }

plat/xilinx/versal/include/plat_private.h

@@ -20,7 +20,7 @@ typedef struct versal_intr_info_type_el3 {
 uint32_t get_uart_clk(void);
 void versal_config_setup(void);
 
-const mmap_region_t *plat_versal_get_mmap(void);
+const mmap_region_t *plat_get_mmap(void);
 
 extern uint32_t platform_id, platform_version;
 

plat/xilinx/versal/include/versal_def.h

@@ -48,6 +48,7 @@
  * IRQ constants
  ******************************************************************************/
 #define VERSAL_IRQ_SEC_PHY_TIMER		U(29)
+#define ARM_IRQ_SEC_PHY_TIMER	29
 
 /*******************************************************************************
  * CCI-400 related constants

plat/xilinx/versal/tsp/tsp-versal.mk

@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# TSP source files specific to Versal platform
+
+PLAT_XILINX_COMMON := plat/xilinx/common/
+
+include ${PLAT_XILINX_COMMON}/tsp/tsp.mk

plat/xilinx/versal_net/aarch64/versal_net_common.c

@@ -34,7 +34,7 @@ const mmap_region_t plat_versal_net_mmap[] = {
 	{ 0 }
 };
 
-const mmap_region_t *plat_versal_net_get_mmap(void)
+const mmap_region_t *plat_get_mmap(void)
 {
 	return plat_versal_net_mmap;
 }

plat/xilinx/versal_net/bl31_versal_net_setup.c

@@ -131,6 +131,19 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 		}
 
 		INFO("BL31: PLM to TF-A handover success\n");
+
+		/*
+		 * The BL32 load address is indicated as 0x0 in the handoff
+		 * parameters, which is different from the default/user-provided
+		 * load address of 0x60000000 but the flags are correctly
+		 * configured. Consequently, in this scenario, set the PC
+		 * to the requested BL32_BASE address.
+		 */
+
+		/* TODO: Remove the following check once this is fixed from PLM */
+		if (bl32_image_ep_info.pc == 0 && bl32_image_ep_info.spsr != 0) {
+			bl32_image_ep_info.pc = (uintptr_t)BL32_BASE;
+		}
 	} else {
 		INFO("BL31: setting up default configs\n");
 
@@ -234,6 +247,6 @@ void bl31_plat_arch_setup(void)
 		{0}
 	};
 
-	setup_page_tables(bl_regions, plat_versal_net_get_mmap());
+	setup_page_tables(bl_regions, plat_get_mmap());
 	enable_mmu(0);
 }

plat/xilinx/versal_net/include/plat_private.h

@@ -20,7 +20,7 @@ typedef struct versal_intr_info_type_el3 {
 void versal_net_config_setup(void);
 uint32_t get_uart_clk(void);
 
-const mmap_region_t *plat_versal_net_get_mmap(void);
+const mmap_region_t *plat_get_mmap(void);
 
 void plat_versal_net_gic_driver_init(void);
 void plat_versal_net_gic_init(void);

plat/xilinx/versal_net/include/versal_net_def.h

@@ -128,6 +128,7 @@
  * IRQ constants
  ******************************************************************************/
 #define VERSAL_NET_IRQ_SEC_PHY_TIMER	U(29)
+#define ARM_IRQ_SEC_PHY_TIMER	29
 
 /*******************************************************************************
  * UART related constants

plat/xilinx/versal_net/tsp/tsp-versal_net.mk

@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# TSP source files specific to Versal NET platform
+
+PLAT_XILINX_COMMON := plat/xilinx/common/
+
+include ${PLAT_XILINX_COMMON}/tsp/tsp.mk
+
+BL32_SOURCES		+=	plat/xilinx/versal_net/plat_topology.c		\
+				${XLAT_TABLES_LIB_SRCS}

plat/xilinx/zynqmp/aarch64/zynqmp_common.c

@@ -27,13 +27,18 @@
  * This doesn't include TZRAM as the 'mem_layout' argument passed to
  * configure_mmu_elx() will give the available subset of that,
  */
-const mmap_region_t plat_arm_mmap[] = {
+const mmap_region_t plat_zynqmp_mmap[] = {
 	{ DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
 	{ DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
 	{ CRF_APB_BASE, CRF_APB_BASE, CRF_APB_SIZE, MT_DEVICE | MT_RW | MT_SECURE },
 	{0}
 };
 
+const mmap_region_t *plat_get_mmap(void)
+{
+	return plat_zynqmp_mmap;
+}
+
 static uint32_t zynqmp_get_silicon_ver(void)
 {
 	static unsigned int ver;

plat/xilinx/zynqmp/bl31_zynqmp_setup.c

@@ -219,6 +219,6 @@ void bl31_plat_arch_setup(void)
 
 	custom_mmap_add();
 
-	setup_page_tables(bl_regions, plat_arm_get_mmap());
+	setup_page_tables(bl_regions, plat_get_mmap());
 	enable_mmu_el3(0);
 }

plat/xilinx/zynqmp/include/plat_private.h

@@ -13,9 +13,12 @@
 #include <bl31/interrupt_mgmt.h>
 #include <common/bl_common.h>
 #include <drivers/cadence/cdns_uart.h>
+#include <lib/xlat_tables/xlat_tables.h>
 
 void zynqmp_config_setup(void);
 
+const mmap_region_t *plat_get_mmap(void);
+
 uint32_t zynqmp_calc_core_pos(u_register_t mpidr);
 
 /* ZynqMP specific functions */

plat/xilinx/zynqmp/tsp/tsp-zynqmp.mk

@@ -4,5 +4,7 @@
 # SPDX-License-Identifier: BSD-3-Clause
 
 # TSP source files specific to ZynqMP platform
-BL32_SOURCES		+=	plat/common/aarch64/platform_mp_stack.S		\
-				plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
+
+PLAT_XILINX_COMMON := plat/xilinx/common/
+
+include ${PLAT_XILINX_COMMON}/tsp/tsp.mk