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https://github.com/ARM-software/arm-trusted-firmware.git
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639b3676cc
Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx Versal NET platform. TSP is a component for testing and validating secure OS and trusted execution environments. If a BL32 image is present, then there must be a matching Secure-EL1 Payload Dispatcher (SPD) service called TSPD, this service is responsible for Initializing the TSP. During initialization that service must register a function to carry out initialization of BL32 once the runtime services are fully initialized. BL31 invokes such a registered function to initialize BL32 before running BL33. The GICv3 driver is initialized in EL3 and does not need to be initialized again in SEL1 GICv3 driver is initialized in EL3 This is because the S-EL1 can use GIC system registers to manage interrupts and does not need GIC interface base addresses to be configured. The secure code load address is initially being pointed to 0x0 in the handoff parameters, which is different from the default or user-provided load address of 0x60000000. In this case, set up the PC to the requested BL32_BASE address to ensure that the secure code is loaded and executed from the correct location. Change-Id: I58fe256dc9d6be5cee384c5ebb9baca2737c02a6 Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
169 lines
6 KiB
C
169 lines
6 KiB
C
/*
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* Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef VERSAL_NET_DEF_H
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#define VERSAL_NET_DEF_H
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#include <plat/arm/common/smccc_def.h>
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#include <plat/common/common_def.h>
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#define MAX_INTR_EL3 2
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/* List all consoles */
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#define VERSAL_NET_CONSOLE_ID_pl011 U(1)
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#define VERSAL_NET_CONSOLE_ID_pl011_0 U(1)
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#define VERSAL_NET_CONSOLE_ID_pl011_1 U(2)
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#define VERSAL_NET_CONSOLE_ID_dcc U(3)
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#define CONSOLE_IS(con) (VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE)
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/* List all platforms */
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#define VERSAL_NET_SILICON U(0)
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#define VERSAL_NET_SPP U(1)
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#define VERSAL_NET_EMU U(2)
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#define VERSAL_NET_QEMU U(3)
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#define VERSAL_NET_QEMU_COSIM U(7)
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/* For platform detection */
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#define PMC_TAP U(0xF11A0000)
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#define PMC_TAP_VERSION (PMC_TAP + 0x4U)
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# define PLATFORM_MASK GENMASK(27U, 24U)
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# define PLATFORM_VERSION_MASK GENMASK(31U, 28U)
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/* Global timer reset */
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#define PSX_CRF U(0xEC200000)
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#define ACPU0_CLK_CTRL U(0x10C)
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#define ACPU_CLK_CTRL_CLKACT BIT(25)
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#define RST_APU0_OFFSET U(0x300)
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#define RST_APU_COLD_RESET BIT(0)
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#define RST_APU_WARN_RESET BIT(4)
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#define RST_APU_CLUSTER_COLD_RESET BIT(8)
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#define RST_APU_CLUSTER_WARM_RESET BIT(9)
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#define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C)
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#define APU_PCLI (0xECB10000ULL)
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#define APU_PCLI_CPU_STEP (0x30ULL)
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#define APU_PCLI_CLUSTER_CPU_STEP (4ULL * APU_PCLI_CPU_STEP)
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#define APU_PCLI_CLUSTER_OFFSET U(0x8000)
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#define APU_PCLI_CLUSTER_STEP U(0x1000)
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#define PCLI_PREQ_OFFSET U(0x4)
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#define PREQ_CHANGE_REQUEST BIT(0)
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#define PCLI_PSTATE_OFFSET U(0x8)
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#define PCLI_PSTATE_VAL_SET U(0x48)
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#define PCLI_PSTATE_VAL_CLEAR U(0x38)
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/* Firmware Image Package */
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#define VERSAL_NET_PRIMARY_CPU U(0)
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#define CORE_0_ISR_WAKE_OFFSET (0x00000020ULL)
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#define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \
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(APU_PCLI_CPU_STEP * (cpu_id))))
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#define APU_PCIL_CORE_X_ISR_WAKE_MASK (0x00000001U)
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#define CORE_0_IEN_WAKE_OFFSET (0x00000028ULL)
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#define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \
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(APU_PCLI_CPU_STEP * (cpu_id))))
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#define APU_PCIL_CORE_X_IEN_WAKE_MASK (0x00000001U)
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#define CORE_0_IDS_WAKE_OFFSET (0x0000002CULL)
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#define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \
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(APU_PCLI_CPU_STEP * (cpu_id))))
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#define APU_PCIL_CORE_X_IDS_WAKE_MASK (0x00000001U)
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#define CORE_0_ISR_POWER_OFFSET (0x00000010ULL)
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#define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \
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(APU_PCLI_CPU_STEP * (cpu_id))))
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#define APU_PCIL_CORE_X_ISR_POWER_MASK U(0x00000001)
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#define CORE_0_IEN_POWER_OFFSET (0x00000018ULL)
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#define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \
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(APU_PCLI_CPU_STEP * (cpu_id))))
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#define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U)
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#define CORE_0_IDS_POWER_OFFSET (0x0000001CULL)
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#define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \
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(APU_PCLI_CPU_STEP * (cpu_id))))
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#define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U)
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#define CORE_PWRDN_EN_BIT_MASK (0x1U)
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/*******************************************************************************
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* memory map related constants
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******************************************************************************/
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/* IPP 1.2/SPP 0.9 mapping */
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#define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */
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#define DEVICE0_SIZE U(0x08000000)
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#define DEVICE1_BASE U(0xE2000000) /* gic */
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#define DEVICE1_SIZE U(0x00800000)
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#define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */
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#define DEVICE2_SIZE U(0x01000000)
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#define CRF_BASE U(0xFD1A0000)
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#define CRF_SIZE U(0x00600000)
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#define IPI_BASE U(0xEB300000)
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#define IPI_SIZE U(0x00100000)
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/* CRL */
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#define VERSAL_NET_CRL U(0xEB5E0000)
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#define VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C)
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#define VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET U(0x348)
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#define VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U)
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/* IOU SCNTRS */
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#define VERSAL_NET_IOU_SCNTRS U(0xEC920000)
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#define VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0)
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#define VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20)
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#define VERSAL_NET_IOU_SCNTRS_CONTROL_EN U(1)
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#define APU_CLUSTER0 U(0xECC00000)
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#define APU_RVBAR_L_0 U(0x40)
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#define APU_RVBAR_H_0 U(0x44)
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#define APU_CLUSTER_STEP U(0x100000)
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#define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504)
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/*******************************************************************************
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* IRQ constants
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******************************************************************************/
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#define VERSAL_NET_IRQ_SEC_PHY_TIMER U(29)
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#define ARM_IRQ_SEC_PHY_TIMER 29
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define VERSAL_NET_UART0_BASE U(0xF1920000)
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#define VERSAL_NET_UART1_BASE U(0xF1930000)
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#define UART_BAUDRATE 115200
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#if CONSOLE_IS(pl011_1)
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#define UART_BASE VERSAL_NET_UART1_BASE
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#else
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/* Default console is UART0 */
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#define UART_BASE VERSAL_NET_UART0_BASE
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#endif
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/* Processor core device IDs */
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#define PM_DEV_CLUSTER0_ACPU_0 (0x1810C0AFU)
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#define PM_DEV_CLUSTER0_ACPU_1 (0x1810C0B0U)
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#define PM_DEV_CLUSTER0_ACPU_2 (0x1810C0B1U)
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#define PM_DEV_CLUSTER0_ACPU_3 (0x1810C0B2U)
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#define PM_DEV_CLUSTER1_ACPU_0 (0x1810C0B3U)
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#define PM_DEV_CLUSTER1_ACPU_1 (0x1810C0B4U)
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#define PM_DEV_CLUSTER1_ACPU_2 (0x1810C0B5U)
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#define PM_DEV_CLUSTER1_ACPU_3 (0x1810C0B6U)
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#define PM_DEV_CLUSTER2_ACPU_0 (0x1810C0B7U)
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#define PM_DEV_CLUSTER2_ACPU_1 (0x1810C0B8U)
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#define PM_DEV_CLUSTER2_ACPU_2 (0x1810C0B9U)
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#define PM_DEV_CLUSTER2_ACPU_3 (0x1810C0BAU)
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#define PM_DEV_CLUSTER3_ACPU_0 (0x1810C0BBU)
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#define PM_DEV_CLUSTER3_ACPU_1 (0x1810C0BCU)
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#define PM_DEV_CLUSTER3_ACPU_2 (0x1810C0BDU)
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#define PM_DEV_CLUSTER3_ACPU_3 (0x1810C0BEU)
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#endif /* VERSAL_NET_DEF_H */
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