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Refactor two platform specific functions, plat_versal_get_mmap() and plat_versal_net_get_mmap(), to use a more generic function name plat_get_mmap(). The function can be used in the common code to obtain memory region. Change-Id: I3eeb24aff217eef30af60a7742cbebe9d3b2edce Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
152 lines
3.8 KiB
C
152 lines
3.8 KiB
C
/*
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* Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
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* Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <plat_common.h>
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#include <plat_ipi.h>
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#include <plat_private.h>
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#include <versal_net_def.h>
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uint32_t platform_id, platform_version;
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/*
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* Table of regions to map using the MMU.
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* This doesn't include TZRAM as the 'mem_layout' argument passed to
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* configure_mmu_elx() will give the available subset of that,
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*/
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const mmap_region_t plat_versal_net_mmap[] = {
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MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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{ 0 }
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};
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const mmap_region_t *plat_get_mmap(void)
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{
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return plat_versal_net_mmap;
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}
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/* For saving cpu clock for certain platform */
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uint32_t cpu_clock;
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char *board_name_decode(void)
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{
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switch (platform_id) {
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case VERSAL_NET_SPP:
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return "IPP";
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case VERSAL_NET_EMU:
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return "EMU";
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case VERSAL_NET_SILICON:
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return "Silicon";
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case VERSAL_NET_QEMU:
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return "QEMU";
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default:
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return "Unknown";
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}
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}
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void board_detection(void)
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{
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uint32_t version;
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version = mmio_read_32(PMC_TAP_VERSION);
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platform_id = FIELD_GET(PLATFORM_MASK, version);
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platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
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if (platform_id == VERSAL_NET_QEMU_COSIM) {
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platform_id = VERSAL_NET_QEMU;
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}
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if ((platform_id == VERSAL_NET_SPP) ||
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(platform_id == VERSAL_NET_EMU) ||
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(platform_id == VERSAL_NET_QEMU)) {
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/*
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* 9 is diff for
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* 0 means 0.9 version
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* 1 means 1.0 version
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* 2 means 1.1 version
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* etc,
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*/
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platform_version += 9U;
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}
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/* Make sure that console is setup to see this message */
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VERBOSE("Platform id: %d version: %d.%d\n", platform_id,
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platform_version / 10U, platform_version % 10U);
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}
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uint32_t get_uart_clk(void)
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{
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uint32_t uart_clock;
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switch (platform_id) {
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case VERSAL_NET_SPP:
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uart_clock = 1000000;
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break;
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case VERSAL_NET_EMU:
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uart_clock = 25000000;
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break;
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case VERSAL_NET_QEMU:
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uart_clock = 25000000;
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break;
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case VERSAL_NET_SILICON:
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uart_clock = 100000000;
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break;
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default:
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panic();
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}
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return uart_clock;
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}
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void versal_net_config_setup(void)
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{
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uint32_t val;
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uintptr_t crl_base, iou_scntrs_base, psx_base;
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crl_base = VERSAL_NET_CRL;
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iou_scntrs_base = VERSAL_NET_IOU_SCNTRS;
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psx_base = PSX_CRF;
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/* Reset for system timestamp generator in FPX */
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mmio_write_32(psx_base + PSX_CRF_RST_TIMESTAMP_OFFSET, 0);
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/* Global timer init - Program time stamp reference clk */
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val = mmio_read_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET);
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val |= VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
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mmio_write_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET, val);
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/* Clear reset of timestamp reg */
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mmio_write_32(crl_base + VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET, 0);
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/* Program freq register in System counter and enable system counter. */
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mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET,
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cpu_clock);
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mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
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VERSAL_NET_IOU_SCNTRS_CONTROL_EN);
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generic_delay_timer_init();
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#if (TFA_NO_PM == 0)
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/* Configure IPI data for versal_net */
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versal_net_ipi_config_table_init();
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#endif
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}
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uint32_t plat_get_syscnt_freq2(void)
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{
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return cpu_clock;
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}
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