mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 18:14:24 +00:00
639b3676cc
Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx Versal NET platform. TSP is a component for testing and validating secure OS and trusted execution environments. If a BL32 image is present, then there must be a matching Secure-EL1 Payload Dispatcher (SPD) service called TSPD, this service is responsible for Initializing the TSP. During initialization that service must register a function to carry out initialization of BL32 once the runtime services are fully initialized. BL31 invokes such a registered function to initialize BL32 before running BL33. The GICv3 driver is initialized in EL3 and does not need to be initialized again in SEL1 GICv3 driver is initialized in EL3 This is because the S-EL1 can use GIC system registers to manage interrupts and does not need GIC interface base addresses to be configured. The secure code load address is initially being pointed to 0x0 in the handoff parameters, which is different from the default or user-provided load address of 0x60000000. In this case, set up the PC to the requested BL32_BASE address to ensure that the secure code is loaded and executed from the correct location. Change-Id: I58fe256dc9d6be5cee384c5ebb9baca2737c02a6 Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
89 lines
2.6 KiB
C
89 lines
2.6 KiB
C
/*
|
|
* Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.
|
|
* Copyright (c) 2023, Advanced Micro Devices. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#include <common/bl_common.h>
|
|
#include <common/debug.h>
|
|
#include <drivers/arm/pl011.h>
|
|
#include <drivers/console.h>
|
|
#include <plat/arm/common/plat_arm.h>
|
|
#include <platform_tsp.h>
|
|
|
|
#include <plat_private.h>
|
|
|
|
/*******************************************************************************
|
|
* Initialize the UART
|
|
******************************************************************************/
|
|
void tsp_early_platform_setup(void)
|
|
{
|
|
/*
|
|
* Register a different console than already in use to display
|
|
* messages from TSP
|
|
*/
|
|
static console_t tsp_boot_console;
|
|
int32_t rc;
|
|
|
|
#if defined(PLAT_zynqmp)
|
|
rc = console_cdns_register((uintptr_t)UART_BASE,
|
|
(uint32_t)get_uart_clk(),
|
|
(uint32_t)UART_BAUDRATE,
|
|
&tsp_boot_console);
|
|
#else
|
|
rc = console_pl011_register((uintptr_t)UART_BASE,
|
|
(uint32_t)get_uart_clk(),
|
|
(uint32_t)UART_BAUDRATE,
|
|
&tsp_boot_console);
|
|
#endif
|
|
|
|
if (rc == 0) {
|
|
panic();
|
|
}
|
|
|
|
console_set_scope(&tsp_boot_console,
|
|
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* Perform platform specific setup placeholder
|
|
******************************************************************************/
|
|
void tsp_platform_setup(void)
|
|
{
|
|
/*
|
|
* For ZynqMP, the GICv2 driver needs to be initialized in S-EL1,
|
|
* and for other platforms, the GICv3 driver is initialized in EL3.
|
|
* This is because S-EL1 can use GIC system registers to manage
|
|
* interrupts and does not need to be initialized again in SEL1.
|
|
*/
|
|
#if defined(PLAT_zynqmp)
|
|
plat_arm_gic_driver_init();
|
|
plat_arm_gic_init();
|
|
#endif
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* Perform the very early platform specific architectural setup here. At the
|
|
* moment this is only initializes the MMU
|
|
******************************************************************************/
|
|
void tsp_plat_arch_setup(void)
|
|
{
|
|
const mmap_region_t bl_regions[] = {
|
|
MAP_REGION_FLAT(BL32_BASE, BL32_END - BL32_BASE,
|
|
MT_MEMORY | MT_RW | MT_SECURE),
|
|
MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
|
|
MT_CODE | MT_SECURE),
|
|
MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
|
|
MT_RO_DATA | MT_SECURE),
|
|
#if defined(PLAT_zynqmp) || defined(PLAT_versal)
|
|
MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
|
|
BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
|
|
MT_DEVICE | MT_RW | MT_SECURE),
|
|
#endif
|
|
{0}
|
|
};
|
|
|
|
setup_page_tables(bl_regions, plat_get_mmap());
|
|
enable_mmu_el1(0);
|
|
}
|