Replace the dummy implementation of clk_ops.get_rate with a basic
version that only handles the oscillator objects. Subsequent commits
will add more objects to this list.
Change-Id: I8c1bbbfa6b116fdcf5a1f1353bdb52b474bac831
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks can be beneficial, with the peripheral clocks configured after
fully initializing the MMU.
Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add all clock modules as entries in MMU using dynamic regions.
Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The digest size in bytes for sha1/256/384/512 were defined in multiple
places. Refactor the macros into a common header file.
Change-Id: I84ef3561486ff70345ae8c871d5d6e1564574ec2
Signed-off-by: Raghu Krishnamurthy <raghupathyk@nvidia.com>
The DDR clock can be powered by either a PLL or an oscillator. An MC_CGM
mux selects between these two clock sources. A reset block, part of
partition 0, is also connected to this IP block. Therefore, all the
dependencies mentioned above must be configured to have a working clock.
Change-Id: Ia841428db9acb95c59ea851b6afeb0b7ff9230a2
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add the DDR PLL instance and configure it to operate at its maximum
allowed frequency.
Change-Id: I96efd68687de78f70759f631d10a0f611c234c8d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The S32CC-based SoCs are organized in partitions. These are
software-resettable domains in which configuration participates in
MC_CGM, MC_ME, and RDC modules. A partition is an island that may
contain multiple blocks, each of which corresponds to a peripheral or a
core and can, in most cases, be reset individually. This reset structure
results in better device availability. If a fault is detected in a
software reset domain, that domain can be reset separately without
impacting the operation of the rest of the chip.
Change-Id: Ie60dbe151309209e377aa71356dbbd6a4f376a8c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Bring in the implementation for the struct clk_ops->get_parent callback
for the S32G clock driver. The parent is established depending on the
clock object type. Usually, this is determined based on the parent
field, but not always.
Change-Id: I76a3d2636dc23ba2d547d058b8650dd0e99fe1fa
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.
Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or FXOSC oscillators. It has eight outputs (PHIs) and
their frequencies can be controlled programmatically using output
dividers. An additional output clocks the PERIPH DFS using the VCO
frequency of the PERIPH PLL.
Change-Id: I637294b2da94f35e95dc1750dad36c129a276bb9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add all clock modules required to enable the XBAR clock, including the
DFS, its output dividers and MC_CGM muxes.
Change-Id: Ib9cf82c0e40b76863637ed7602c3a09411d17615
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Introduce the MC_CGM0 instance responsible for XBAR and other peripheral
clocks.
Change-Id: Icf1e9ce6e71e4ff446835d1e7b6522bfb6f2b4b6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The DFS modules are connected to the PLL VCO and provide a clock
downstream through a set of output dividers, the frequency of which can
be adjusted programmatically.
Change-Id: Ie945d10fd39e6e40e6c051ccde8486dcfb5bd53f
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add set rate support for fixed divider clock modules of whose role is to
reduce the source frequency by a factor.
Change-Id: I8a29a2c5b1a829db0c396407c3517c9e66caaa93
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
These objects are needed to allow early enablement of the A53 core
clock.
Change-Id: I44d81975c8eba8cc6cfd18aeb6c9b324edaa3f01
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add implementation for ARM PLL divider rate set mechanism.
Change-Id: I78f4418bcbb5ea0a6ef64675e44bd074d2230ea3
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add implementation for ARM PLL rate set mechanism.
Change-Id: Ic859567bd67747f173d425158cdc581801f7446c
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The MC_CGM1 clock objects will participate in A53 clocking.
Change-Id: I7309b630d72ac0ad66df7c299b678454220e0581
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
On S32CC SoCs, the set_parent operation will be used on clock modules
that are mux instances in order to establish the clock source. This will
be used for PLLs and MC_CGM muxes.
Change-Id: I7228d379500ea790459b858da8fc0bdcbed4fd62
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add all the clock objects needed to describe the ARM PLL, which can be
powered by either FXOSC or FIRC oscillators.
Change-Id: I2585ed38178ca1d5c5485adb38af1b3b8d94f1f6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
s32cc_init_early_clks will be used to increase the frequency of the
clocks which have a performance impact on BL2 boot. This set includes
A53, XBAR, DDR and Linflex clocks. For now, it will only contain the
frequency set for FXOSC. More clock management will be added in the next
commits.
Change-Id: Ie85465884de02f5082185f91749f190f40249c2e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The set_rate callback will now be applied to FIRC, FXOSC, and SIRC
oscillators. It is a prerequisite for the upcoming commits that will
utilize this capability.
Change-Id: I82d1545c63b3e15497c1c002ff9ec0d7bf990aa0
Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The oscillator clock objects will be used to describe the FIRC, FXOSC,
and SIRC clocks, all of which are oscillators on S32CC SoCs.
Change-Id: Icf235cc9b8f1d95d2c0051ce9a7655fd120289b8
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The clock IDs are organized into categories, which are determined based
on the first 2 MSB bits for each ID. Currently, there are two big
categories: hardware and software-defined clocks.
The first category refers to clock IDs understood by the S32CC PLL muxes
and MC_CGM module muxes and is immutable. The last category of the
clocks includes software-defined IDs for clocks to allow an easy
representation of the hierarchy.
Change-Id: Idc079feb3ca5f92d8bf337ef09efad006e267088
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
This is a UART controller found on NXP automotive parts.
For instance: S32V, S32G and S32R.
Change-Id: Iff0dd0c379633ac0651e5db287537c87666b57d2
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
This patch is to fix Errata #841119 and #826419 failed apply in linux
because of SMMU_CBn_ACTLR register can't be modified in non-secure
states.
Signed-off-by: Howard Lu <howard.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I2b23e7c8baa809f385917eb45b10ec6b26a9ada8
Removed GICR_CTLR_DPG0_MASK definition from platform GIC header file
as Arm GICv3 header file added its definition.
Change-Id: Ieec43aeef96b9b6c8a7f955a8d145be6e4b183c5
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Add support for Chassis 3.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I85cf68d4f1db81bf344e34dce13799ae173aa23a
bitfield structure maybe has strict-aliasing issue for some compiler,
for example the old code has hang issue for yocto 3.4 toolchain, so
refine the code to avoid to use bitfield structure.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I6b6d7597311240dd6d6b8ca4ce508c69332f9c68
Added offset for register DEVDISR2 and DEVDISR3, added
bit definiton for PORSR1_RCW, and some macro for SVR.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ie49392b89280c6c2c3510fcb4c85d827a1efdac0
Now lx2 which use MT35XU512A supports warm boot, fix the macro
define caused by the commit:
feat(driver/nxp/xspi): add MT35XU02G flash info
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I83eb8cb9a30ac7c7efd5a010acbd03eddebed52b
Define RSTCR_RESET_REQ for Chassis V3.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I5cb7019baae5fe0d06b3d5e65f185f87ee16ad3a
1. Refined struct soc_info_t definition.
2. Refined get_soc_info function.
3. Fixed some SVR persernality value.
4. Refined API to get cluster numbers and cores per cluster.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I3c20611a523516cc63330dce4c925e6cda1e93c4
NXP drivers header files are moved:
- from: drivers/nxp/<xx>/*.h
- to : include/drivers/nxp/<xx>/*.h
To accommodate these changes each drivers makefiles
drivers/nxp/<xx>/xx.mk, are updated.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I3979c509724d87e3d631a03dbafda1ee5ef07d21
NXP SMMU driver API for NXP SoC.
- Currently it supports by-passing SMMU, called only when NXP CAAM
is enabled.
- (TBD) AMQ based SMMU access control: Access Management Qualifiers (AMQ)
advertised by a bus master for a given transaction.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I23a12928ddedb1a2cf4b396606e35c67e016e331
Flexspi driver now introduces read/write/erase APIs for complete flash
size, FAST-READ are by default used and IP bus is used for erase, read
and write using flexspi APIs.
Framework layer is currently embedded in driver itself using flash_info
defines.
Test cases are also added to confirm flash functionality currently under
DEBUG flag.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Change-Id: I755c0f763f6297a35cad6885f84640de50f51bb0
