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feat(nxp-clk): add A53 clock objects

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These objects are needed to allow early enablement of the A53 core
clock.

Change-Id: I44d81975c8eba8cc6cfd18aeb6c9b324edaa3f01
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
This commit is contained in:
Ghennadi Procopciuc 2024-06-12 12:06:36 +03:00
parent de950ef04f
commit 44e2130ab9
3 changed files with 52 additions and 1 deletions
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2
drivers/nxp/clk/s32cc/s32cc_clk_drv.c
View file

@ -152,6 +152,7 @@ static int enable_module(const struct s32cc_clk_obj *module, unsigned int *depth
ret = -ENOTSUP;
break;
case s32cc_pll_out_div_t:
case s32cc_fixed_div_t:
ret = -ENOTSUP;
break;
default:
@ -341,6 +342,7 @@ static int set_module_rate(const struct s32cc_clk_obj *module,
break;
case s32cc_clkmux_t:
case s32cc_shared_clkmux_t:
case s32cc_fixed_div_t:
ret = -ENOTSUP;
break;
default:

26
drivers/nxp/clk/s32cc/s32cc_clk_modules.c
View file

@ -7,6 +7,9 @@
#include <s32cc-clk-modules.h>
#include <s32cc-clk-utils.h>
#define S32CC_A53_MIN_FREQ (48UL * MHZ)
#define S32CC_A53_MAX_FREQ (1000UL * MHZ)
/* Oscillators */
static struct s32cc_osc fxosc =
S32CC_OSC_INIT(S32CC_FXOSC);
@ -48,6 +51,23 @@ static struct s32cc_clkmux cgm1_mux0 =
S32CC_CLK_ARM_PLL_DFS2, 0, 0);
static struct s32cc_clk cgm1_mux0_clk = S32CC_MODULE_CLK(cgm1_mux0);
/* A53_CORE */
static struct s32cc_clk a53_core_clk =
S32CC_FREQ_MODULE_CLK(cgm1_mux0_clk, S32CC_A53_MIN_FREQ,
S32CC_A53_MAX_FREQ);
/* A53_CORE_DIV2 */
static struct s32cc_fixed_div a53_core_div2 =
S32CC_FIXED_DIV_INIT(cgm1_mux0_clk, 2);
static struct s32cc_clk a53_core_div2_clk =
S32CC_FREQ_MODULE_CLK(a53_core_div2, S32CC_A53_MIN_FREQ / 2,
S32CC_A53_MAX_FREQ / 2);
/* A53_CORE_DIV10 */
static struct s32cc_fixed_div a53_core_div10 =
S32CC_FIXED_DIV_INIT(cgm1_mux0_clk, 10);
static struct s32cc_clk a53_core_div10_clk =
S32CC_FREQ_MODULE_CLK(a53_core_div10, S32CC_A53_MIN_FREQ / 10,
S32CC_A53_MAX_FREQ / 10);
static struct s32cc_clk *s32cc_hw_clk_list[5] = {
/* Oscillators */
[S32CC_CLK_ID(S32CC_CLK_FIRC)] = &firc_clk,
@ -63,12 +83,16 @@ static struct s32cc_clk_array s32cc_hw_clocks = {
.n_clks = ARRAY_SIZE(s32cc_hw_clk_list),
};
static struct s32cc_clk *s32cc_arch_clk_list[3] = {
static struct s32cc_clk *s32cc_arch_clk_list[6] = {
/* ARM PLL */
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_MUX)] = &arm_pll_mux_clk,
[S32CC_CLK_ID(S32CC_CLK_ARM_PLL_VCO)] = &arm_pll_vco_clk,
/* MC_CGM1 */
[S32CC_CLK_ID(S32CC_CLK_MC_CGM1_MUX0)] = &cgm1_mux0_clk,
/* A53 */
[S32CC_CLK_ID(S32CC_CLK_A53_CORE)] = &a53_core_clk,
[S32CC_CLK_ID(S32CC_CLK_A53_CORE_DIV2)] = &a53_core_div2_clk,
[S32CC_CLK_ID(S32CC_CLK_A53_CORE_DIV10)] = &a53_core_div10_clk,
};
static struct s32cc_clk_array s32cc_arch_clocks = {

25
include/drivers/nxp/clk/s32cc/s32cc-clk-modules.h
View file

@ -19,6 +19,7 @@ enum s32cc_clkm_type {
s32cc_pll_out_div_t,
s32cc_clkmux_t,
s32cc_shared_clkmux_t,
s32cc_fixed_div_t,
};
enum s32cc_clk_source {
@ -112,6 +113,30 @@ struct s32cc_pll_out_div {
.index = (INDEX), \
}
#define S32CC_PLL_OUT_DIV_INIT(PARENT, INDEX) \
{ \
.desc = { \
.type = s32cc_pll_out_div_t, \
}, \
.parent = &(PARENT).desc, \
.index = (INDEX), \
}
struct s32cc_fixed_div {
struct s32cc_clk_obj desc;
struct s32cc_clk_obj *parent;
uint32_t rate_div;
};
#define S32CC_FIXED_DIV_INIT(PARENT, RATE_DIV) \
{ \
.desc = { \
.type = s32cc_fixed_div_t, \
}, \
.parent = &(PARENT).desc, \
.rate_div = (RATE_DIV), \
}
struct s32cc_clk {
struct s32cc_clk_obj desc;
struct s32cc_clk_obj *module;