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https://github.com/ARM-software/arm-trusted-firmware.git
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feat(imx93): add the trdc driver
Add the trdc driver that is used on NXP i.MX9 family Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ie1fd86b76564fa7e20d74d5b4dbfe7ea0ee851fc
This commit is contained in:
Jacky Bai
parent
9f38eb8143
commit
2935291009
2 changed files with 537 additions and 0 deletions
365
drivers/nxp/trdc/imx_trdc.c
Normal file
365
drivers/nxp/trdc/imx_trdc.c
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/*
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stdbool.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/nxp/trdc/imx_trdc.h>
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#include <lib/mmio.h>
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int trdc_mda_set_cpu(uintptr_t trdc_base, uint32_t mda_inst,
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uint32_t mda_reg, uint8_t sa, uint8_t dids,
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uint8_t did, uint8_t pe, uint8_t pidm, uint8_t pid)
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{
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uint32_t val = mmio_read_32(trdc_base + MDAC_W_X(mda_inst, mda_reg));
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/* invalid: config non-cpu master with cpu config format. */
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if ((val & MDA_DFMT) != 0U) {
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return -EINVAL;
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}
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val = MDA_VLD | MDA_DFMT0_DID(pid) | MDA_DFMT0_PIDM(pidm) | MDA_DFMT0_PE(pe) |
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MDA_DFMT0_SA(sa) | MDA_DFMT0_DIDS(dids) | MDA_DFMT0_DID(did);
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mmio_write_32(trdc_base + MDAC_W_X(mda_inst, mda_reg), val);
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return 0;
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}
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int trdc_mda_set_noncpu(uintptr_t trdc_base, uint32_t mda_inst,
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bool did_bypass, uint8_t sa, uint8_t pa,
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uint8_t did)
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{
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uint32_t val = mmio_read_32(trdc_base + MDAC_W_X(mda_inst, 0));
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/* invalid: config cpu master with non-cpu config format. */
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if ((val & MDA_DFMT) == 0U) {
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return -EINVAL;
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}
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val = MDA_VLD | MDA_DFMT1_SA(sa) | MDA_DFMT1_PA(pa) | MDA_DFMT1_DID(did) |
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MDA_DFMT1_DIDB(did_bypass ? 1U : 0U);
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mmio_write_32(trdc_base + MDAC_W_X(mda_inst, 0), val);
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return 0;
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}
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static uintptr_t trdc_get_mbc_base(uintptr_t trdc_reg, uint32_t mbc_x)
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{
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struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
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uint32_t mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0);
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if (mbc_x >= mbc_num) {
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return 0U;
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}
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return trdc_reg + 0x10000 + 0x2000 * mbc_x;
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}
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static uintptr_t trdc_get_mrc_base(uintptr_t trdc_reg, uint32_t mrc_x)
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{
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struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
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uint32_t mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0);
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uint32_t mrc_num = MRC_NUM(trdc_base->trdc_hwcfg0);
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if (mrc_x >= mrc_num) {
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return 0U;
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}
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return trdc_reg + 0x10000 + 0x2000 * mbc_num + 0x1000 * mrc_x;
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}
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uint32_t trdc_mbc_blk_num(uintptr_t trdc_reg, uint32_t mbc_x, uint32_t mem_x)
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{
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uint32_t glbcfg;
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struct mbc_mem_dom *mbc_dom;
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struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
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if (mbc_base == NULL) {
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return 0;
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}
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/* only first dom has the glbcfg */
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mbc_dom = &mbc_base->mem_dom[0];
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glbcfg = mmio_read_32((uintptr_t)&mbc_dom->mem_glbcfg[mem_x]);
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return MBC_BLK_NUM(glbcfg);
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}
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uint32_t trdc_mrc_rgn_num(uintptr_t trdc_reg, uint32_t mrc_x)
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{
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uint32_t glbcfg;
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struct mrc_rgn_dom *mrc_dom;
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struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x);
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if (mrc_base == NULL) {
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return 0;
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}
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/* only first dom has the glbcfg */
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mrc_dom = &mrc_base->mrc_dom[0];
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glbcfg = mmio_read_32((uintptr_t)&mrc_dom->mrc_glbcfg[0]);
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return MBC_BLK_NUM(glbcfg);
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}
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int trdc_mbc_set_control(uintptr_t trdc_reg, uint32_t mbc_x,
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uint32_t glbac_id, uint32_t glbac_val)
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{
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struct mbc_mem_dom *mbc_dom;
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struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
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if (mbc_base == NULL || glbac_id >= GLBAC_NUM) {
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return -EINVAL;
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}
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/* only first dom has the glbac */
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mbc_dom = &mbc_base->mem_dom[0];
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mmio_write_32((uintptr_t)&mbc_dom->memn_glbac[glbac_id], glbac_val);
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return 0;
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}
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int trdc_mbc_blk_config(uintptr_t trdc_reg, uint32_t mbc_x,
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uint32_t dom_x, uint32_t mem_x, uint32_t blk_x,
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bool sec_access, uint32_t glbac_id)
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{
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uint32_t *cfg_w;
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uint32_t index, offset, val;
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struct mbc_mem_dom *mbc_dom;
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struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
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if (mbc_base == NULL || glbac_id >= GLBAC_NUM) {
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return -EINVAL;
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}
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mbc_dom = &mbc_base->mem_dom[dom_x];
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switch (mem_x) {
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case 0:
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cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8];
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break;
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case 1:
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cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8];
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break;
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case 2:
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cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8];
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break;
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case 3:
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cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8];
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break;
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default:
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return -EINVAL;
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};
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index = blk_x % 8;
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offset = index * 4;
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val = mmio_read_32((uintptr_t)cfg_w);
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val &= ~(0xF << offset);
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/*
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* MBC0-3
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* Global 0, 0x7777 secure pri/user read/write/execute,
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* S400 has already set it. So select MBC0_MEMN_GLBAC0
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*/
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if (sec_access) {
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val |= ((0x0 | (glbac_id & 0x7)) << offset);
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mmio_write_32((uintptr_t)cfg_w, val);
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} else {
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/* nse bit set */
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val |= ((0x8 | (glbac_id & 0x7)) << offset);
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mmio_write_32((uintptr_t)cfg_w, val);
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}
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return 0;
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}
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int trdc_mrc_set_control(uintptr_t trdc_reg, uint32_t mrc_x,
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uint32_t glbac_id, uint32_t glbac_val)
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{
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struct mrc_rgn_dom *mrc_dom;
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struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x);
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if (mrc_base == NULL || glbac_id >= GLBAC_NUM) {
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return -EINVAL;
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}
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/* only first dom has the glbac */
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mrc_dom = &mrc_base->mrc_dom[0];
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mmio_write_32((uintptr_t)&mrc_dom->memn_glbac[glbac_id], glbac_val);
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return 0;
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}
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int trdc_mrc_rgn_config(uintptr_t trdc_reg, uint32_t mrc_x,
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uint32_t dom_x, uint32_t rgn_id,
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uint32_t addr_start, uint32_t addr_size,
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bool sec_access, uint32_t glbac_id)
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{
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uint32_t *desc_w;
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uint32_t addr_end;
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struct mrc_rgn_dom *mrc_dom;
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struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x);
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if (mrc_base == NULL || glbac_id >= GLBAC_NUM || rgn_id >= MRC_REG_ALL) {
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return -EINVAL;
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}
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mrc_dom = &mrc_base->mrc_dom[dom_x];
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addr_end = addr_start + addr_size - 1;
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addr_start &= ~0x3fff;
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addr_end &= ~0x3fff;
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desc_w = &mrc_dom->rgn_desc_words[rgn_id][0];
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if (sec_access) {
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mmio_write_32((uintptr_t)desc_w, addr_start | (glbac_id & 0x7));
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mmio_write_32((uintptr_t)(desc_w + 1), addr_end | 0x1);
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} else {
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mmio_write_32((uintptr_t)desc_w, addr_start | (glbac_id & 0x7));
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mmio_write_32((uintptr_t)(desc_w + 1), (addr_end | 0x1 | 0x10));
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}
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return 0;
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}
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bool trdc_mrc_enabled(uintptr_t mrc_base)
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{
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return (mmio_read_32(mrc_base) & BIT(15));
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}
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bool trdc_mbc_enabled(uintptr_t mbc_base)
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{
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return (mmio_read_32(mbc_base) & BIT(14));
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}
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static bool is_trdc_mgr_slot(uintptr_t trdc_base, uint8_t mbc_id,
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uint8_t mem_id, uint16_t blk_id)
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{
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unsigned int i;
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for (i = 0U; i < trdc_mgr_num; i++) {
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if (trdc_mgr_blks[i].trdc_base == trdc_base) {
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if (mbc_id == trdc_mgr_blks[i].mbc_id &&
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mem_id == trdc_mgr_blks[i].mbc_mem_id &&
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(blk_id == trdc_mgr_blks[i].blk_mgr ||
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blk_id == trdc_mgr_blks[i].blk_mc)) {
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return true;
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}
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}
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}
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return false;
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}
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/*
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* config the TRDC MGR & MC's access policy. only the secure privilege
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* mode SW can access it.
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*/
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void trdc_mgr_mbc_setup(struct trdc_mgr_info *mgr)
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{
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unsigned int i;
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/*
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* If the MBC is global enabled, need to cconfigure the MBCs of
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* TRDC MGR & MC correctly.
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*/
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if (trdc_mbc_enabled(mgr->trdc_base)) {
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/* ONLY secure privilige can access */
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trdc_mbc_set_control(mgr->trdc_base, mgr->mbc_id, 7, 0x6000);
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for (i = 0U; i < 16U; i++) {
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trdc_mbc_blk_config(mgr->trdc_base, mgr->mbc_id, i,
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mgr->mbc_mem_id, mgr->blk_mgr, true, 7);
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trdc_mbc_blk_config(mgr->trdc_base, mgr->mbc_id, i,
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mgr->mbc_mem_id, mgr->blk_mc, true, 7);
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}
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}
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}
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/*
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* Set up the TRDC access policy for all the resources under
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* the TRDC control.
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*/
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void trdc_setup(struct trdc_config_info *cfg)
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{
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unsigned int i, j, num;
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bool is_mgr;
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/* config the MRCs */
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if (trdc_mrc_enabled(cfg->trdc_base)) {
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/* set global access policy */
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for (i = 0U; i < cfg->num_mrc_glbac; i++) {
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trdc_mrc_set_control(cfg->trdc_base,
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cfg->mrc_glbac[i].mbc_mrc_id,
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cfg->mrc_glbac[i].glbac_id,
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cfg->mrc_glbac[i].glbac_val);
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}
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/* set each MRC region access policy */
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for (i = 0U; i < cfg->num_mrc_cfg; i++) {
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trdc_mrc_rgn_config(cfg->trdc_base, cfg->mrc_cfg[i].mrc_id,
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cfg->mrc_cfg[i].dom_id,
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cfg->mrc_cfg[i].region_id,
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cfg->mrc_cfg[i].region_start,
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cfg->mrc_cfg[i].region_size,
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cfg->mrc_cfg[i].secure,
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cfg->mrc_cfg[i].glbac_id);
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}
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}
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/* config the MBCs */
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if (trdc_mbc_enabled(cfg->trdc_base)) {
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/* set MBC global access policy */
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for (i = 0U; i < cfg->num_mbc_glbac; i++) {
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trdc_mbc_set_control(cfg->trdc_base,
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cfg->mbc_glbac[i].mbc_mrc_id,
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cfg->mbc_glbac[i].glbac_id,
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cfg->mbc_glbac[i].glbac_val);
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}
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for (i = 0U; i < cfg->num_mbc_cfg; i++) {
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if (cfg->mbc_cfg[i].blk_id == MBC_BLK_ALL) {
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num = trdc_mbc_blk_num(cfg->trdc_base,
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cfg->mbc_cfg[i].mbc_id,
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cfg->mbc_cfg[i].mem_id);
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for (j = 0U; j < num; j++) {
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/* Skip mgr and mc */
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is_mgr = is_trdc_mgr_slot(cfg->trdc_base,
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cfg->mbc_cfg[i].mbc_id,
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cfg->mbc_cfg[i].mem_id, j);
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if (is_mgr) {
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continue;
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}
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trdc_mbc_blk_config(cfg->trdc_base,
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cfg->mbc_cfg[i].mbc_id,
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cfg->mbc_cfg[i].dom_id,
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cfg->mbc_cfg[i].mem_id, j,
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cfg->mbc_cfg[i].secure,
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cfg->mbc_cfg[i].glbac_id);
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}
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} else {
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trdc_mbc_blk_config(cfg->trdc_base,
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cfg->mbc_cfg[i].mbc_id,
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cfg->mbc_cfg[i].dom_id,
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cfg->mbc_cfg[i].mem_id,
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cfg->mbc_cfg[i].blk_id,
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cfg->mbc_cfg[i].secure,
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cfg->mbc_cfg[i].glbac_id);
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}
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}
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}
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}
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172
include/drivers/nxp/trdc/imx_trdc.h
Normal file
172
include/drivers/nxp/trdc/imx_trdc.h
Normal file
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@ -0,0 +1,172 @@
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/*
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IMX_TRDC_H
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#define IMX_XRDC_H
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#define MBC_BLK_ALL U(255)
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#define MRC_REG_ALL U(16)
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#define GLBAC_NUM U(8)
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#define DID_NUM U(16)
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#define MBC_MAX_NUM U(4)
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#define MRC_MAX_NUM U(2)
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#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF)
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#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F)
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#define MBC_BLK_NUM(GLBCFG) ((GLBCFG) & 0x3FF)
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#define MRC_RGN_NUM(GLBCFG) ((GLBCFG) & 0x1F)
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#define MDAC_W_X(m, r) (0x800 + (m) * 0x20 + (r) * 0x4)
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/* CPU/non-CPU domain common bits */
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#define MDA_VLD BIT(31)
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#define MDA_LK1 BIT(30)
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#define MDA_DFMT BIT(29)
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/* CPU domain bits */
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#define MDA_DFMT0_DID(x) ((x) & 0xF)
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#define MDA_DFMT0_DIDS(x) (((x) & 0x3) << 4)
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#define MDA_DFMT0_PE(x) (((x) & 0x3) << 6)
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#define MDA_DFMT0_PIDM(x) (((x) & 0x3F) << 8)
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#define MDA_DFMT0_SA(x) (((x) & 0x3) << 14)
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#define MDA_DFMT0_PID(x) (((x) & 0x3F) << 16)
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/* non-CPU domain bits */
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#define MDA_DFMT1_DID(x) ((x) & 0xF)
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#define MDA_DFMT1_PA(x) (((x) & 0x3) << 4)
|
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#define MDA_DFMT1_SA(x) (((x) & 0x3) << 6)
|
||||
#define MDA_DFMT1_DIDB(x) ((x) << 8)
|
||||
|
||||
#define SP(X) ((X) << 12)
|
||||
#define SU(X) ((X) << 8)
|
||||
#define NP(X) ((X) << 4)
|
||||
#define NU(X) ((X) << 0)
|
||||
|
||||
#define RWX U(7)
|
||||
#define RW U(6)
|
||||
#define RX U(5)
|
||||
#define R U(4)
|
||||
#define X U(1)
|
||||
|
||||
struct mbc_mem_dom {
|
||||
uint32_t mem_glbcfg[4];
|
||||
uint32_t nse_blk_index;
|
||||
uint32_t nse_blk_set;
|
||||
uint32_t nse_blk_clr;
|
||||
uint32_t nsr_blk_clr_all;
|
||||
uint32_t memn_glbac[8];
|
||||
/* The upper only existed in the beginning of each MBC */
|
||||
uint32_t mem0_blk_cfg_w[64];
|
||||
uint32_t mem0_blk_nse_w[16];
|
||||
uint32_t mem1_blk_cfg_w[8];
|
||||
uint32_t mem1_blk_nse_w[2];
|
||||
uint32_t mem2_blk_cfg_w[8];
|
||||
uint32_t mem2_blk_nse_w[2];
|
||||
uint32_t mem3_blk_cfg_w[8];
|
||||
uint32_t mem3_blk_nse_w[2]; /*0x1F0, 0x1F4 */
|
||||
uint32_t reserved[2];
|
||||
};
|
||||
|
||||
struct mrc_rgn_dom {
|
||||
uint32_t mrc_glbcfg[4];
|
||||
uint32_t nse_rgn_indirect;
|
||||
uint32_t nse_rgn_set;
|
||||
uint32_t nse_rgn_clr;
|
||||
uint32_t nse_rgn_clr_all;
|
||||
uint32_t memn_glbac[8];
|
||||
/* The upper only existed in the beginning of each MRC */
|
||||
uint32_t rgn_desc_words[16][2]; /* 16 regions at max, 2 words per region */
|
||||
uint32_t rgn_nse;
|
||||
uint32_t reserved2[15];
|
||||
};
|
||||
|
||||
struct mda_inst {
|
||||
uint32_t mda_w[8];
|
||||
};
|
||||
|
||||
struct trdc_mgr {
|
||||
uint32_t trdc_cr;
|
||||
uint32_t res0[59];
|
||||
uint32_t trdc_hwcfg0;
|
||||
uint32_t trdc_hwcfg1;
|
||||
uint32_t res1[450];
|
||||
struct mda_inst mda[128];
|
||||
};
|
||||
|
||||
struct trdc_mbc {
|
||||
struct mbc_mem_dom mem_dom[DID_NUM];
|
||||
};
|
||||
|
||||
struct trdc_mrc {
|
||||
struct mrc_rgn_dom mrc_dom[DID_NUM];
|
||||
};
|
||||
|
||||
/***************************************************************
|
||||
* Below structs used fro provding the TRDC configuration info
|
||||
* that will be used to init the TRDC based on use case.
|
||||
***************************************************************/
|
||||
struct trdc_glbac_config {
|
||||
uint8_t mbc_mrc_id;
|
||||
uint8_t glbac_id;
|
||||
uint32_t glbac_val;
|
||||
};
|
||||
|
||||
struct trdc_mbc_config {
|
||||
uint8_t mbc_id;
|
||||
uint8_t dom_id;
|
||||
uint8_t mem_id;
|
||||
uint8_t blk_id;
|
||||
uint8_t glbac_id;
|
||||
bool secure;
|
||||
};
|
||||
|
||||
struct trdc_mrc_config {
|
||||
uint8_t mrc_id;
|
||||
uint8_t dom_id;
|
||||
uint8_t region_id;
|
||||
uint32_t region_start;
|
||||
uint32_t region_size;
|
||||
uint8_t glbac_id;
|
||||
bool secure;
|
||||
};
|
||||
|
||||
struct trdc_mgr_info {
|
||||
uintptr_t trdc_base;
|
||||
uint8_t mbc_id;
|
||||
uint8_t mbc_mem_id;
|
||||
uint8_t blk_mgr;
|
||||
uint8_t blk_mc;
|
||||
};
|
||||
|
||||
struct trdc_config_info {
|
||||
uintptr_t trdc_base;
|
||||
struct trdc_glbac_config *mbc_glbac;
|
||||
uint32_t num_mbc_glbac;
|
||||
struct trdc_mbc_config *mbc_cfg;
|
||||
uint32_t num_mbc_cfg;
|
||||
struct trdc_glbac_config *mrc_glbac;
|
||||
uint32_t num_mrc_glbac;
|
||||
struct trdc_mrc_config *mrc_cfg;
|
||||
uint32_t num_mrc_cfg;
|
||||
};
|
||||
|
||||
extern struct trdc_mgr_info trdc_mgr_blks[];
|
||||
extern unsigned int trdc_mgr_num;
|
||||
/* APIs to apply and enable TRDC */
|
||||
int trdc_mda_set_cpu(uintptr_t trdc_base, uint32_t mda_inst,
|
||||
uint32_t mda_reg, uint8_t sa, uint8_t dids,
|
||||
uint8_t did, uint8_t pe, uint8_t pidm, uint8_t pid);
|
||||
|
||||
int trdc_mda_set_noncpu(uintptr_t trdc_base, uint32_t mda_inst,
|
||||
bool did_bypass, uint8_t sa, uint8_t pa,
|
||||
uint8_t did);
|
||||
|
||||
void trdc_mgr_mbc_setup(struct trdc_mgr_info *mgr);
|
||||
void trdc_setup(struct trdc_config_info *cfg);
|
||||
void trdc_config(void);
|
||||
|
||||
#endif /* IMX_TRDC_H */
|
||||
Loading…
Add table
Reference in a new issue