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https://github.com/ARM-software/arm-trusted-firmware.git
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2935291009
Add the trdc driver that is used on NXP i.MX9 family Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ie1fd86b76564fa7e20d74d5b4dbfe7ea0ee851fc
172 lines
4 KiB
C
172 lines
4 KiB
C
/*
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IMX_TRDC_H
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#define IMX_XRDC_H
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#define MBC_BLK_ALL U(255)
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#define MRC_REG_ALL U(16)
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#define GLBAC_NUM U(8)
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#define DID_NUM U(16)
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#define MBC_MAX_NUM U(4)
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#define MRC_MAX_NUM U(2)
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#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF)
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#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F)
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#define MBC_BLK_NUM(GLBCFG) ((GLBCFG) & 0x3FF)
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#define MRC_RGN_NUM(GLBCFG) ((GLBCFG) & 0x1F)
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#define MDAC_W_X(m, r) (0x800 + (m) * 0x20 + (r) * 0x4)
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/* CPU/non-CPU domain common bits */
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#define MDA_VLD BIT(31)
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#define MDA_LK1 BIT(30)
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#define MDA_DFMT BIT(29)
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/* CPU domain bits */
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#define MDA_DFMT0_DID(x) ((x) & 0xF)
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#define MDA_DFMT0_DIDS(x) (((x) & 0x3) << 4)
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#define MDA_DFMT0_PE(x) (((x) & 0x3) << 6)
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#define MDA_DFMT0_PIDM(x) (((x) & 0x3F) << 8)
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#define MDA_DFMT0_SA(x) (((x) & 0x3) << 14)
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#define MDA_DFMT0_PID(x) (((x) & 0x3F) << 16)
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/* non-CPU domain bits */
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#define MDA_DFMT1_DID(x) ((x) & 0xF)
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#define MDA_DFMT1_PA(x) (((x) & 0x3) << 4)
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#define MDA_DFMT1_SA(x) (((x) & 0x3) << 6)
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#define MDA_DFMT1_DIDB(x) ((x) << 8)
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#define SP(X) ((X) << 12)
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#define SU(X) ((X) << 8)
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#define NP(X) ((X) << 4)
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#define NU(X) ((X) << 0)
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#define RWX U(7)
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#define RW U(6)
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#define RX U(5)
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#define R U(4)
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#define X U(1)
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struct mbc_mem_dom {
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uint32_t mem_glbcfg[4];
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uint32_t nse_blk_index;
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uint32_t nse_blk_set;
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uint32_t nse_blk_clr;
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uint32_t nsr_blk_clr_all;
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uint32_t memn_glbac[8];
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/* The upper only existed in the beginning of each MBC */
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uint32_t mem0_blk_cfg_w[64];
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uint32_t mem0_blk_nse_w[16];
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uint32_t mem1_blk_cfg_w[8];
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uint32_t mem1_blk_nse_w[2];
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uint32_t mem2_blk_cfg_w[8];
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uint32_t mem2_blk_nse_w[2];
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uint32_t mem3_blk_cfg_w[8];
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uint32_t mem3_blk_nse_w[2]; /*0x1F0, 0x1F4 */
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uint32_t reserved[2];
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};
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struct mrc_rgn_dom {
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uint32_t mrc_glbcfg[4];
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uint32_t nse_rgn_indirect;
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uint32_t nse_rgn_set;
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uint32_t nse_rgn_clr;
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uint32_t nse_rgn_clr_all;
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uint32_t memn_glbac[8];
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/* The upper only existed in the beginning of each MRC */
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uint32_t rgn_desc_words[16][2]; /* 16 regions at max, 2 words per region */
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uint32_t rgn_nse;
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uint32_t reserved2[15];
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};
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struct mda_inst {
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uint32_t mda_w[8];
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};
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struct trdc_mgr {
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uint32_t trdc_cr;
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uint32_t res0[59];
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uint32_t trdc_hwcfg0;
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uint32_t trdc_hwcfg1;
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uint32_t res1[450];
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struct mda_inst mda[128];
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};
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struct trdc_mbc {
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struct mbc_mem_dom mem_dom[DID_NUM];
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};
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struct trdc_mrc {
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struct mrc_rgn_dom mrc_dom[DID_NUM];
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};
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/***************************************************************
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* Below structs used fro provding the TRDC configuration info
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* that will be used to init the TRDC based on use case.
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***************************************************************/
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struct trdc_glbac_config {
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uint8_t mbc_mrc_id;
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uint8_t glbac_id;
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uint32_t glbac_val;
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};
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struct trdc_mbc_config {
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uint8_t mbc_id;
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uint8_t dom_id;
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uint8_t mem_id;
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uint8_t blk_id;
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uint8_t glbac_id;
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bool secure;
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};
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struct trdc_mrc_config {
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uint8_t mrc_id;
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uint8_t dom_id;
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uint8_t region_id;
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uint32_t region_start;
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uint32_t region_size;
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uint8_t glbac_id;
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bool secure;
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};
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struct trdc_mgr_info {
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uintptr_t trdc_base;
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uint8_t mbc_id;
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uint8_t mbc_mem_id;
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uint8_t blk_mgr;
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uint8_t blk_mc;
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};
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struct trdc_config_info {
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uintptr_t trdc_base;
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struct trdc_glbac_config *mbc_glbac;
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uint32_t num_mbc_glbac;
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struct trdc_mbc_config *mbc_cfg;
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uint32_t num_mbc_cfg;
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struct trdc_glbac_config *mrc_glbac;
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uint32_t num_mrc_glbac;
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struct trdc_mrc_config *mrc_cfg;
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uint32_t num_mrc_cfg;
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};
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extern struct trdc_mgr_info trdc_mgr_blks[];
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extern unsigned int trdc_mgr_num;
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/* APIs to apply and enable TRDC */
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int trdc_mda_set_cpu(uintptr_t trdc_base, uint32_t mda_inst,
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uint32_t mda_reg, uint8_t sa, uint8_t dids,
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uint8_t did, uint8_t pe, uint8_t pidm, uint8_t pid);
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int trdc_mda_set_noncpu(uintptr_t trdc_base, uint32_t mda_inst,
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bool did_bypass, uint8_t sa, uint8_t pa,
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uint8_t did);
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void trdc_mgr_mbc_setup(struct trdc_mgr_info *mgr);
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void trdc_setup(struct trdc_config_info *cfg);
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void trdc_config(void);
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#endif /* IMX_TRDC_H */
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