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feat(nxp/driver/tzc380): add tzc380 platform driver support
Added TZC380 platform driver support. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Id0aa6cb64fa7af79dd44e0dbb0e62cb2fd4cb824
This commit is contained in:
Jiafei Pan
parent
fdafe2b5ea
commit
de9e57ff1f
3 changed files with 207 additions and 1 deletions
152
drivers/nxp/tzc/plat_tzc380.c
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152
drivers/nxp/tzc/plat_tzc380.c
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/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <plat_tzc380.h>
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#pragma weak populate_tzc380_reg_list
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#ifdef DEFAULT_TZASC_CONFIG
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/*
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* Typical Memory map of DRAM0
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* |-----------NXP_NS_DRAM_ADDR ( = NXP_DRAM0_ADDR)----------|
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* | |
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* | |
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* | Non-SECURE REGION |
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* | |
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* | |
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* | |
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* |------- (NXP_NS_DRAM_ADDR + NXP_NS_DRAM_SIZE - 1) -------|
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* |-----------------NXP_SECURE_DRAM_ADDR--------------------|
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* | |
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* | |
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* | |
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* | SECURE REGION (= 64MB) |
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* | |
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* | |
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* | |
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* |--- (NXP_SECURE_DRAM_ADDR + NXP_SECURE_DRAM_SIZE - 1)----|
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* |-----------------NXP_SP_SHRD_DRAM_ADDR-------------------|
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* | |
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* | Secure EL1 Payload SHARED REGION (= 2MB) |
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* | |
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* |-----------(NXP_DRAM0_ADDR + NXP_DRAM0_SIZE - 1)---------|
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*
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*
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*
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* Typical Memory map of DRAM1
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* |---------------------NXP_DRAM1_ADDR----------------------|
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* | |
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* | |
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* | Non-SECURE REGION |
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* | |
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* | |
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* |---(NXP_DRAM1_ADDR + Dynamically calculated Size - 1) ---|
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*
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*
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* Typical Memory map of DRAM2
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* |---------------------NXP_DRAM2_ADDR----------------------|
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* | |
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* | |
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* | Non-SECURE REGION |
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* | |
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* | |
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* |---(NXP_DRAM2_ADDR + Dynamically calculated Size - 1) ---|
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*/
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/*****************************************************************************
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* This function sets up access permissions on memory regions
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*
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* Input:
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* tzc380_reg_list : TZC380 Region List
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* dram_idx : DRAM index
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* list_idx : TZC380 Region List Index
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* dram_start_addr : Start address of DRAM at dram_idx.
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* dram_size : Size of DRAM at dram_idx.
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* secure_dram_sz : Secure DRAM Size
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* shrd_dram_sz : Shared DRAM Size
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*
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* Out:
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* list_idx : last populated index + 1
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*
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****************************************************************************/
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int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
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int dram_idx, int list_idx,
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uint64_t dram_start_addr,
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uint64_t dram_size,
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uint32_t secure_dram_sz,
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uint32_t shrd_dram_sz)
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{
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/* Region 0: Default region marked as Non-Secure */
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if (list_idx == 0) {
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tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_NS_RW;
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tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_DISABLE;
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tzc380_reg_list[list_idx].addr = UL(0x0);
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tzc380_reg_list[list_idx].size = 0x0;
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tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
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list_idx++;
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}
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/* Continue with list entries for index > 0 */
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if (dram_idx == 0) {
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/* TZC Region 1 on DRAM0 for Secure Memory*/
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tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
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tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
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tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size;
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tzc380_reg_list[list_idx].size = secure_dram_sz;
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tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
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list_idx++;
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/* TZC Region 2 on DRAM0 for Shared Memory*/
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tzc380_reg_list[list_idx].secure = TZC_ATTR_SP_S_RW;
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tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE;
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tzc380_reg_list[list_idx].addr = dram_start_addr + dram_size + secure_dram_sz;
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tzc380_reg_list[list_idx].size = shrd_dram_sz;
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tzc380_reg_list[list_idx].sub_mask = 0x0; /* all enabled */
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list_idx++;
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}
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return list_idx;
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}
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#else
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int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
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int dram_idx, int list_idx,
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uint64_t dram_start_addr,
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uint64_t dram_size,
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uint32_t secure_dram_sz,
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uint32_t shrd_dram_sz)
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{
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ERROR("tzc380_reg_list used is not a default list\n");
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ERROR("%s needs to be over-written.\n", __func__);
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return 0;
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}
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#endif /* DEFAULT_TZASC_CONFIG */
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void mem_access_setup(uintptr_t base, uint32_t total_regions,
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struct tzc380_reg *tzc380_reg_list)
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{
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uint32_t indx = 0;
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unsigned int attr_value;
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VERBOSE("Configuring TrustZone Controller tzc380\n");
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tzc380_init(base);
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tzc380_set_action(TZC_ACTION_NONE);
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for (indx = 0; indx < total_regions; indx++) {
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attr_value = tzc380_reg_list[indx].secure |
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TZC_ATTR_SUBREG_DIS(tzc380_reg_list[indx].sub_mask) |
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TZC_ATTR_REGION_SIZE(tzc380_reg_list[indx].size) |
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tzc380_reg_list[indx].enabled;
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tzc380_configure_region(indx, tzc380_reg_list[indx].addr,
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attr_value);
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}
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tzc380_set_action(TZC_ACTION_ERR);
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}
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@ -13,11 +13,18 @@ PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/tzc
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ifeq ($(TZC_ID), TZC400)
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TZASC_SOURCES += drivers/arm/tzc/tzc400.c\
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$(PLAT_DRIVERS_PATH)/tzc/plat_tzc400.c
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else ifeq ($(TZC_ID), NONE)
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else
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ifeq ($(TZC_ID), TZC380)
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TZASC_SOURCES += drivers/arm/tzc/tzc380.c\
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$(PLAT_DRIVERS_PATH)/tzc/plat_tzc380.c
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else
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ifeq ($(TZC_ID), NONE)
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$(info -> No TZC present on platform)
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else
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$(error -> TZC type not set!)
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endif
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endif
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endif
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ifeq (${BL_COMM_TZASC_NEEDED},yes)
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BL_COMMON_SOURCES += ${TZASC_SOURCES}
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47
include/drivers/nxp/tzc/plat_tzc380.h
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47
include/drivers/nxp/tzc/plat_tzc380.h
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@ -0,0 +1,47 @@
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/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#if !defined(PLAT_TZC380_H) && defined(IMAGE_BL2)
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#define PLAT_TZC380_H
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#include <tzc380.h>
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/* Number of DRAM regions to be configured
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* for the platform can be over-written.
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*
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* Array tzc400_reg_list too, needs be over-written
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* if there is any changes to default DRAM region
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* configuration.
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*/
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#ifndef MAX_NUM_TZC_REGION
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/* 3 regions:
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* Region 0(default),
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* Region 1 (DRAM0, Secure Memory),
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* Region 2 (DRAM0, Shared memory)
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*/
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#define MAX_NUM_TZC_REGION 3
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#define DEFAULT_TZASC_CONFIG 1
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#endif
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struct tzc380_reg {
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unsigned int secure;
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unsigned int enabled;
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uint64_t addr;
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uint64_t size;
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unsigned int sub_mask;
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};
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void mem_access_setup(uintptr_t base, uint32_t total_regions,
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struct tzc380_reg *tzc380_reg_list);
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int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list,
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int dram_idx, int list_idx,
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uint64_t dram_start_addr,
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uint64_t dram_size,
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uint32_t secure_dram_sz,
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uint32_t shrd_dram_sz);
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#endif /* PLAT_TZC380_H */
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