The script 'sp_mk_generator.py' was reworked in [1]. There was a
reference the variable 'data' left. This variable 'data' used to refer
to the json data of a the sp layout file.
This patch fixed the reference with the proper variable according to the
rework [1].
[1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=a96a07bfb66b7d38fe3da824e8ba183967659008
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I9ddbfa8d55a114bcef6997920522571e070fc7d2
GICD reg write must complete before core goes to idle
mode. Achieve this with dsb() barrier instruction in IPI
ISR
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: I5af42ca901567ee5e54a5434ebe3e673a92cb9be
Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infrastructure to register multiple interrupt
handlers. This infrastructure was used and tested for two
interrupts and so, interrupt id and handler container size is
2 which is defined by MAX_INTR_EL3. Interrupt id is not used
as container index due to size constraints. User is expected to
adjust MAX_INTR_EL3 based on how many interrupts are handled in
TF-A
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id49d94f6773fbb6874ccf89c0d12572efc7e678e
PM_FEATURE_CHECK is supported only for platform
management API. PM_LOAD_PDI command is not intended
for platform management. This patch removes version
check of PM_LOAD_PDI and adds version check of command
that is used for SGI registartion.
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
Change-Id: I353163109b639acab73120f405a811770e8831a0
Cortex-A78C erratum 2376749 is a Cat B erratum that applies
to revisions r0p1 and r0p2 of the A78C and is currently open.
The workaround is to set CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause
invalidations to other PE caches.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I3b29f4b7f167bf499d5d11ffef91a94861bd1383
Some registers of MSDC need to be set in ATF, so we add MSDC drivers.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Idde51a136ad08dbaece0bdaa804b934fca7046b6
- MTK_SIP_KERNEL_DFD can be moved to mtk_sip_def.h.
- Remove unused MTK_SIP_* definations which are already defined in
mtk_sip_def.h.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ife8f1e842d986691488548632426f194199d42b9
Renesas platform does not support crypto, but mbedtls_common.mk
is still included in its makefile. Therefore, this inclusion
was removed to avoid un-necessary compilation of mbedTLS source.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ib6978255e39a7f5d5013952841930ae68b12c318
When putting FIP binary in eMMC boot partition (with STM32MP_EMMC_BOOT),
the FIP max size should be precised. If it is not, an assert fails in
io_block driver, as cur->size will be zero.
For this length, we then use the size of the eMMC boot partition minus
STM32MP_EMMC_BOOT_FIP_OFFSET.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I48b7635cff64f52d4b337a4c8c3becd9a0be72e8
The boot partition size of an eMMC is given in ext_csd register, at
offset 226 (BOOT_SIZE_MULT), which has to be multiplied by 128kB.
Add a helper function mmc_boot_part_size() to get this eMMC boot
partition size.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I0e8e0fc9632f147fa1b1b3374accb78439025403
Cortex-A710 erratum 2216384 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR5_EL1[17] to 1 and applying an instruction patching sequence.
Setting this bit, along with these instructions will prevent the
deadlock, and thereby avoids the reset of the processor.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Change-Id: I2821591c23f854c12111288ad1fd1aef45db6add
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* changes:
fix(n1sdp): mapping Run-time UART to IOFPGA UART0
fix(n1sdp): add numa node id for pcie controllers
fix(n1sdp): replace non-inclusive terms from dts file
* changes:
feat(stm32mp1): allow to override MTD base offset
feat(stm32mp1): manage second NAND OTP on STM32MP13
feat(stm32mp1): add define for external scratch buffer for nand devices
feat(mtd): add platform function to allow using external buffer
feat(libc): introduce __maybe_unused
* changes:
feat(mt8188): add pinctrl support
feat(mt8188): add RTC support
feat(mt8188): add pmic and pwrap support
refator(mediatek): move pmic.[c|h] to common folder
refator(mediatek): move common definitions of pmic wrap to common folder
feat(mt8188): add IOMMU enable control in SiP service
feat(mt8188): add display port control in SiP service
fix(mediatek): use uppercase for definition
feat(mediatek): move dp drivers to common folder
feat(mediatek): move mtk_cirq.c drivers to cirq folder
feat(mt8188): initialize GIC
feat(mt8188): initialize systimer
feat(mt8188): initialize platform for MediaTek MT8188
refator(mediatek): remove unused files
refator(mediatek): move drivers folder in common to plat/mediatek
feat(mediatek): support coreboot BL31 loading
TEST=build pass.
BUG=b:233720142
Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com>
Change-Id: I348eff0f53341593f74a63780e2e8298cbc3ec88
Add PWRAP and PMIC driver to support power-off.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: Id9951134925f6cb5f8d304a7b8e7901837809bd9
These two files are identical on MT8192 and MT8195. They can also be
used on MT8188. So move them to common/drivers/pmic/.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I8c12d15f1da79ab5767ac02b3ab70e8508155ee8
Some definitions can be shared among mt8192, mt8195, and
mt8186, so move them to pmic_wrap_init_common.h.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I992b61a47a84039fe8c246e2ff75721c57ee41a5
Add SiP service for multimedia & infra master to enable/disable
MM & INFRA IOMMU in secure world
TEST=build pass
BUG=b:236339614
Signed-off-by: Chengci Xu <chengci.xu@mediatek.corp-partner.google.com>
Change-Id: I4eb1fda6044cf2cb6c22c005cb2fa550906b71e9
MTK display port mute/unmute control registers need to be
set in secure world.
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0aa0675f07c80aab4349493bfbb0782bf0bbef58
Display port driver can be reused, so we move it to common/drivers.
TEST=build mt8195 pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I58c7b41ba3ad653cdf6f6fbae6778abfd7e950a9
To use cirq drivers more easier, we place mtk_cirq.c and mtk_cirq.h
to common/drivers/cirq.
We also rename mtk_cirq.c/h to mt_cirq.c/h for consistency with other
driver folders.
TEST=build pass for mt8192/mt8195/mt8186
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I71bc442f00b16fb4031260937982c0496fcaaea0
We do not use oem_svc.[c|h], so remove them.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0afb64d997cf4e23063f4fa2226e8d2649d22574
We plan to put some soc related drivers in common/drivers. To reduce
confision, we move them to plat/mediatek.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6b344e660f40a23b15151aab073d3045b28f52aa
Currently the Run-time UART is mapped to AP UART1 which is internally
routed to MCP UART1, so unsharing it from AP UART1 and mapping it to
IOFPGA UART0 for exclusiveness among the usage of the UARTs.
Signed-off-by: Himanshu Sharma <Himanshu.Sharma@arm.com>
Change-Id: I366740a971a880decf0d373e9055e7ebda5df53a
If not mentioned explicitly, numa-node-id for pcie_ctlr
is assigned as unknown. With this patch pcie_ctlr and
ccix_pcie_ctlr are assigned numa-node-id=0 and
pcie_secondary_ctlr is assigned numa-node-id=1.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I533abdd6ea162df7b15ee04cbfc48ba7a544b91a
