Prepare v2025.01-rc5

-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmdqIAsACgkQFHw5/5Y0
 tyxmdAv/a0dUsibc2oyLJzRFioJO6ib0dro5EHiH1oyF3igOTGe1ifxeQyR/0bb8
 /3Qtr19f77INNjgQmRNpLbBfeoIMm3MeVF+zwQzEvUDEHNNQ0nnxu/yNnJB6Ebej
 xF/vdAP4JoV+KFQXMCMjIyFZcjZh4wGn1L1T8y7GQHS+p1zf0EYA7tPbk5rbwk/E
 xAFSymtWvOZVjLgV9YKp/RqS1+vGHaKydwzUZAncXJzeAMFD2Wm7mnDkd828U/eR
 7vs5BCnRwTgj7iWE6KXJUhFz2hrrBMFTEIV4GNW28vBSCoArlWshLbpKRolEoKY9
 i+dfkBDhghw9fVcTBOSP7BkiFwQl02jPB4Vf8G5ykK11CHO8XTpdjE5buGS1zsiW
 dTX9w4pynCl07p0qYsgGPYf2cE1k6dG6XFNUzH3owyNGiF+66VQeG05V79moQp9F
 ZF0/rux475UhZceXDImdecgkBDsc9gRvu0aX9ZYQtaBCgKJnQ8nyYPXGWZ/u0TSl
 1WVADGUq
 =4mOT
 -----END PGP SIGNATURE-----

Merge tag 'v2025.01-rc5' into next

Prepare v2025.01-rc5

.gitlab-ci.yml

@@ -669,3 +669,8 @@ nyan-big:
   variables:
     ROLE: nyan-big
   <<: *lab_dfn
+
+rpi:
+  variables:
+    ROLE: rpi
+  <<: *lab_dfn

Kconfig

@@ -578,6 +578,7 @@ config STACK_SIZE
 	hex "Define max stack size that can be used by U-Boot"
 	default 0x4000000 if ARCH_VERSAL_NET || ARCH_VERSAL || ARCH_ZYNQMP
 	default 0x200000 if MICROBLAZE
+	default 0x4000 if ARCH_STM32
 	default 0x1000000
 	help
 	  Define Max stack size that can be used by U-Boot. This value is used

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2025
 PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION = -rc5
 NAME =
 
 # *DOCUMENTATION*
@@ -21,7 +21,7 @@ include include/host_arch.h
 ifeq ("", "$(CROSS_COMPILE)")
   MK_ARCH="${shell uname -m}"
 else
-  MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(ccache\)\{0,1\}[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}"
+  MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(.*ccache\)\{0,1\}[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}"
 endif
 unexport HOST_ARCH
 ifeq ("x86_64", $(MK_ARCH))

arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi

@@ -203,3 +203,7 @@
 &sysclk {
 	bootph-all;
 };
+
+&usb0 {
+	dr_mode = "host";
+};

arch/arm/dts/r8a7790-u-boot.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source extras for U-Boot on RCar R8A7790 SoC
+ * Device Tree Source extras for U-Boot on R-Car R8A7790 SoC
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

arch/arm/dts/r8a7791-u-boot.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source extras for U-Boot on RCar R8A7791 SoC
+ * Device Tree Source extras for U-Boot on R-Car R8A7791 SoC
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

arch/arm/dts/r8a7792-u-boot.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source extras for U-Boot on RCar R8A7792 SoC
+ * Device Tree Source extras for U-Boot on R-Car R8A7792 SoC
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

arch/arm/dts/r8a7793-u-boot.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source extras for U-Boot on RCar R8A7793 SoC
+ * Device Tree Source extras for U-Boot on R-Car R8A7793 SoC
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

arch/arm/dts/r8a7794-u-boot.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source extras for U-Boot on RCar R8A7794 SoC
+ * Device Tree Source extras for U-Boot on R-Car R8A7794 SoC
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

arch/arm/dts/r8a77951-u-boot.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source extras for U-Boot on RCar R8A7795 SoC
+ * Device Tree Source extras for U-Boot on R-Car R8A7795 SoC
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

arch/arm/dts/r8a77960-u-boot.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source extras for U-Boot on RCar R8A7796 SoC
+ * Device Tree Source extras for U-Boot on R-Car R8A7796 SoC
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

arch/arm/dts/r8a77965-u-boot.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source extras for U-Boot on RCar R8A77965 SoC
+ * Device Tree Source extras for U-Boot on R-Car R8A77965 SoC
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

arch/arm/dts/r8a77970-u-boot.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source extras for U-Boot on RCar R8A77970 SoC
+ * Device Tree Source extras for U-Boot on R-Car R8A77970 SoC
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

arch/arm/dts/r8a77980-u-boot.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source extras for U-Boot on RCar R8A77980 SoC
+ * Device Tree Source extras for U-Boot on R-Car R8A77980 SoC
  *
  * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
  */

arch/arm/dts/r8a77990-u-boot.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source extras for U-Boot on RCar R8A77990 SoC
+ * Device Tree Source extras for U-Boot on R-Car R8A77990 SoC
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

arch/arm/dts/r8a77995-u-boot.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source extras for U-Boot on RCar R8A77995 SoC
+ * Device Tree Source extras for U-Boot on R-Car R8A77995 SoC
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

arch/arm/dts/r8a779x-u-boot.dtsi

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source extras for U-Boot on RCar Gen3
+ * Device Tree Source extras for U-Boot on R-Car Gen3
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

arch/arm/dts/stm32mp15-u-boot.dtsi

@@ -186,6 +186,9 @@
 	bootph-all;
 	#address-cells = <1>;
 	#size-cells = <0>;
+	clock-names = "hse", "hsi", "csi", "lse", "lsi";
+	clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
+		 <&clk_lse>, <&clk_lsi>;
 };
 
 &usart1 {

arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi

@@ -112,6 +112,10 @@
 };
 
 &rcc {
+	clock-names = "hse", "hsi", "csi", "lse", "lsi";
+	clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>,
+		 <&clk_lse>, <&clk_lsi>;
+
 	st,clksrc = <
 		CLK_MPU_PLL1P
 		CLK_AXI_PLL2P

arch/arm/mach-imx/imx8m/soc.c

@@ -362,7 +362,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 	 * space below the 4G address boundary (which is 3GiB big),
 	 * even when the effective available memory is bigger.
 	 */
-	top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, 0xffffffff);
+	top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, SZ_4G);
 
 	/*
 	 * rom_pointer[0] stores the TEE memory start address.

arch/arm/mach-renesas/Kconfig.32

@@ -1,11 +1,11 @@
 if RCAR_32
 
 config ARCH_RENESAS_BOARD_STRING
-	string "Renesas RCar Gen2 board name"
+	string "Renesas R-Car Gen2 board name"
 	default "Board"
 
 config RCAR_GEN2
-	bool "Renesas RCar Gen2"
+	bool "Renesas R-Car Gen2"
 	select PHY
 	select PHY_RCAR_GEN2
 	select TMU_TIMER

arch/arm/mach-renesas/include/mach/boot0.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Specialty padding for the RCar Gen2 SPL JTAG loading
+ * Specialty padding for the R-Car Gen2 SPL JTAG loading
  */
 
 #ifndef __BOOT0_H

arch/arm/mach-renesas/memmap-gen3.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Renesas RCar Gen3 memory map tables
+ * Renesas R-Car Gen3 memory map tables
  *
  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
  */

arch/arm/mach-stm32mp/stm32mp1/cpu.c

@@ -53,6 +53,7 @@ void dram_bank_mmu_setup(int bank)
 	struct bd_info *bd = gd->bd;
 	int	i;
 	phys_addr_t start;
+	phys_addr_t addr;
 	phys_size_t size;
 	bool use_lmb = false;
 	enum dcache_option option;
@@ -77,8 +78,12 @@ void dram_bank_mmu_setup(int bank)
 	for (i = start >> MMU_SECTION_SHIFT;
 	     i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
 	     i++) {
+		addr = i << MMU_SECTION_SHIFT;
 		option = DCACHE_DEFAULT_OPTION;
-		if (use_lmb && lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP))
+		if (use_lmb &&
+		    (lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP) ||
+		    addr >= gd->ram_top)
+		   )
 			option = 0; /* INVALID ENTRY in TLB */
 		set_section_dcache(i, option);
 	}

board/freescale/t208xqds/eth_t208xqds.c

@@ -210,8 +210,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 				fdt_set_phy_handle(fdt, compat, addr,
 						   "phy_1gkx1");
 				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
-				sprintf(buf, "%s%s%s", buf, "lane-c,",
+				strcat(buf, "lane-c,");
-						(char *)lane_mode[0]);
+				strcat(buf, (char *)lane_mode[0]);
 				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 					 PCCR1_SGMIIH_KX_MASK);
 				break;
@@ -222,8 +222,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 				fdt_set_phy_handle(fdt, compat, addr,
 						   "phy_1gkx2");
 				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
-				sprintf(buf, "%s%s%s", buf, "lane-d,",
+				strcat(buf, "lane-d,");
-						(char *)lane_mode[0]);
+				strcat(buf, (char *)lane_mode[0]);
 				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 					 PCCR1_SGMIIG_KX_MASK);
 				break;
@@ -234,8 +234,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 				fdt_set_phy_handle(fdt, compat, addr,
 						   "phy_1gkx9");
 				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
-				sprintf(buf, "%s%s%s", buf, "lane-a,",
+				strcat(buf, "lane-a,");
-						(char *)lane_mode[0]);
+				strcat(buf, (char *)lane_mode[0]);
 				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 					 PCCR1_SGMIIE_KX_MASK);
 				break;
@@ -247,8 +247,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 						   "phy_1gkx10");
 				fdt_status_okay_by_alias(fdt,
 							 "1gkx_pcs_mdio10");
-				sprintf(buf, "%s%s%s", buf, "lane-b,",
+				strcat(buf, "lane-b,");
-						(char *)lane_mode[0]);
+				strcat(buf, (char *)lane_mode[0]);
 				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 					 PCCR1_SGMIIF_KX_MASK);
 				break;
@@ -269,8 +269,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 				fdt_set_phy_handle(fdt, compat, addr,
 						   "phy_1gkx5");
 				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
-				sprintf(buf, "%s%s%s", buf, "lane-g,",
+				strcat(buf, "lane-g,");
-						(char *)lane_mode[0]);
+				strcat(buf, (char *)lane_mode[0]);
 				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 					 PCCR1_SGMIIC_KX_MASK);
 				break;
@@ -281,8 +281,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 				fdt_set_phy_handle(fdt, compat, addr,
 						   "phy_1gkx6");
 				fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
-				sprintf(buf, "%s%s%s", buf, "lane-h,",
+				strcat(buf, "lane-h,");
-						(char *)lane_mode[0]);
+				strcat(buf, (char *)lane_mode[0]);
 				out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
 					 PCCR1_SGMIID_KX_MASK);
 				break;
@@ -328,8 +328,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 				fdt_set_phy_handle(fdt, compat, addr,
 						"phy_xfi9");
 				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
-				sprintf(buf, "%s%s%s", buf, "lane-a,",
+				strcat(buf, "lane-a,");
-						(char *)lane_mode[1]);
+				strcat(buf, (char *)lane_mode[1]);
 			}
 				break;
 			case FM1_10GEC2:
@@ -339,8 +339,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 				fdt_set_phy_handle(fdt, compat, addr,
 						"phy_xfi10");
 				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
-				sprintf(buf, "%s%s%s", buf, "lane-b,",
+				strcat(buf, "lane-b,");
-						(char *)lane_mode[1]);
+				strcat(buf, (char *)lane_mode[1]);
 			}
 				break;
 			case FM1_10GEC3:
@@ -350,8 +350,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 				fdt_set_phy_handle(fdt, compat, addr,
 						"phy_xfi1");
 				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
-				sprintf(buf, "%s%s%s", buf, "lane-c,",
+				strcat(buf, "lane-c,");
-						(char *)lane_mode[1]);
+				strcat(buf, (char *)lane_mode[1]);
 			}
 				break;
 			case FM1_10GEC4:
@@ -361,8 +361,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 				fdt_set_phy_handle(fdt, compat, addr,
 						"phy_xfi2");
 				fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
-				sprintf(buf, "%s%s%s", buf, "lane-d,",
+				strcat(buf, "lane-d,");
-						(char *)lane_mode[1]);
+				strcat(buf, (char *)lane_mode[1]);
 			}
 				break;
 			default:

board/kontron/sl28/sl28.c

@@ -156,7 +156,8 @@ int fsl_board_late_init(void)
 	 * If the watchdog isn't enabled at reset (which is a configuration
 	 * option) disabling it doesn't hurt either.
 	 */
-	if (!IS_ENABLED(CONFIG_WATCHDOG_AUTOSTART))
+	if (IS_ENABLED(CONFIG_WDT_SL28CPLD) &&
+	    !IS_ENABLED(CONFIG_WATCHDOG_AUTOSTART))
 		stop_recovery_watchdog();
 
 	return 0;

board/kontron/sl28/spl.c

@@ -50,9 +50,10 @@ int board_fit_config_name_match(const char *name)
 		return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var1");
 	case 2:
 		return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var2");
+	case 3:
+		return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var3");
 	case 4:
 		return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var4");
-	case 3:
 	default:
 		return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28");
 	}

board/raspberrypi/rpi/rpi.c

@@ -68,6 +68,19 @@ struct msg_get_clock_rate {
 	u32 end_tag;
 };
 
+struct efi_fw_image fw_images[] = {
+	{
+		.fw_name = u"RPI_UBOOT",
+		.image_index = 1,
+	},
+};
+
+struct efi_capsule_update_info update_info = {
+	.dfu_string = "mmc 0=u-boot.bin fat 0 1",
+	.num_images = ARRAY_SIZE(fw_images),
+	.images = fw_images,
+};
+
 #ifdef CONFIG_ARM64
 #define DTB_DIR "broadcom/"
 #else
@@ -544,12 +557,15 @@ void  update_fdt_from_fw(void *fdt, void *fw_fdt)
 	if (fdt == fw_fdt)
 		return;
 
-	/* The firmware provides a more precie model; so copy that */
+	/* The firmware provides a more precise model; so copy that */
 	copy_property(fdt, fw_fdt, "/", "model");
 
 	/* memory reserve as suggested by the firmware */
 	copy_property(fdt, fw_fdt, "/", "memreserve");
 
+	/* copy the CMA memory setting from the firmware DT to linux */
+	copy_property(fdt, fw_fdt, "/reserved-memory/linux,cma", "size");
+
 	/* Adjust dma-ranges for the SD card and PCI bus as they can depend on
 	 * the SoC revision
 	 */

boot/Makefile

@@ -60,7 +60,7 @@ obj-$(CONFIG_$(PHASE_)LOAD_FIT) += common_fit.o
 obj-$(CONFIG_$(PHASE_)EXPO) += expo.o scene.o expo_build.o
 obj-$(CONFIG_$(PHASE_)EXPO) += scene_menu.o scene_textline.o
 ifdef CONFIG_COREBOOT_SYSINFO
-obj-$(CONFIG_$(SPL_TPL_)EXPO) += expo_build_cb.o
+obj-$(CONFIG_$(PHASE_)EXPO) += expo_build_cb.o
 endif
 
 obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE) += vbe.o

boot/image-android.c

@@ -332,41 +332,45 @@ int android_image_get_kernel(const void *hdr,
 	       kernel_addr, DIV_ROUND_UP(img_data.kernel_size, 1024));
 
 	int len = 0;
-	if (*img_data.kcmdline) {
-		printf("Kernel command line: %s\n", img_data.kcmdline);
-		len += strlen(img_data.kcmdline);
-	}
-
-	if (img_data.kcmdline_extra) {
-		printf("Kernel extra command line: %s\n", img_data.kcmdline_extra);
-		len += strlen(img_data.kcmdline_extra);
-	}
-
 	char *bootargs = env_get("bootargs");
+
 	if (bootargs)
 		len += strlen(bootargs);
 
-	char *newbootargs = malloc(len + 2);
+	if (*img_data.kcmdline) {
+		printf("Kernel command line: %s\n", img_data.kcmdline);
+		len += strlen(img_data.kcmdline) + (len ? 1 : 0); /* +1 for extra space */
+	}
+
+	if (*img_data.kcmdline_extra) {
+		printf("Kernel extra command line: %s\n", img_data.kcmdline_extra);
+		len += strlen(img_data.kcmdline_extra) + (len ? 1 : 0); /* +1 for extra space */
+	}
+
+	char *newbootargs = malloc(len + 1); /* +1 for the '\0' */
 	if (!newbootargs) {
 		puts("Error: malloc in android_image_get_kernel failed!\n");
 		return -ENOMEM;
 	}
-	*newbootargs = '\0';
+	*newbootargs = '\0'; /* set to Null in case no components below are present */
 
-	if (bootargs) {
+	if (bootargs)
 		strcpy(newbootargs, bootargs);
-		strcat(newbootargs, " ");
+
+	if (*img_data.kcmdline) {
+		if (*newbootargs) /* If there is something in newbootargs, a space is needed */
+			strcat(newbootargs, " ");
+		strcat(newbootargs, img_data.kcmdline);
 	}
 
-	if (*img_data.kcmdline)
+	if (*img_data.kcmdline_extra) {
-		strcat(newbootargs, img_data.kcmdline);
+		if (*newbootargs) /* If there is something in newbootargs, a space is needed */
-
+			strcat(newbootargs, " ");
-	if (img_data.kcmdline_extra) {
-		strcat(newbootargs, " ");
 		strcat(newbootargs, img_data.kcmdline_extra);
 	}
 
 	env_set("bootargs", newbootargs);
+	free(newbootargs);
 
 	if (os_data) {
 		if (image_get_magic(ihdr) == IH_MAGIC) {

boot/image-fdt.c

@@ -77,7 +77,7 @@ static void boot_fdt_reserve_region(u64 addr, u64 size, enum lmb_flags flags)
 		debug("   reserving fdt memory region: addr=%llx size=%llx flags=%x\n",
 		      (unsigned long long)addr,
 		      (unsigned long long)size, flags);
-	} else {
+	} else if (ret != -EEXIST) {
 		puts("ERROR: reserving fdt memory region failed ");
 		printf("(addr=%llx size=%llx flags=%x)\n",
 		       (unsigned long long)addr,

common/memtop.c

@@ -121,8 +121,8 @@ static long region_overlap_check(struct mem_region *mem_rgn, phys_addr_t base,
 	return (i < mem_rgn->count) ? i : -1;
 }
 
-static int find_ram_top(struct mem_region *free_mem,
+static phys_addr_t find_ram_top(struct mem_region *free_mem,
-			struct mem_region *reserved_mem, phys_size_t size)
+				struct mem_region *reserved_mem, phys_size_t size)
 {
 	long i, rgn;
 	phys_addr_t base = 0;

common/usb_onboard_hub.c

@@ -183,7 +183,12 @@ static int usb_onboard_hub_bind(struct udevice *dev)
 	int ret, off;
 
 	ret = dev_read_phandle_with_args(dev, "peer-hub", NULL, 0, 0, &phandle);
-	if (ret)  {
+	if (ret == -ENOENT) {
+		dev_dbg(dev, "peer-hub property not present\n");
+		return 0;
+	}
+
+	if (ret) {
 		dev_err(dev, "peer-hub not specified\n");
 		return ret;
 	}

configs/am62x_a53_usbdfu.config

@@ -16,7 +16,6 @@ CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
 CONFIG_SPL_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GENERIC=y
 CONFIG_SPL_USB_DWC3_GENERIC=y

configs/kontron_sl28_defconfig

@@ -54,6 +54,7 @@ CONFIG_SPL_MAX_SIZE=0x20000
 CONFIG_SPL_BOARD_INIT=y
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x200000
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x900
 CONFIG_SPL_MPC8XXX_INIT_DDR=y
@@ -77,7 +78,7 @@ CONFIG_CMD_RNG=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_UPSTREAM=y
-CONFIG_OF_LIST="freescale/fsl-ls1028a-kontron-sl28 freescale/fsl-ls1028a-kontron-sl28-var1 freescale/fsl-ls1028a-kontron-sl28-var2 freescale/fsl-ls1028a-kontron-sl28-var4"
+CONFIG_OF_LIST="freescale/fsl-ls1028a-kontron-sl28 freescale/fsl-ls1028a-kontron-sl28-var1 freescale/fsl-ls1028a-kontron-sl28-var2 freescale/fsl-ls1028a-kontron-sl28-var3 freescale/fsl-ls1028a-kontron-sl28-var4"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y

configs/ls1028ardb_tfa_defconfig

@@ -67,6 +67,7 @@ CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x57
 CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y

configs/renesas_rcar.config

@@ -17,6 +17,7 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
+CONFIG_ENV_OVERWRITE=y
 CONFIG_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_MTD=y

configs/renesas_rcar2.config

@@ -14,7 +14,6 @@ CONFIG_CMD_USB=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000
 CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_SECT_SIZE=0x40000
 CONFIG_ENV_SIZE=0x40000
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y

configs/renesas_rcar3.config

@@ -2,5 +2,4 @@
 
 CONFIG_BITBANGMII=y
 CONFIG_BITBANGMII_MULTI=y
-CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_PBSIZE=2068

configs/rpi_3_b_plus_defconfig

@@ -10,6 +10,8 @@ CONFIG_ENV_SIZE=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b-plus"
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
 CONFIG_BOOTSTD_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_FDT_SIMPLEFB=y
@@ -19,14 +21,19 @@ CONFIG_SYS_PBSIZE=1049
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_NVEDIT_EFI=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_TFTP_TSIZE=y
+CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000
 CONFIG_BCM2835_GPIO=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_BCM2835=y
@@ -49,3 +56,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_BCM2835=y
 CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_PHYS_TO_BUS=y
+# CONFIG_HEXDUMP is not set

configs/rpi_3_defconfig

@@ -10,6 +10,8 @@ CONFIG_ENV_SIZE=0x4000
 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b"
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_LOAD_ADDR=0x1000000
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
 CONFIG_BOOTSTD_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_FDT_SIMPLEFB=y
@@ -19,14 +21,19 @@ CONFIG_SYS_PBSIZE=1049
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_NVEDIT_EFI=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_TFTP_TSIZE=y
+CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000
 CONFIG_BCM2835_GPIO=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_BCM2835=y
@@ -49,3 +56,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_BCM2835=y
 CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_PHYS_TO_BUS=y
+# CONFIG_HEXDUMP is not set

configs/rpi_4_defconfig

@@ -10,6 +10,8 @@ CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_PCI=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
 CONFIG_BOOTSTD_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_FDT_SIMPLEFB=y
@@ -20,11 +22,13 @@ CONFIG_SYS_PBSIZE=1049
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_NVEDIT_EFI=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -65,3 +69,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_BCM2835=y
 CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_PHYS_TO_BUS=y
+# CONFIG_HEXDUMP is not set

configs/rpi_arm64_defconfig

@@ -8,6 +8,8 @@ CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SYS_LOAD_ADDR=0x1000000
 CONFIG_PCI=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
 CONFIG_BOOTSTD_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_FDT_SIMPLEFB=y
@@ -18,15 +20,20 @@ CONFIG_SYS_PBSIZE=1049
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_MISC_INIT_R=y
 CONFIG_SYS_PROMPT="U-Boot> "
+CONFIG_CMD_NVEDIT_EFI=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_EFIDEBUG=y
 CONFIG_CMD_FS_UUID=y
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_TFTP_TSIZE=y
 CONFIG_DM_DMA=y
+CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000
 CONFIG_BCM2835_GPIO=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
@@ -56,3 +63,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_VIDEO_BCM2835=y
 CONFIG_CONSOLE_SCROLL_LINES=10
 CONFIG_PHYS_TO_BUS=y
+# CONFIG_HEXDUMP is not set

configs/starfive_visionfive2_defconfig

@@ -32,7 +32,6 @@ CONFIG_CMODEL_MEDANY=y
 CONFIG_RISCV_SMODE=y
 # CONFIG_OF_BOARD_FIXUP is not set
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
 CONFIG_FIT=y
 CONFIG_BOOTSTD_DEFAULTS=y
 CONFIG_BOOTSTAGE=y

configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig

@@ -27,6 +27,9 @@ CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y

configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig

@@ -27,6 +27,9 @@ CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y

configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig

@@ -27,6 +27,9 @@ CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y

configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig

@@ -27,6 +27,9 @@ CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y

configs/stm32mp15_basic_defconfig

@@ -38,6 +38,9 @@ CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C=y
 CONFIG_SPL_MTD=y

configs/stm32mp15_dhcom_basic_defconfig

@@ -7,5 +7,4 @@ CONFIG_SYS_MEMTEST_START=0xc0000000
 CONFIG_SYS_MEMTEST_END=0xc4000000
 CONFIG_SYS_I2C_EEPROM_BUS=3
 CONFIG_OF_LIST="st/stm32mp157c-dhcom-pdk2 st/stm32mp153c-dhcom-drc02 st/stm32mp157c-dhcom-picoitx"
-CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
 CONFIG_SYS_I2C_EEPROM_ADDR=0x50

configs/stm32mp15_dhcor_basic_defconfig

@@ -5,7 +5,6 @@ CONFIG_ARCH_STM32MP=y
 CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-dhcor-avenger96"
 CONFIG_SYS_I2C_EEPROM_BUS=2
 CONFIG_OF_LIST="st/stm32mp157a-dhcor-avenger96 st/stm32mp151a-dhcor-testbench st/stm32mp153c-dhcor-drc-compact"
-CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
 CONFIG_SYS_I2C_EEPROM_ADDR=0x53
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y

configs/stm32mp15_dhsom.config

@@ -22,6 +22,7 @@ CONFIG_HAS_BOARD_SIZE_LIMIT=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_HWSPINLOCK_STM32=y
 CONFIG_KS8851_MLL=y
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks access-controllers"
 CONFIG_PHY_ANEG_TIMEOUT=20000
 CONFIG_PINCTRL_STMFX=y
 CONFIG_REMOTEPROC_STM32_COPRO=y
@@ -57,11 +58,14 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_STACK=0x30000000
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
 CONFIG_SPL_TEXT_BASE=0x2FFC2500
 CONFIG_SPL_USB_GADGET=y
 CONFIG_STM32_ADC=y
 CONFIG_SYSRESET_SYSCON=y
 CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
 CONFIG_SYS_MALLOC_F_LEN=0x3000
 CONFIG_SYS_PBSIZE=1050
 CONFIG_PREBOOT="run dh_preboot"

doc/board/coolpi/genbook_cm5_rk3588.rst

@@ -6,6 +6,7 @@ Cool Pi GenBook is a laptop powered by RK3588, it works with a
 carrier board connect with CM5.
 
 Specification:
+
 * Rockchip RK3588
 * LPDDR5X 8/32 GB
 * eMMC 64 GB
@@ -24,11 +25,11 @@ Get the TF-A and DDR init (TPL) binaries
 
 .. prompt:: bash
 
-   > cd u-boot
+   cd u-boot
-   > export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin
+   export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin
-   > export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.46.elf
+   export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.46.elf
-   > make coolpi-genbook-cm5-rk3588_defconfig
+   make coolpi-genbook-cm5-rk3588_defconfig
-   > make CROSS_COMPILE=aarch64-linux-gnu-
+   make CROSS_COMPILE=aarch64-linux-gnu-
 
 This will build ``u-boot-rockchip.bin`` for eMMC and ``u-boot-rockchip-spi.bin`` for SPI Nor.
 

doc/board/kontron/sl28.rst

@@ -65,12 +65,14 @@ wdt command flags
 The `wdt start` as well as the `wdt expire` command take a flags argument.
 The supported bitmask is as follows.
 
-| Bit | Description                   |
+===  ==============================
-| --- | ----------------------------- |
+Bit  Description
-|   0 | Enable failsafe mode          |
+===  ==============================
-|   1 | Lock the control register     |
+  0  Enable failsafe mode
-|   2 | Disable board reset           |
+  1  Lock the control register
-|   3 | Enable WDT_TIME_OUT# line     |
+  2  Disable board reset
+  3  Enable WDT_TIME_OUT# line
+===  ==============================
 
 For example, you can use `wdt expire 1` to issue a reset and boot into the
 failsafe bootloader.

doc/board/theobroma-systems/puma_rk3399.rst

@@ -27,6 +27,7 @@ RK3399-Q7 features:
  * Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF)
  * NOR Flash: onboard SPI NOR
  * Companion Controller: onboard additional Cortex-M0 microcontroller
+
    * RTC
    * fan controller
    * CAN

doc/board/theobroma-systems/tiger_rk3588.rst

@@ -8,6 +8,7 @@ connector) system-on-module from Theobroma Systems, featuring the
 Rockchip RK3588.
 
 It provides the following feature set:
+
  * up to 16GB LPDDR4x
  * on-module eMMC
  * SD card (on a baseboard) via edge connector
@@ -18,14 +19,20 @@ It provides the following feature set:
  * HDMI input over FPC connector
  * CAN
  * USB
+
    - 1x USB 3.0 dual-role (direct connection)
    - 2x USB 3.0 host + 1x USB 2.0 host
+
  * PCIe
+
    - 1x PCIe 2.1 Gen3, 4 lanes
    - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
+
  * on-module ATtiny816 companion controller, implementing:
+
    - low-power RTC functionality (ISL1208 emulation)
    - fan controller (AMC6821 emulation)
+
  * on-module Secure Element with Global Platform 2.2.1 compliant
    JavaCard environment
 

doc/develop/release_cycle.rst

@@ -75,7 +75,7 @@ For the next scheduled release, release candidates were made on::
 
 * U-Boot v2025.01-rc4 was released on Mon 09 December 2024.
 
-.. * U-Boot v2025.01-rc5 was released on Mon 23 December 2024.
+* U-Boot v2025.01-rc5 was released on Mon 23 December 2024.
 
 .. * U-Boot v2025.01-rc6 was released on Mon 30 December 2024.
 

doc/develop/sending_patches.rst

@@ -377,7 +377,7 @@ The following are a "rule of thumb" as to how the states are used in patchwork
 today. Not all states are used by all custodians.
 
 * New: Patch has been submitted to the list, and none of the maintainers has
-  changed it's state since.
+  changed its state since.
 
 * Under Review: A custodian is reviewing the patch currently.
 

doc/develop/uefi/fwu_updates.rst

@@ -170,7 +170,7 @@ build the tool, enable::
 
     CONFIG_TOOLS_MKEFICAPSULE=y
 
-Run the following commands to generate the accept/revert capsules::
+Run the following commands to generate the accept/revert capsules:
 
 .. code-block:: bash
 
@@ -180,7 +180,7 @@ Run the following commands to generate the accept/revert capsules::
       <capsule_file_name>
 
 Some examples of using the mkeficapsule tool for generation of the
-empty capsule would be::
+empty capsule would be:
 
 .. code-block:: bash
 

doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt

@@ -1,61 +0,0 @@
-* Rockchip RK3188/RK3066 Clock and Reset Unit
-
-The RK3188/RK3066 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
-			"rockchip,rk3066a-cru"
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
-  If missing pll rates are not changable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
-dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
-Similar macros exist for the reset sources in these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "xin32k" - rtc clock - optional,
- - "xin27m" - 27mhz crystal input on rk3066 - optional,
- - "ext_hsadc" - external HSADC clock - optional,
- - "ext_cif0" - external camera clock - optional,
- - "ext_rmii" - external RMII clock - optional,
- - "ext_jtag" - externalJTAG clock - optional
-
-Example: Clock controller node:
-
-	cru: cru@20000000 {
-		compatible = "rockchip,rk3188-cru";
-		reg = <0x20000000 0x1000>;
-		rockchip,grf = <&grf>;
-
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
-
-Example: UART controller node that consumes the clock generated by the clock
-  controller:
-
-	uart0: serial@10124000 {
-		compatible = "snps,dw-apb-uart";
-		reg = <0x10124000 0x400>;
-		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-		reg-shift = <2>;
-		reg-io-width = <1>;
-		clocks = <&cru SCLK_UART0>;
-	};

doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt

@@ -1,61 +0,0 @@
-* Rockchip RK3288 Clock and Reset Unit
-
-The RK3288 clock controller generates and supplies clock to various
-controllers within the SoC and also implements a reset controller for SoC
-peripherals.
-
-Required Properties:
-
-- compatible: should be "rockchip,rk3288-cru"
-- reg: physical base address of the controller and length of memory mapped
-  region.
-- #clock-cells: should be 1.
-- #reset-cells: should be 1.
-
-Optional Properties:
-
-- rockchip,grf: phandle to the syscon managing the "general register files"
-  If missing pll rates are not changable, due to the missing pll lock status.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. All available clocks are defined as
-preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
-used in device tree sources. Similar macros exist for the reset sources in
-these files.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xin24m" - crystal input - required,
- - "xin32k" - rtc clock - optional,
- - "ext_i2s" - external I2S clock - optional,
- - "ext_hsadc" - external HSADC clock - optional,
- - "ext_edp_24m" - external display port clock - optional,
- - "ext_vip" - external VIP clock - optional,
- - "ext_isp" - external ISP clock - optional,
- - "ext_jtag" - external JTAG clock - optional
-
-Example: Clock controller node:
-
-	cru: cru@20000000 {
-		compatible = "rockchip,rk3188-cru";
-		reg = <0x20000000 0x1000>;
-		rockchip,grf = <&grf>;
-
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
-
-Example: UART controller node that consumes the clock generated by the clock
-  controller:
-
-	uart0: serial@10124000 {
-		compatible = "snps,dw-apb-uart";
-		reg = <0x10124000 0x400>;
-		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-		reg-shift = <2>;
-		reg-io-width = <1>;
-		clocks = <&cru SCLK_UART0>;
-	};

doc/device-tree-bindings/clock/rockchip.txt

@@ -1,77 +0,0 @@
-Device Tree Clock bindings for arch-rockchip
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-== Gate clocks ==
-
-These bindings are deprecated!
-Please use the soc specific CRU bindings instead.
-
-The gate registers form a continuos block which makes the dt node
-structure a matter of taste, as either all gates can be put into
-one gate clock spanning all registers or they can be divided into
-the 10 individual gates containing 16 clocks each.
-The code supports both approaches.
-
-Required properties:
-- compatible : "rockchip,rk2928-gate-clk"
-- reg : shall be the control register address(es) for the clock.
-- #clock-cells : from common clock binding; shall be set to 1
-- clock-output-names : the corresponding gate names that the clock controls
-- clocks : should contain the parent clock for each individual gate,
-  therefore the number of clocks elements should match the number of
-  clock-output-names
-
-Example using multiple gate clocks:
-
-		clk_gates0: gate-clk@200000d0 {
-			compatible = "rockchip,rk2928-gate-clk";
-			reg = <0x200000d0 0x4>;
-			clocks = <&dummy>, <&dummy>,
-				 <&dummy>, <&dummy>,
-				 <&dummy>, <&dummy>,
-				 <&dummy>, <&dummy>,
-				 <&dummy>, <&dummy>,
-				 <&dummy>, <&dummy>,
-				 <&dummy>, <&dummy>,
-				 <&dummy>, <&dummy>;
-
-			clock-output-names =
-				"gate_core_periph", "gate_cpu_gpll",
-				"gate_ddrphy", "gate_aclk_cpu",
-				"gate_hclk_cpu", "gate_pclk_cpu",
-				"gate_atclk_cpu", "gate_i2s0",
-				"gate_i2s0_frac", "gate_i2s1",
-				"gate_i2s1_frac", "gate_i2s2",
-				"gate_i2s2_frac", "gate_spdif",
-				"gate_spdif_frac", "gate_testclk";
-
-			#clock-cells = <1>;
-		};
-
-		clk_gates1: gate-clk@200000d4 {
-			compatible = "rockchip,rk2928-gate-clk";
-			reg = <0x200000d4 0x4>;
-			clocks = <&xin24m>, <&xin24m>,
-				 <&xin24m>, <&dummy>,
-				 <&dummy>, <&xin24m>,
-				 <&xin24m>, <&dummy>,
-				 <&xin24m>, <&dummy>,
-				 <&xin24m>, <&dummy>,
-				 <&xin24m>, <&dummy>,
-				 <&xin24m>, <&dummy>;
-
-			clock-output-names =
-				"gate_timer0", "gate_timer1",
-				"gate_timer2", "gate_jtag",
-				"gate_aclk_lcdc1_src", "gate_otgphy0",
-				"gate_otgphy1", "gate_ddr_gpll",
-				"gate_uart0", "gate_frac_uart0",
-				"gate_uart1", "gate_frac_uart1",
-				"gate_uart2", "gate_frac_uart2",
-				"gate_uart3", "gate_frac_uart3";
-
-			#clock-cells = <1>;
-		};

doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt

@@ -1,157 +0,0 @@
-* Rockchip Pinmux Controller
-
-The Rockchip Pinmux Controller, enables the IC
-to share one PAD to several functional blocks. The sharing is done by
-multiplexing the PAD input/output signals. For each PAD there are several
-muxing options with option 0 being the use as a GPIO.
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-The Rockchip pin configuration node is a node of a group of pins which can be
-used for a specific device or function. This node represents both mux and
-config of the pins in that group. The 'pins' selects the function mode(also
-named pin mode) this pin can work on and the 'config' configures various pad
-settings such as pull-up, etc.
-
-The pins are grouped into up to 5 individual pin banks which need to be
-defined as gpio sub-nodes of the pinmux controller.
-
-Required properties for iomux controller:
-  - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
-		       "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
-		       "rockchip,rk3288-pinctrl"
-  - rockchip,grf: phandle referencing a syscon providing the
-	 "general register files"
-
-Optional properties for iomux controller:
-  - rockchip,pmu: phandle referencing a syscon providing the pmu registers
-	 as some SoCs carry parts of the iomux controller registers there.
-	 Required for at least rk3188 and rk3288.
-
-Deprecated properties for iomux controller:
-  - reg: first element is the general register space of the iomux controller
-	 It should be large enough to contain also separate pull registers.
-	 second element is the separate pull register space of the rk3188.
-	 Use rockchip,grf and rockchip,pmu described above instead.
-
-Required properties for gpio sub nodes:
-  - compatible: "rockchip,gpio-bank"
-  - reg: register of the gpio bank (different than the iomux registerset)
-  - interrupts: base interrupt of the gpio bank in the interrupt controller
-  - clocks: clock that drives this bank
-  - gpio-controller: identifies the node as a gpio controller and pin bank.
-  - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
-    binding is used, the amount of cells must be specified as 2. See generic
-    GPIO binding documentation for description of particular cells.
-  - interrupt-controller: identifies the controller node as interrupt-parent.
-  - #interrupt-cells: the value of this property should be 2 and the interrupt
-    cells should use the standard two-cell scheme described in
-    bindings/interrupt-controller/interrupts.txt
-
-Deprecated properties for gpio sub nodes:
-  - compatible: "rockchip,rk3188-gpio-bank0"
-  - reg: second element: separate pull register for rk3188 bank0, use
-	 rockchip,pmu described above instead
-
-Required properties for pin configuration node:
-  - rockchip,pins: 3 integers array, represents a group of pins mux and config
-    setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
-    The MUX 0 means gpio and MUX 1 to N mean the specific device function.
-    The phandle of a node containing the generic pinconfig options
-    to use, as described in pinctrl-bindings.txt in this directory.
-
-Examples:
-
-#include <dt-bindings/pinctrl/rockchip.h>
-
-...
-
-pinctrl@20008000 {
-	compatible = "rockchip,rk3066a-pinctrl";
-	rockchip,grf = <&grf>;
-
-	#address-cells = <1>;
-	#size-cells = <1>;
-	ranges;
-
-	gpio0: gpio0@20034000 {
-		compatible = "rockchip,gpio-bank";
-		reg = <0x20034000 0x100>;
-		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk_gates8 9>;
-
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	...
-
-	pcfg_pull_default: pcfg_pull_default {
-		bias-pull-pin-default
-	};
-
-	uart2 {
-		uart2_xfer: uart2-xfer {
-			rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
-					<RK_GPIO1 9 1 &pcfg_pull_default>;
-		};
-	};
-};
-
-uart2: serial@20064000 {
-	compatible = "snps,dw-apb-uart";
-	reg = <0x20064000 0x400>;
-	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-	reg-shift = <2>;
-	reg-io-width = <1>;
-	clocks = <&mux_uart2>;
-	status = "okay";
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_xfer>;
-};
-
-Example for rk3188:
-
-	pinctrl@20008000 {
-		compatible = "rockchip,rk3188-pinctrl";
-		rockchip,grf = <&grf>;
-		rockchip,pmu = <&pmu>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		gpio0: gpio0@0x2000a000 {
-			compatible = "rockchip,rk3188-gpio-bank0";
-			reg = <0x2000a000 0x100>;
-			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_gates8 9>;
-
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		gpio1: gpio1@0x2003c000 {
-			compatible = "rockchip,gpio-bank";
-			reg = <0x2003c000 0x100>;
-			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_gates8 10>;
-
-			gpio-controller;
-			#gpio-cells = <2>;
-
-			interrupt-controller;
-			#interrupt-cells = <2>;
-		};
-
-		...
-
-	};

doc/device-tree-bindings/thermal/rockchip-thermal.txt

@@ -1,68 +0,0 @@
-* Temperature Sensor ADC (TSADC) on rockchip SoCs
-
-Required properties:
-- compatible : "rockchip,rk3288-tsadc"
-- reg : physical base address of the controller and length of memory mapped
-	region.
-- interrupts : The interrupt number to the cpu. The interrupt specifier format
-	       depends on the interrupt controller.
-- clocks : Must contain an entry for each entry in clock-names.
-- clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for
-		the peripheral clock.
-- resets : Must contain an entry for each entry in reset-names.
-	   See ../reset/reset.txt for details.
-- reset-names : Must include the name "tsadc-apb".
-- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description.
-- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value.
-- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO.
-- rockchip,hw-tshut-polarity : The hardware-controlled active polarity 0:LOW
-			       1:HIGH.
-
-Exiample:
-tsadc: tsadc@ff280000 {
-	compatible = "rockchip,rk3288-tsadc";
-	reg = <0xff280000 0x100>;
-	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-	clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
-	clock-names = "tsadc", "apb_pclk";
-	resets = <&cru SRST_TSADC>;
-	reset-names = "tsadc-apb";
-	pinctrl-names = "default";
-	pinctrl-0 = <&otp_out>;
-	#thermal-sensor-cells = <1>;
-	rockchip,hw-tshut-temp = <95000>;
-	rockchip,hw-tshut-mode = <0>;
-	rockchip,hw-tshut-polarity = <0>;
-};
-
-Example: referring to thermal sensors:
-thermal-zones {
-	cpu_thermal: cpu_thermal {
-		polling-delay-passive = <1000>; /* milliseconds */
-		polling-delay = <5000>; /* milliseconds */
-
-		/* sensor	ID */
-		thermal-sensors = <&tsadc	1>;
-
-		trips {
-			cpu_alert0: cpu_alert {
-				temperature = <70000>; /* millicelsius */
-				hysteresis = <2000>; /* millicelsius */
-				type = "passive";
-			};
-			cpu_crit: cpu_crit {
-				temperature = <90000>; /* millicelsius */
-				hysteresis = <2000>; /* millicelsius */
-				type = "critical";
-			};
-		};
-
-		cooling-maps {
-			map0 {
-				trip = <&cpu_alert0>;
-				cooling-device =
-				    <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-			};
-		};
-	};
-};

doc/device-tree-bindings/usb/dwc2.txt

@@ -5,10 +5,6 @@ Required properties:
 - compatible : One of:
   - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
   - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC.
-  - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
-  - "rockchip,px30-usb", "rockchip,rk3066-usb", "snps,dwc2": for px30 Soc;
-  - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
-  - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
   - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
   - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
   - "amlogic,meson8-usb": The DWC2 USB controller instance in Amlogic Meson8 SoCs;

doc/device-tree-bindings/video/rockchip-lvds.txt

@@ -1,77 +0,0 @@
-Rockchip LVDS interface
-------------------
-
-Required properties:
-- compatible: "rockchip,rk3288-lvds";
-
-- reg: physical base address of the controller and length
-	of memory mapped region.
-- clocks: must include clock specifiers corresponding to entries in the
-	clock-names property.
-- clock-names: must contain "pclk_lvds"
-
-- rockchip,grf: phandle to the general register files syscon
-
-- rockchip,data-mapping: should be <LVDS_FORMAT_VESA> or  <LVDS_FORMAT_JEIDA>,
-	This describes how the color bits are laid out in the
-	serialized LVDS signal.
-- rockchip,data-width : should be <18> or <24>;
-- rockchip,output: should be <LVDS_OUTPUT_RGB>, <LVDS_OUTPUT_SINGLE> or
-	<LVDS_OUTPUT_DUAL>, This describes the output face.
-
-- display-timings : described by
-	doc/device-tree-bindings/video/display-timing.txt.
-
-Example:
-	lvds: lvds@ff96c000 {
-		compatible = "rockchip,rk3288-lvds";
-		reg = <0xff96c000 0x4000>;
-		clocks = <&cru PCLK_LVDS_PHY>;
-		clock-names = "pclk_lvds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&lcdc0_ctl>;
-		rockchip,grf = <&grf>;
-		status = "disabled";
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			lvds_in: port@0 {
-				reg = <0>;
-
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				lvds_in_vopb: endpoint@0 {
-					reg = <0>;
-					remote-endpoint = <&vopb_out_lvds>;
-				};
-				lvds_in_vopl: endpoint@1 {
-					reg = <1>;
-					remote-endpoint = <&vopl_out_lvds>;
-				};
-			};
-		};
-	};
-
-	&lvds {
-		rockchip,data-mapping = <LVDS_FORMAT_VESA>;
-		rockchip,data-width = <24>;
-		rockchip,output = <LVDS_OUTPUT_DUAL>;
-		rockchip,panel = <&panel>;
-		status = "okay";
-
-		display-timings {
-			timing@0 {
-				clock-frequency = <40000000>;
-				hactive = <1920>;
-				vactive = <1080>;
-				hsync-len = <44>;
-				hfront-porch = <88>;
-				hback-porch = <148>;
-				vfront-porch = <4>;
-				vback-porch = <36>;
-				vsync-len = <5>;
-			};
-		};
-	};

doc/usage/environment.rst

@@ -499,12 +499,12 @@ Automatically updated variables
 -------------------------------
 
 The following environment variables may be used and automatically
-updated by the network boot commands ("bootp" and "rarpboot"),
+updated by the network boot commands ("bootp", "dhcp" and "rarpboot"),
 depending the information provided by your boot server:
 
-=========  ===================================================
+========== ===================================================================
 Variable   Notes
-=========  ===================================================
+========== ===================================================================
 bootfile   see above
 dnsip      IP address of your Domain Name Server
 dnsip2     IP address of your secondary Domain Name Server
@@ -514,7 +514,10 @@ ipaddr     See above
 netmask    Subnet Mask
 rootpath   Pathname of the root filesystem on the NFS server
 serverip   see above
-=========  ===================================================
+ipaddrN    IP address for interface N (>0) (NET_LWIP dhcp only)
+netmaskN   Subnet mask for interface N (>0) (NET_LWIP dhcp only)
+gatewayipN IP address of the Gateway for interface N (>0) (NET_LWIP dhcp only)
+========== ===================================================================
 
 
 Special environment variables

drivers/clk/mpc83xx_clk.h

@@ -321,7 +321,7 @@ static inline u32 get_pci_sync_in(immap_t *im)
 }
 
 /**
- * get_csb_clk() - Read the CSB (Coheren System Bus) clock speed
+ * get_csb_clk() - Read the CSB (Coherent System Bus) clock speed
  * @im: Pointer to the MPC83xx main register map in question
  *
  * Return: The CSB clock speed value as a 32-bit number.

drivers/clk/renesas/Kconfig

@@ -5,20 +5,20 @@ config CLK_RENESAS
 	  Enable support for clock present on Renesas SoCs.
 
 config CLK_RCAR
-	bool "Renesas RCar clock driver support"
+	bool "Renesas R-Car clock driver support"
 	help
-	  Enable common code for clocks on Renesas RCar SoCs.
+	  Enable common code for clocks on Renesas R-Car SoCs.
 
 config CLK_RCAR_CPG_LIB
 	bool "CPG/MSSR library functions"
 
 config CLK_RCAR_GEN2
-	bool "Renesas RCar Gen2 clock driver"
+	bool "Renesas R-Car Gen2 clock driver"
 	def_bool y if RCAR_32
 	depends on CLK_RENESAS
 	select CLK_RCAR
 	help
-	  Enable this to support the clocks on Renesas RCar Gen2 SoC.
+	  Enable this to support the clocks on Renesas R-Car Gen2 SoC.
 
 config CLK_R8A7790
 	bool "Renesas R8A7790 clock driver"
@@ -51,14 +51,14 @@ config CLK_R8A7794
 	  Enable this to support the clocks on Renesas R8A7794 SoC.
 
 config CLK_RCAR_GEN3
-	bool "Renesas RCar Gen3 and Gen4 clock driver"
+	bool "Renesas R-Car Gen3 and Gen4 clock driver"
 	def_bool y if RCAR_64
 	depends on CLK_RENESAS
 	select CLK_RCAR
 	select CLK_RCAR_CPG_LIB
 	select DM_RESET
 	help
-	  Enable this to support the clocks on Renesas RCar Gen3 and Gen4 SoCs.
+	  Enable this to support the clocks on Renesas R-Car Gen3 and Gen4 SoCs.
 
 config CLK_R8A774A1
         bool "Renesas R8A774A1 clock driver"

drivers/clk/renesas/clk-rcar-gen2.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Renesas RCar Gen2 CPG MSSR driver
+ * Renesas R-Car Gen2 CPG MSSR driver
  *
  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
  *

drivers/clk/renesas/clk-rcar-gen3.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Renesas RCar Gen3 CPG MSSR driver
+ * Renesas R-Car Gen3 CPG MSSR driver
  *
  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
  *

drivers/clk/renesas/r8a779h0-cpg-mssr.c

@@ -39,7 +39,6 @@ enum clk_ids {
 	CLK_PLL6,
 	CLK_PLL7,
 	CLK_PLL1_DIV2,
-	CLK_PLL2_DIV2,
 	CLK_PLL3_DIV2,
 	CLK_PLL4_DIV2,
 	CLK_PLL4_DIV5,
@@ -82,7 +81,6 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = {
 	DEF_BASE(".pll7", CLK_PLL7,	CLK_TYPE_GEN4_PLL7,	CLK_MAIN),
 
 	DEF_FIXED(".pll1_div2",	CLK_PLL1_DIV2,	CLK_PLL1,	2, 1),
-	DEF_FIXED(".pll2_div2",	CLK_PLL2_DIV2,	CLK_PLL2,	2, 1),
 	DEF_FIXED(".pll3_div2",	CLK_PLL3_DIV2,	CLK_PLL3,	2, 1),
 	DEF_FIXED(".pll4_div2",	CLK_PLL4_DIV2,	CLK_PLL4,	2, 1),
 	DEF_FIXED(".pll4_div5",	CLK_PLL4_DIV5,	CLK_PLL4,	5, 1),
@@ -106,10 +104,10 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = {
 	DEF_RATE(".oco",	CLK_OCO,	32768),
 
 	/* Core Clock Outputs */
-	DEF_GEN4_Z("zc0",	R8A779H0_CLK_ZC0,	CLK_TYPE_GEN4_Z,	CLK_PLL2_DIV2,	2, 0),
+	DEF_GEN4_Z("zc0",	R8A779H0_CLK_ZC0,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, 0),
-	DEF_GEN4_Z("zc1",	R8A779H0_CLK_ZC1,	CLK_TYPE_GEN4_Z,	CLK_PLL2_DIV2,	2, 8),
+	DEF_GEN4_Z("zc1",	R8A779H0_CLK_ZC1,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, 8),
-	DEF_GEN4_Z("zc2",	R8A779H0_CLK_ZC2,	CLK_TYPE_GEN4_Z,	CLK_PLL2_DIV2,	2, 32),
+	DEF_GEN4_Z("zc2",	R8A779H0_CLK_ZC2,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, 32),
-	DEF_GEN4_Z("zc3",	R8A779H0_CLK_ZC3,	CLK_TYPE_GEN4_Z,	CLK_PLL2_DIV2,	2, 40),
+	DEF_GEN4_Z("zc3",	R8A779H0_CLK_ZC3,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, 40),
 	DEF_FIXED("s0d2",	R8A779H0_CLK_S0D2,	CLK_S0,		2, 1),
 	DEF_FIXED("s0d3",	R8A779H0_CLK_S0D3,	CLK_S0,		3, 1),
 	DEF_FIXED("s0d4",	R8A779H0_CLK_S0D4,	CLK_S0,		4, 1),

drivers/clk/renesas/rcar-cpg-lib.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Renesas RCar Gen3 CPG MSSR driver
+ * Renesas R-Car Gen3 CPG MSSR driver
  *
  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
  *

drivers/clk/renesas/renesas-cpg-mssr.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Renesas RCar Gen3 CPG MSSR driver
+ * Renesas R-Car Gen3 CPG MSSR driver
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  *

drivers/clk/renesas/renesas-cpg-mssr.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Renesas RCar Gen3 CPG MSSR driver
+ * Renesas R-Car Gen3 CPG MSSR driver
  *
  * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
  *

drivers/clk/tegra/tegra-car-clk.c

@@ -10,6 +10,9 @@
 #include <asm/arch/clock.h>
 #include <asm/arch-tegra/clk_rst.h>
 
+#define TEGRA_CAR_CLK_PLL	BIT(0)
+#define TEGRA_CAR_CLK_PERIPH	BIT(1)
+
 static int tegra_car_clk_request(struct clk *clk)
 {
 	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
@@ -20,24 +23,41 @@ static int tegra_car_clk_request(struct clk *clk)
 	 * varies per SoC) are the peripheral clocks, which use a numbering
 	 * scheme that matches HW registers 1:1. There are other clock IDs
 	 * beyond this that are assigned arbitrarily by the Tegra CAR DT
-	 * binding. Due to the implementation of this driver, it currently
+	 * binding.
-	 * only supports the peripheral IDs.
 	 */
-	if (clk->id >= PERIPH_ID_COUNT)
+	if (clk->id < PERIPH_ID_COUNT) {
-		return -EINVAL;
+		clk->data |= TEGRA_CAR_CLK_PERIPH;
+		return 0;
+	}
 
-	return 0;
+	/* If check for periph failed, then check for PLL clock id */
+	int id = clk_id_to_pll_id(clk->id);
+
+	if (clock_id_is_pll(id)) {
+		clk->id = id;
+		clk->data |= TEGRA_CAR_CLK_PLL;
+		return 0;
+	}
+
+	return -EINVAL;
 }
 
 static ulong tegra_car_clk_get_rate(struct clk *clk)
 {
-	enum clock_id parent;
-
 	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
 	      clk->id);
 
-	parent = clock_get_periph_parent(clk->id);
+	if (clk->data & TEGRA_CAR_CLK_PLL)
-	return clock_get_periph_rate(clk->id, parent);
+		return clock_get_rate(clk->id);
+
+	if (clk->data & TEGRA_CAR_CLK_PERIPH) {
+		enum clock_id parent;
+
+		parent = clock_get_periph_parent(clk->id);
+		return clock_get_periph_rate(clk->id, parent);
+	}
+
+	return -1U;
 }
 
 static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
@@ -47,6 +67,9 @@ static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
 	debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
 	      clk->dev, clk->id);
 
+	if (clk->data & TEGRA_CAR_CLK_PLL)
+		return 0;
+
 	parent = clock_get_periph_parent(clk->id);
 	return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
 }
@@ -56,6 +79,9 @@ static int tegra_car_clk_enable(struct clk *clk)
 	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
 	      clk->id);
 
+	if (clk->data & TEGRA_CAR_CLK_PLL)
+		return 0;
+
 	clock_enable(clk->id);
 
 	return 0;
@@ -66,6 +92,9 @@ static int tegra_car_clk_disable(struct clk *clk)
 	debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
 	      clk->id);
 
+	if (clk->data & TEGRA_CAR_CLK_PLL)
+		return 0;
+
 	clock_disable(clk->id);
 
 	return 0;
@@ -83,6 +112,9 @@ static int tegra_car_clk_probe(struct udevice *dev)
 {
 	debug("%s(dev=%p)\n", __func__, dev);
 
+	clock_init();
+	clock_verify();
+
 	return 0;
 }
 

drivers/gpio/Kconfig

@@ -358,10 +358,10 @@ config PCF8575_GPIO
 	 chips are from NXP and TI.
 
 config RCAR_GPIO
-	bool "Renesas RCar GPIO driver"
+	bool "Renesas R-Car GPIO driver"
 	depends on DM_GPIO && ARCH_RENESAS
 	help
-	  This driver supports the GPIO banks on Renesas RCar SoCs.
+	  This driver supports the GPIO banks on Renesas R-Car SoCs.
 
 config RZA1_GPIO
 	bool "Renesas RZ/A1 GPIO driver"

drivers/i2c/Kconfig

@@ -504,16 +504,16 @@ config SYS_I2C_OMAP24XX
 	  Add support for the OMAP2+ I2C driver.
 
 config SYS_I2C_RCAR_I2C
-	bool "Renesas RCar I2C driver"
+	bool "Renesas R-Car I2C driver"
 	depends on (RCAR_GEN2 || RCAR_64) && DM_I2C
 	help
-	  Support for Renesas RCar I2C controller.
+	  Support for Renesas R-Car I2C controller.
 
 config SYS_I2C_RCAR_IIC
-	bool "Renesas RCar Gen3 IIC driver"
+	bool "Renesas R-Car Gen3 IIC driver"
 	depends on (RCAR_GEN2 || RCAR_GEN3) && DM_I2C
 	help
-	  Support for Renesas RCar Gen3 IIC controller.
+	  Support for Renesas R-Car Gen3 IIC controller.
 
 config SYS_I2C_ROCKCHIP
 	bool "Rockchip I2C driver"

drivers/i2c/rcar_iic.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Renesas RCar IIC driver
+ * Renesas R-Car IIC driver
  *
  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
  *

drivers/mmc/mmc.c

@@ -750,7 +750,7 @@ static int mmc_send_op_cond(struct mmc *mmc)
 {
 	int err, i;
 	int timeout = 1000;
-	uint start;
+	ulong start;
 
 	/* Some cards seem to need this */
 	mmc_go_idle(mmc);
@@ -844,7 +844,8 @@ int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
 static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
 			bool send_status)
 {
-	unsigned int status, start;
+	ulong start;
+	unsigned int status;
 	struct mmc_cmd cmd;
 	int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
 	bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&

drivers/mmc/renesas-sdhi.c

@@ -571,7 +571,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
 	int i, ret = 0, sret;
 	u32 caps, reg;
 
-	/* Only supported on Renesas RCar */
+	/* Only supported on Renesas R-Car */
 	if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
 		return -EINVAL;
 

drivers/mmc/tmio-common.h

@@ -64,7 +64,7 @@
 #define   TMIO_SD_CLKCTL_DIV4		BIT(0)	/* SDCLK = CLK / 4 */
 #define   TMIO_SD_CLKCTL_DIV2		0	/* SDCLK = CLK / 2 */
 #define   TMIO_SD_CLKCTL_DIV1		BIT(10)	/* SDCLK = CLK */
-#define   TMIO_SD_CLKCTL_RCAR_DIV1	0xff	/* SDCLK = CLK (RCar ver.) */
+#define   TMIO_SD_CLKCTL_RCAR_DIV1	0xff	/* SDCLK = CLK (R-Car ver.) */
 #define   TMIO_SD_CLKCTL_OFFEN		BIT(9)	/* stop SDCLK when unused */
 #define   TMIO_SD_CLKCTL_SCLKEN	BIT(8)	/* SDCLK output enable */
 #define TMIO_SD_SIZE			0x04c	/* block size */
@@ -90,7 +90,7 @@
 #define   TMIO_SD_VOLT_180		(2 << 0)/* 1.8V signal */
 #define TMIO_SD_DMA_MODE		0x410
 #define   TMIO_SD_DMA_MODE_DIR_RD	BIT(16)	/* 1: from device, 0: to dev */
-#define   TMIO_SD_DMA_MODE_BUS_WIDTH	(BIT(5) | BIT(4)) /* RCar, 64bit */
+#define   TMIO_SD_DMA_MODE_BUS_WIDTH	(BIT(5) | BIT(4)) /* R-Car, 64bit */
 #define   TMIO_SD_DMA_MODE_ADDR_INC	BIT(0)	/* 1: address inc, 0: fixed */
 #define TMIO_SD_DMA_CTL		0x414
 #define   TMIO_SD_DMA_CTL_START	BIT(0)	/* start DMA (auto cleared) */
@@ -128,9 +128,9 @@ struct tmio_sd_priv {
 #define TMIO_SD_CAP_DIV1024		BIT(2)	/* divisor 1024 is available */
 #define TMIO_SD_CAP_64BIT		BIT(3)	/* Controller is 64bit */
 #define TMIO_SD_CAP_16BIT		BIT(4)	/* Controller is 16bit */
-#define TMIO_SD_CAP_RCAR_GEN2		BIT(5)	/* Renesas RCar version of IP */
+#define TMIO_SD_CAP_RCAR_GEN2		BIT(5)	/* Renesas R-Car version of IP */
-#define TMIO_SD_CAP_RCAR_GEN3		BIT(6)	/* Renesas RCar version of IP */
+#define TMIO_SD_CAP_RCAR_GEN3		BIT(6)	/* Renesas R-Car version of IP */
-#define TMIO_SD_CAP_RCAR_UHS		BIT(7)	/* Renesas RCar UHS/SDR modes */
+#define TMIO_SD_CAP_RCAR_UHS		BIT(7)	/* Renesas R-Car UHS/SDR modes */
 #define TMIO_SD_CAP_RCAR		\
 	(TMIO_SD_CAP_RCAR_GEN2 | TMIO_SD_CAP_RCAR_GEN3)
 	struct udevice *vqmmc_dev;

drivers/mtd/Kconfig

@@ -194,11 +194,11 @@ config ALTERA_QSPI
 	  "Embedded Peripherals IP User Guide" of Altera.
 
 config RENESAS_RPC_HF
-	bool "Renesas RCar Gen3 RPC HyperFlash driver"
+	bool "Renesas R-Car Gen3 RPC HyperFlash driver"
 	depends on RCAR_GEN3 && DM_MTD
 	help
 	  This enables access to HyperFlash memory through the Renesas
-	  RCar Gen3 RPC controller.
+	  R-Car Gen3 RPC controller.
 
 config HBMC_AM654
 	bool "HyperBus controller driver for AM65x SoC"

drivers/mtd/renesas_rpc_hf.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Renesas RCar Gen3 RPC HyperFlash driver
+ * Renesas R-Car Gen3 RPC HyperFlash driver
  *
  * Copyright (C) 2016 Renesas Electronics Corporation
  * Copyright (C) 2016 Cogent Embedded, Inc.

drivers/net/rswitch.c

@@ -837,6 +837,7 @@ static int rswitch_send(struct udevice *dev, void *packet, int len)
 
 	/* Update TX descriptor */
 	rswitch_flush_dcache((uintptr_t)packet, len);
+	rswitch_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
 	memset(desc, 0x0, sizeof(*desc));
 	desc->die_dt = DT_FSINGLE;
 	desc->info_ds = len;
@@ -1112,6 +1113,9 @@ static int rswitch_bind(struct udevice *parent)
 		return -ENOENT;
 
 	ofnode_for_each_subnode(node, ports_np) {
+		if (!ofnode_is_enabled(node))
+			continue;
+
 		ret = device_bind_with_driver_data(parent, drv,
 						   ofnode_get_name(node),
 						   (ulong)priv, node, &dev);

drivers/pci/Kconfig

@@ -189,19 +189,19 @@ config PCI_MSC01
 	depends on TARGET_MALTA
 
 config PCI_RCAR_GEN2
-	bool "Renesas RCar Gen2 PCIe driver"
+	bool "Renesas R-Car Gen2 PCIe driver"
 	depends on RCAR_32
 	help
 	  Say Y here if you want to enable PCIe controller support on
-	  Renesas RCar Gen2 SoCs. The PCIe controller on RCar Gen2 is
+	  Renesas R-Car Gen2 SoCs. The PCIe controller on R-Car Gen2 is
 	  also used to access EHCI USB controller on the SoC.
 
 config PCI_RCAR_GEN3
-	bool "Renesas RCar Gen3 PCIe driver"
+	bool "Renesas R-Car Gen3 PCIe driver"
 	depends on RCAR_GEN3
 	help
 	  Say Y here if you want to enable PCIe controller support on
-	  Renesas RCar Gen3 SoCs.
+	  Renesas R-Car Gen3 SoCs.
 
 config PCI_SANDBOX
 	bool "Sandbox PCI support"

drivers/pci/pci-rcar-gen2.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Renesas RCar Gen2 PCIEC driver
+ * Renesas R-Car Gen2 PCIEC driver
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

drivers/pci/pci-rcar-gen3.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Renesas RCar Gen3 PCIEC driver
+ * Renesas R-Car Gen3 PCIEC driver
  *
  * Copyright (C) 2018-2019 Marek Vasut <marek.vasut@gmail.com>
  *

drivers/phy/phy-rcar-gen2.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Renesas RCar Gen2 USB PHY driver
+ * Renesas R-Car Gen2 USB PHY driver
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

drivers/phy/phy-rcar-gen3.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Renesas RCar Gen3 USB PHY driver
+ * Renesas R-Car Gen3 USB PHY driver
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

drivers/pinctrl/renesas/Kconfig

@@ -23,34 +23,34 @@ config PINCTRL_PFC_FULL
 	  U-Boot driver.
 
 config PINCTRL_PFC_R8A7790
-	bool "Renesas RCar Gen2 R8A7790 pin control driver"
+	bool "Renesas R-Car Gen2 R8A7790 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen2 R8A7790 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen2 R8A7790 SoCs.
 
 config PINCTRL_PFC_R8A7791
-	bool "Renesas RCar Gen2 R8A7791 pin control driver"
+	bool "Renesas R-Car Gen2 R8A7791 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen2 R8A7791 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen2 R8A7791 SoCs.
 
 config PINCTRL_PFC_R8A7792
-	bool "Renesas RCar Gen2 R8A7792 pin control driver"
+	bool "Renesas R-Car Gen2 R8A7792 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen2 R8A7792 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen2 R8A7792 SoCs.
 
 config PINCTRL_PFC_R8A7793
-	bool "Renesas RCar Gen2 R8A7793 pin control driver"
+	bool "Renesas R-Car Gen2 R8A7793 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen2 R8A7793 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen2 R8A7793 SoCs.
 
 config PINCTRL_PFC_R8A7794
-	bool "Renesas RCar Gen2 R8A7794 pin control driver"
+	bool "Renesas R-Car Gen2 R8A7794 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen2 R8A7794 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen2 R8A7794 SoCs.
 
 config PINCTRL_PFC_R8A774A1
         bool "Renesas RZ/G2 R8A774A1 pin control driver"
@@ -77,76 +77,76 @@ config PINCTRL_PFC_R8A774E1
           Support pin multiplexing control on Renesas RZ/G2H R8A774E1 SoCs.
 
 config PINCTRL_PFC_R8A77951
-	bool "Renesas RCar Gen3 R8A7795 pin control driver"
+	bool "Renesas R-Car Gen3 R8A7795 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen3 R8A7795 SoCs.
 
 config PINCTRL_PFC_R8A77960
-	bool "Renesas RCar Gen3 R8A77960 pin control driver"
+	bool "Renesas R-Car Gen3 R8A77960 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen3 R8A77960 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen3 R8A77960 SoCs.
 
 config PINCTRL_PFC_R8A77961
-	bool "Renesas RCar Gen3 R8A77961 pin control driver"
+	bool "Renesas R-Car Gen3 R8A77961 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen3 R8A77961 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen3 R8A77961 SoCs.
 
 config PINCTRL_PFC_R8A77965
-	bool "Renesas RCar Gen3 R8A77965 pin control driver"
+	bool "Renesas R-Car Gen3 R8A77965 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen3 R8A77965 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen3 R8A77965 SoCs.
 
 config PINCTRL_PFC_R8A77970
-	bool "Renesas RCar Gen3 R8A77970 pin control driver"
+	bool "Renesas R-Car Gen3 R8A77970 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen3 R8A77970 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen3 R8A77970 SoCs.
 
 config PINCTRL_PFC_R8A77980
-	bool "Renesas RCar Gen3 R8A77980 pin control driver"
+	bool "Renesas R-Car Gen3 R8A77980 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen3 R8A77980 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen3 R8A77980 SoCs.
 
 config PINCTRL_PFC_R8A77990
-	bool "Renesas RCar Gen3 R8A77990 pin control driver"
+	bool "Renesas R-Car Gen3 R8A77990 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen3 R8A77990 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen3 R8A77990 SoCs.
 
 config PINCTRL_PFC_R8A77995
-	bool "Renesas RCar Gen3 R8A77995 pin control driver"
+	bool "Renesas R-Car Gen3 R8A77995 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen3 R8A77995 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen3 R8A77995 SoCs.
 
 config PINCTRL_PFC_R8A779A0
-	bool "Renesas RCar Gen3 R8A779A0 pin control driver"
+	bool "Renesas R-Car Gen3 R8A779A0 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen3 R8A779A0 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen3 R8A779A0 SoCs.
 
 config PINCTRL_PFC_R8A779F0
-	bool "Renesas RCar Gen4 R8A779F0 pin control driver"
+	bool "Renesas R-Car Gen4 R8A779F0 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen4 R8A779F0 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen4 R8A779F0 SoCs.
 
 config PINCTRL_PFC_R8A779G0
-	bool "Renesas RCar Gen4 R8A779G0 pin control driver"
+	bool "Renesas R-Car Gen4 R8A779G0 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen4 R8A779G0 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen4 R8A779G0 SoCs.
 
 config PINCTRL_PFC_R8A779H0
-	bool "Renesas RCar Gen4 R8A779H0 pin control driver"
+	bool "Renesas R-Car Gen4 R8A779H0 pin control driver"
 	depends on PINCTRL_PFC
 	help
-	  Support pin multiplexing control on Renesas RCar Gen4 R8A779H0 SoCs.
+	  Support pin multiplexing control on Renesas R-Car Gen4 R8A779H0 SoCs.
 
 config PINCTRL_RZA1
 	bool "Renesas RZ/A1 R7S72100 pin control driver"

drivers/serial/Kconfig

@@ -920,7 +920,7 @@ config SCIF_CONSOLE
 	depends on SH || ARCH_RENESAS
 	help
 	  Select this to enable Renesas SCIF UART. To operate serial ports
-	  on systems with RCar or SH SoCs, say Y to this option. If unsure,
+	  on systems with R-Car or SH SoCs, say Y to this option. If unsure,
 	  say N.
 
 choice

drivers/spi/Kconfig

@@ -420,7 +420,7 @@ config RENESAS_RPC_SPI
 	imply SPI_FLASH_SFDP_SUPPORT
 	help
 	  Enable the Renesas RPC SPI driver, used to access SPI NOR flash
-	  on Renesas RCar Gen3 SoCs. This uses driver model and requires a
+	  on Renesas R-Car Gen3 SoCs. This uses driver model and requires a
 	  device tree binding to operate.
 
 config ROCKCHIP_SFC

drivers/spi/renesas_rpc_spi.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Renesas RCar Gen3 RPC QSPI driver
+ * Renesas R-Car Gen3 RPC QSPI driver
  *
  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  */

drivers/usb/gadget/Kconfig

@@ -115,10 +115,10 @@ config USB_GADGET_DWC2_OTG
 	  USB_GADGET to be enabled.
 
 config USB_RENESAS_USBHS
-	bool "Renesas RCar USB2.0 HS controller (gadget mode)"
+	bool "Renesas R-Car USB2.0 HS controller (gadget mode)"
 	select USB_GADGET_DUALSPEED
 	help
-	  The Renesas Rcar USB 2.0 high-speed gadget controller
+	  The Renesas R-Car USB 2.0 high-speed gadget controller
 	  integrated into Salvator and Kingfisher boards. Select this
 	  option if you want the driver to operate in Peripheral mode.
 	  This option requires USB_GADGET to be enabled.

drivers/usb/host/Kconfig

@@ -103,12 +103,12 @@ config USB_XHCI_PCI
 	  Enables support for the PCI-based xHCI controller.
 
 config USB_XHCI_RCAR
-	bool "Renesas RCar USB 3.0 support"
+	bool "Renesas R-Car USB 3.0 support"
 	default y
 	depends on ARCH_RENESAS
 	help
 	  Choose this option to add support for USB 3.0 driver on Renesas
-	  RCar Gen3 SoCs.
+	  R-Car Gen3 SoCs.
 
 config USB_XHCI_STI
 	bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller"

drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h

@@ -1,5 +1,5 @@
 /*
- * Renesas RCar xHCI controller firmware version 3
+ * Renesas R-Car xHCI controller firmware version 3
  *
  * Copyright (c) 2014, Renesas Electronics Corporation
  * All rights reserved.

drivers/usb/host/xhci-rcar.c

@@ -2,7 +2,7 @@
 /*
  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
  *
- * Renesas RCar USB HOST xHCI Controller
+ * Renesas R-Car USB HOST xHCI Controller
  */
 
 #include <clk.h>

drivers/video/zynqmp/zynqmp_dpsub.c

@@ -11,6 +11,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <generic-phy.h>
+#include <reset.h>
 #include <stdlib.h>
 #include <video.h>
 #include <wait_bit.h>
@@ -2093,10 +2094,15 @@ static int zynqmp_dpsub_probe(struct udevice *dev)
 {
 	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct zynqmp_dpsub_priv *priv = dev_get_priv(dev);
+	struct reset_ctl_bulk resets;
 	struct clk clk;
 	int ret;
 	int mode = RGBA8888;
 
+	ret = reset_get_bulk(dev, &resets);
+	if (!ret)
+		reset_deassert_bulk(&resets);
+
 	ret = clk_get_by_name(dev, "dp_apb_clk", &clk);
 	if (ret < 0) {
 		dev_err(dev, "failed to get clock\n");

include/configs/ls1028ardb.h

@@ -53,6 +53,7 @@
 #define CFG_EXTRA_ENV_SETTINGS		\
 	"board=ls1028ardb\0"			\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"fdtfile=fsl-ls1028a-rdb.dtb\0"         \
 	"ramdisk_addr=0x800000\0"		\
 	"ramdisk_size=0x2000000\0"		\
 	"bootm_size=0x10000000\0"		\