From 0e24474cc323a9012bf1f0942f46d1053e326b3f Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Wed, 4 Dec 2024 12:55:20 +0530 Subject: [PATCH 01/70] usb: onboard-hub: Update the bind function based on peer-hub property As the "peer-hub" property is optional, don't error out just skip the bind function. Fixes: 57e30b09fc ("usb: onboard-hub: Bail out if peer hub is already probed") Signed-off-by: Venkatesh Yadav Abbarapu Acked-by: Michal Simek Reviewed-by: Patrice Chotard Tested-by: Patrice Chotard --- common/usb_onboard_hub.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/common/usb_onboard_hub.c b/common/usb_onboard_hub.c index 6f28036e095..7fe62b043e6 100644 --- a/common/usb_onboard_hub.c +++ b/common/usb_onboard_hub.c @@ -183,7 +183,12 @@ static int usb_onboard_hub_bind(struct udevice *dev) int ret, off; ret = dev_read_phandle_with_args(dev, "peer-hub", NULL, 0, 0, &phandle); - if (ret) { + if (ret == -ENOENT) { + dev_dbg(dev, "peer-hub property not present\n"); + return 0; + } + + if (ret) { dev_err(dev, "peer-hub not specified\n"); return ret; } From c1b9d3eb88a3d0318f4a724f8c5ed3ecf60fc08c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 11 Dec 2024 08:30:25 +0100 Subject: [PATCH 02/70] ARM: dts: renesas: Fix R-Car spelling The correct spelling is R-Car, including the dash, update the usage. Comment change only, no functional change. Signed-off-by: Marek Vasut --- arch/arm/dts/r8a7790-u-boot.dtsi | 2 +- arch/arm/dts/r8a7791-u-boot.dtsi | 2 +- arch/arm/dts/r8a7792-u-boot.dtsi | 2 +- arch/arm/dts/r8a7793-u-boot.dtsi | 2 +- arch/arm/dts/r8a7794-u-boot.dtsi | 2 +- arch/arm/dts/r8a77951-u-boot.dtsi | 2 +- arch/arm/dts/r8a77960-u-boot.dtsi | 2 +- arch/arm/dts/r8a77965-u-boot.dtsi | 2 +- arch/arm/dts/r8a77970-u-boot.dtsi | 2 +- arch/arm/dts/r8a77980-u-boot.dtsi | 2 +- arch/arm/dts/r8a77990-u-boot.dtsi | 2 +- arch/arm/dts/r8a77995-u-boot.dtsi | 2 +- arch/arm/dts/r8a779x-u-boot.dtsi | 2 +- 13 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/dts/r8a7790-u-boot.dtsi b/arch/arm/dts/r8a7790-u-boot.dtsi index 45e2fa6f9f0..2a7d76bd7b1 100644 --- a/arch/arm/dts/r8a7790-u-boot.dtsi +++ b/arch/arm/dts/r8a7790-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A7790 SoC + * Device Tree Source extras for U-Boot on R-Car R8A7790 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a7791-u-boot.dtsi b/arch/arm/dts/r8a7791-u-boot.dtsi index 7143ffc1658..bb0e2fd106c 100644 --- a/arch/arm/dts/r8a7791-u-boot.dtsi +++ b/arch/arm/dts/r8a7791-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A7791 SoC + * Device Tree Source extras for U-Boot on R-Car R8A7791 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a7792-u-boot.dtsi b/arch/arm/dts/r8a7792-u-boot.dtsi index 214cfde1f89..ebbdcb7efd5 100644 --- a/arch/arm/dts/r8a7792-u-boot.dtsi +++ b/arch/arm/dts/r8a7792-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A7792 SoC + * Device Tree Source extras for U-Boot on R-Car R8A7792 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a7793-u-boot.dtsi b/arch/arm/dts/r8a7793-u-boot.dtsi index fb947462c54..08f2248e1f3 100644 --- a/arch/arm/dts/r8a7793-u-boot.dtsi +++ b/arch/arm/dts/r8a7793-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A7793 SoC + * Device Tree Source extras for U-Boot on R-Car R8A7793 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a7794-u-boot.dtsi b/arch/arm/dts/r8a7794-u-boot.dtsi index 53b54c88917..303afaeb4ce 100644 --- a/arch/arm/dts/r8a7794-u-boot.dtsi +++ b/arch/arm/dts/r8a7794-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A7794 SoC + * Device Tree Source extras for U-Boot on R-Car R8A7794 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a77951-u-boot.dtsi b/arch/arm/dts/r8a77951-u-boot.dtsi index 4cbec591479..c16c5116592 100644 --- a/arch/arm/dts/r8a77951-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A7795 SoC + * Device Tree Source extras for U-Boot on R-Car R8A7795 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a77960-u-boot.dtsi b/arch/arm/dts/r8a77960-u-boot.dtsi index 15a91474324..2245be2aa76 100644 --- a/arch/arm/dts/r8a77960-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A7796 SoC + * Device Tree Source extras for U-Boot on R-Car R8A7796 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi index 54107d1ae35..f39acc237d3 100644 --- a/arch/arm/dts/r8a77965-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A77965 SoC + * Device Tree Source extras for U-Boot on R-Car R8A77965 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a77970-u-boot.dtsi b/arch/arm/dts/r8a77970-u-boot.dtsi index d252c2e8e6c..7900c641ba1 100644 --- a/arch/arm/dts/r8a77970-u-boot.dtsi +++ b/arch/arm/dts/r8a77970-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A77970 SoC + * Device Tree Source extras for U-Boot on R-Car R8A77970 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a77980-u-boot.dtsi b/arch/arm/dts/r8a77980-u-boot.dtsi index 9f7bf499bc0..aa7e058c585 100644 --- a/arch/arm/dts/r8a77980-u-boot.dtsi +++ b/arch/arm/dts/r8a77980-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A77980 SoC + * Device Tree Source extras for U-Boot on R-Car R8A77980 SoC * * Copyright (C) 2019 Marek Vasut */ diff --git a/arch/arm/dts/r8a77990-u-boot.dtsi b/arch/arm/dts/r8a77990-u-boot.dtsi index 50bbbe18647..b701f68db81 100644 --- a/arch/arm/dts/r8a77990-u-boot.dtsi +++ b/arch/arm/dts/r8a77990-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A77990 SoC + * Device Tree Source extras for U-Boot on R-Car R8A77990 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a77995-u-boot.dtsi b/arch/arm/dts/r8a77995-u-boot.dtsi index 347b59ac42c..f4bafb6d088 100644 --- a/arch/arm/dts/r8a77995-u-boot.dtsi +++ b/arch/arm/dts/r8a77995-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A77995 SoC + * Device Tree Source extras for U-Boot on R-Car R8A77995 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a779x-u-boot.dtsi b/arch/arm/dts/r8a779x-u-boot.dtsi index 001ac59adb9..d1441f1f9df 100644 --- a/arch/arm/dts/r8a779x-u-boot.dtsi +++ b/arch/arm/dts/r8a779x-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar Gen3 + * Device Tree Source extras for U-Boot on R-Car Gen3 * * Copyright (C) 2018 Marek Vasut */ From 279d916b986f100831f7680cf00f48ada7e4d019 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 11 Dec 2024 08:30:26 +0100 Subject: [PATCH 03/70] ARM: renesas: Fix R-Car spelling The correct spelling is R-Car, including the dash, update the usage. Kconfig strings and comment changes only, no functional change. Signed-off-by: Marek Vasut --- arch/arm/mach-renesas/Kconfig.32 | 4 ++-- arch/arm/mach-renesas/include/mach/boot0.h | 2 +- arch/arm/mach-renesas/memmap-gen3.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-renesas/Kconfig.32 b/arch/arm/mach-renesas/Kconfig.32 index 693a5abba0d..bbc61ccf480 100644 --- a/arch/arm/mach-renesas/Kconfig.32 +++ b/arch/arm/mach-renesas/Kconfig.32 @@ -1,11 +1,11 @@ if RCAR_32 config ARCH_RENESAS_BOARD_STRING - string "Renesas RCar Gen2 board name" + string "Renesas R-Car Gen2 board name" default "Board" config RCAR_GEN2 - bool "Renesas RCar Gen2" + bool "Renesas R-Car Gen2" select PHY select PHY_RCAR_GEN2 select TMU_TIMER diff --git a/arch/arm/mach-renesas/include/mach/boot0.h b/arch/arm/mach-renesas/include/mach/boot0.h index fe88a2e0373..2128eccd8a4 100644 --- a/arch/arm/mach-renesas/include/mach/boot0.h +++ b/arch/arm/mach-renesas/include/mach/boot0.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Specialty padding for the RCar Gen2 SPL JTAG loading + * Specialty padding for the R-Car Gen2 SPL JTAG loading */ #ifndef __BOOT0_H diff --git a/arch/arm/mach-renesas/memmap-gen3.c b/arch/arm/mach-renesas/memmap-gen3.c index c50700df078..d24419f5daa 100644 --- a/arch/arm/mach-renesas/memmap-gen3.c +++ b/arch/arm/mach-renesas/memmap-gen3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 memory map tables + * Renesas R-Car Gen3 memory map tables * * Copyright (C) 2017 Marek Vasut */ From d774197bb0436080b1e036ec0e9fefa4dbbd3e27 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 11 Dec 2024 08:30:27 +0100 Subject: [PATCH 04/70] clk: renesas: Fix R-Car spelling The correct spelling is R-Car, including the dash, update the usage. Kconfig strings and comment changes only, no functional change. Signed-off-by: Marek Vasut --- drivers/clk/renesas/Kconfig | 12 ++++++------ drivers/clk/renesas/clk-rcar-gen2.c | 2 +- drivers/clk/renesas/clk-rcar-gen3.c | 2 +- drivers/clk/renesas/rcar-cpg-lib.c | 2 +- drivers/clk/renesas/renesas-cpg-mssr.c | 2 +- drivers/clk/renesas/renesas-cpg-mssr.h | 2 +- 6 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index a093027eb0e..12966d02a22 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -5,20 +5,20 @@ config CLK_RENESAS Enable support for clock present on Renesas SoCs. config CLK_RCAR - bool "Renesas RCar clock driver support" + bool "Renesas R-Car clock driver support" help - Enable common code for clocks on Renesas RCar SoCs. + Enable common code for clocks on Renesas R-Car SoCs. config CLK_RCAR_CPG_LIB bool "CPG/MSSR library functions" config CLK_RCAR_GEN2 - bool "Renesas RCar Gen2 clock driver" + bool "Renesas R-Car Gen2 clock driver" def_bool y if RCAR_32 depends on CLK_RENESAS select CLK_RCAR help - Enable this to support the clocks on Renesas RCar Gen2 SoC. + Enable this to support the clocks on Renesas R-Car Gen2 SoC. config CLK_R8A7790 bool "Renesas R8A7790 clock driver" @@ -51,14 +51,14 @@ config CLK_R8A7794 Enable this to support the clocks on Renesas R8A7794 SoC. config CLK_RCAR_GEN3 - bool "Renesas RCar Gen3 and Gen4 clock driver" + bool "Renesas R-Car Gen3 and Gen4 clock driver" def_bool y if RCAR_64 depends on CLK_RENESAS select CLK_RCAR select CLK_RCAR_CPG_LIB select DM_RESET help - Enable this to support the clocks on Renesas RCar Gen3 and Gen4 SoCs. + Enable this to support the clocks on Renesas R-Car Gen3 and Gen4 SoCs. config CLK_R8A774A1 bool "Renesas R8A774A1 clock driver" diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c index 89f2d966746..9b6fce4675c 100644 --- a/drivers/clk/renesas/clk-rcar-gen2.c +++ b/drivers/clk/renesas/clk-rcar-gen2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen2 CPG MSSR driver + * Renesas R-Car Gen2 CPG MSSR driver * * Copyright (C) 2017 Marek Vasut * diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index aa38c0f7dd0..375cc4a4930 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2017 Marek Vasut * diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c index 8862fbc7579..ea33bfd3239 100644 --- a/drivers/clk/renesas/rcar-cpg-lib.c +++ b/drivers/clk/renesas/rcar-cpg-lib.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2017 Marek Vasut * diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 35bad7f5f73..39ff4541c1e 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2018 Marek Vasut * diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 71e409f3eb0..d5db14baf06 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2017-2018 Marek Vasut * From 4a9c8946b8c1fec28ca696512f639723aa3bec05 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 11 Dec 2024 08:30:28 +0100 Subject: [PATCH 05/70] gpio: renesas: Fix R-Car spelling The correct spelling is R-Car, including the dash, update the usage. Kconfig strings and comment changes only, no functional change. Signed-off-by: Marek Vasut --- drivers/gpio/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 92a8597420a..f4a453e1cdd 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -358,10 +358,10 @@ config PCF8575_GPIO chips are from NXP and TI. config RCAR_GPIO - bool "Renesas RCar GPIO driver" + bool "Renesas R-Car GPIO driver" depends on DM_GPIO && ARCH_RENESAS help - This driver supports the GPIO banks on Renesas RCar SoCs. + This driver supports the GPIO banks on Renesas R-Car SoCs. config RZA1_GPIO bool "Renesas RZ/A1 GPIO driver" From 1fea57811ff682be4ddae8fbdb38363dcdec1cd8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 11 Dec 2024 08:30:29 +0100 Subject: [PATCH 06/70] i2c: renesas: Fix R-Car spelling The correct spelling is R-Car, including the dash, update the usage. Kconfig strings and comment changes only, no functional change. Signed-off-by: Marek Vasut --- drivers/i2c/Kconfig | 8 ++++---- drivers/i2c/rcar_iic.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 52067fa7c1f..cdae6825736 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -504,16 +504,16 @@ config SYS_I2C_OMAP24XX Add support for the OMAP2+ I2C driver. config SYS_I2C_RCAR_I2C - bool "Renesas RCar I2C driver" + bool "Renesas R-Car I2C driver" depends on (RCAR_GEN2 || RCAR_64) && DM_I2C help - Support for Renesas RCar I2C controller. + Support for Renesas R-Car I2C controller. config SYS_I2C_RCAR_IIC - bool "Renesas RCar Gen3 IIC driver" + bool "Renesas R-Car Gen3 IIC driver" depends on (RCAR_GEN2 || RCAR_GEN3) && DM_I2C help - Support for Renesas RCar Gen3 IIC controller. + Support for Renesas R-Car Gen3 IIC controller. config SYS_I2C_ROCKCHIP bool "Rockchip I2C driver" diff --git a/drivers/i2c/rcar_iic.c b/drivers/i2c/rcar_iic.c index 2aa0f5fbfae..e019d06be41 100644 --- a/drivers/i2c/rcar_iic.c +++ b/drivers/i2c/rcar_iic.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar IIC driver + * Renesas R-Car IIC driver * * Copyright (C) 2017 Marek Vasut * From 190c6d05e8987246bd2d77afc8cdfd3961257a01 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 11 Dec 2024 08:30:30 +0100 Subject: [PATCH 07/70] mmc: renesas: Fix R-Car spelling The correct spelling is R-Car, including the dash, update the usage. Comment changes only, no functional change. Reviewed-by: Jaehoon Chung Signed-off-by: Marek Vasut --- drivers/mmc/renesas-sdhi.c | 2 +- drivers/mmc/tmio-common.h | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 92afa6adcda..556f07eaf8f 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -571,7 +571,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) int i, ret = 0, sret; u32 caps, reg; - /* Only supported on Renesas RCar */ + /* Only supported on Renesas R-Car */ if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS)) return -EINVAL; diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h index f489fb70766..657aba75148 100644 --- a/drivers/mmc/tmio-common.h +++ b/drivers/mmc/tmio-common.h @@ -64,7 +64,7 @@ #define TMIO_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ #define TMIO_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ #define TMIO_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */ -#define TMIO_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */ +#define TMIO_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (R-Car ver.) */ #define TMIO_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ #define TMIO_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ #define TMIO_SD_SIZE 0x04c /* block size */ @@ -90,7 +90,7 @@ #define TMIO_SD_VOLT_180 (2 << 0)/* 1.8V signal */ #define TMIO_SD_DMA_MODE 0x410 #define TMIO_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */ -#define TMIO_SD_DMA_MODE_BUS_WIDTH (BIT(5) | BIT(4)) /* RCar, 64bit */ +#define TMIO_SD_DMA_MODE_BUS_WIDTH (BIT(5) | BIT(4)) /* R-Car, 64bit */ #define TMIO_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */ #define TMIO_SD_DMA_CTL 0x414 #define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */ @@ -128,9 +128,9 @@ struct tmio_sd_priv { #define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ #define TMIO_SD_CAP_64BIT BIT(3) /* Controller is 64bit */ #define TMIO_SD_CAP_16BIT BIT(4) /* Controller is 16bit */ -#define TMIO_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas RCar version of IP */ -#define TMIO_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas RCar version of IP */ -#define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas RCar UHS/SDR modes */ +#define TMIO_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas R-Car version of IP */ +#define TMIO_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas R-Car version of IP */ +#define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas R-Car UHS/SDR modes */ #define TMIO_SD_CAP_RCAR \ (TMIO_SD_CAP_RCAR_GEN2 | TMIO_SD_CAP_RCAR_GEN3) struct udevice *vqmmc_dev; From 5f97f5c7ed8fc4527759c14331cce01ab3287a5c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 11 Dec 2024 08:30:31 +0100 Subject: [PATCH 08/70] mtd: renesas: Fix R-Car spelling The correct spelling is R-Car, including the dash, update the usage. Kconfig strings and comment changes only, no functional change. Signed-off-by: Marek Vasut --- drivers/mtd/Kconfig | 4 ++-- drivers/mtd/renesas_rpc_hf.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 3764e2567c1..e7ce8b9577b 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -194,11 +194,11 @@ config ALTERA_QSPI "Embedded Peripherals IP User Guide" of Altera. config RENESAS_RPC_HF - bool "Renesas RCar Gen3 RPC HyperFlash driver" + bool "Renesas R-Car Gen3 RPC HyperFlash driver" depends on RCAR_GEN3 && DM_MTD help This enables access to HyperFlash memory through the Renesas - RCar Gen3 RPC controller. + R-Car Gen3 RPC controller. config HBMC_AM654 bool "HyperBus controller driver for AM65x SoC" diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c index 03545822b07..50a6191d9c2 100644 --- a/drivers/mtd/renesas_rpc_hf.c +++ b/drivers/mtd/renesas_rpc_hf.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen3 RPC HyperFlash driver + * Renesas R-Car Gen3 RPC HyperFlash driver * * Copyright (C) 2016 Renesas Electronics Corporation * Copyright (C) 2016 Cogent Embedded, Inc. From 7246f98d29aba5d6caff230b427e39e219165fce Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 11 Dec 2024 08:30:32 +0100 Subject: [PATCH 09/70] pci: renesas: Fix R-Car spelling The correct spelling is R-Car, including the dash, update the usage. Kconfig strings and comment changes only, no functional change. Signed-off-by: Marek Vasut --- drivers/pci/Kconfig | 8 ++++---- drivers/pci/pci-rcar-gen2.c | 2 +- drivers/pci/pci-rcar-gen3.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 876a5fa57ee..41901433e8c 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -189,19 +189,19 @@ config PCI_MSC01 depends on TARGET_MALTA config PCI_RCAR_GEN2 - bool "Renesas RCar Gen2 PCIe driver" + bool "Renesas R-Car Gen2 PCIe driver" depends on RCAR_32 help Say Y here if you want to enable PCIe controller support on - Renesas RCar Gen2 SoCs. The PCIe controller on RCar Gen2 is + Renesas R-Car Gen2 SoCs. The PCIe controller on R-Car Gen2 is also used to access EHCI USB controller on the SoC. config PCI_RCAR_GEN3 - bool "Renesas RCar Gen3 PCIe driver" + bool "Renesas R-Car Gen3 PCIe driver" depends on RCAR_GEN3 help Say Y here if you want to enable PCIe controller support on - Renesas RCar Gen3 SoCs. + Renesas R-Car Gen3 SoCs. config PCI_SANDBOX bool "Sandbox PCI support" diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c index 12c31e74087..08d5c4fbb8b 100644 --- a/drivers/pci/pci-rcar-gen2.c +++ b/drivers/pci/pci-rcar-gen2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen2 PCIEC driver + * Renesas R-Car Gen2 PCIEC driver * * Copyright (C) 2018 Marek Vasut */ diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 76878246f1e..d4b4037ce19 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen3 PCIEC driver + * Renesas R-Car Gen3 PCIEC driver * * Copyright (C) 2018-2019 Marek Vasut * From 1bf8f02f1458059efbf590a352937e86ef684344 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 11 Dec 2024 08:30:33 +0100 Subject: [PATCH 10/70] phy: renesas: Fix R-Car spelling The correct spelling is R-Car, including the dash, update the usage. Comment changes only, no functional change. Signed-off-by: Marek Vasut --- drivers/phy/phy-rcar-gen2.c | 2 +- drivers/phy/phy-rcar-gen3.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/phy-rcar-gen2.c b/drivers/phy/phy-rcar-gen2.c index f9428c7ad12..be736629d51 100644 --- a/drivers/phy/phy-rcar-gen2.c +++ b/drivers/phy/phy-rcar-gen2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen2 USB PHY driver + * Renesas R-Car Gen2 USB PHY driver * * Copyright (C) 2018 Marek Vasut */ diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c index b278f995f37..8c004eaf4c6 100644 --- a/drivers/phy/phy-rcar-gen3.c +++ b/drivers/phy/phy-rcar-gen3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen3 USB PHY driver + * Renesas R-Car Gen3 USB PHY driver * * Copyright (C) 2018 Marek Vasut */ From 4380b31e406bdbd49371a003cac92432486a7c2e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 11 Dec 2024 08:30:34 +0100 Subject: [PATCH 11/70] pinctrl: renesas: Fix R-Car spelling The correct spelling is R-Car, including the dash, update the usage. Kconfig strings and comment changes only, no functional change. Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/Kconfig | 68 ++++++++++++++++----------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 57e88604aa2..a209193b332 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -12,34 +12,34 @@ config PINCTRL_PFC available multiplex function. config PINCTRL_PFC_R8A7790 - bool "Renesas RCar Gen2 R8A7790 pin control driver" + bool "Renesas R-Car Gen2 R8A7790 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7790 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7790 SoCs. config PINCTRL_PFC_R8A7791 - bool "Renesas RCar Gen2 R8A7791 pin control driver" + bool "Renesas R-Car Gen2 R8A7791 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7791 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7791 SoCs. config PINCTRL_PFC_R8A7792 - bool "Renesas RCar Gen2 R8A7792 pin control driver" + bool "Renesas R-Car Gen2 R8A7792 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7792 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7792 SoCs. config PINCTRL_PFC_R8A7793 - bool "Renesas RCar Gen2 R8A7793 pin control driver" + bool "Renesas R-Car Gen2 R8A7793 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7793 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7793 SoCs. config PINCTRL_PFC_R8A7794 - bool "Renesas RCar Gen2 R8A7794 pin control driver" + bool "Renesas R-Car Gen2 R8A7794 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7794 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7794 SoCs. config PINCTRL_PFC_R8A774A1 bool "Renesas RZ/G2 R8A774A1 pin control driver" @@ -66,76 +66,76 @@ config PINCTRL_PFC_R8A774E1 Support pin multiplexing control on Renesas RZ/G2H R8A774E1 SoCs. config PINCTRL_PFC_R8A77951 - bool "Renesas RCar Gen3 R8A7795 pin control driver" + bool "Renesas R-Car Gen3 R8A7795 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A7795 SoCs. config PINCTRL_PFC_R8A77960 - bool "Renesas RCar Gen3 R8A77960 pin control driver" + bool "Renesas R-Car Gen3 R8A77960 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77960 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77960 SoCs. config PINCTRL_PFC_R8A77961 - bool "Renesas RCar Gen3 R8A77961 pin control driver" + bool "Renesas R-Car Gen3 R8A77961 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77961 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77961 SoCs. config PINCTRL_PFC_R8A77965 - bool "Renesas RCar Gen3 R8A77965 pin control driver" + bool "Renesas R-Car Gen3 R8A77965 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77965 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77965 SoCs. config PINCTRL_PFC_R8A77970 - bool "Renesas RCar Gen3 R8A77970 pin control driver" + bool "Renesas R-Car Gen3 R8A77970 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77970 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77970 SoCs. config PINCTRL_PFC_R8A77980 - bool "Renesas RCar Gen3 R8A77980 pin control driver" + bool "Renesas R-Car Gen3 R8A77980 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77980 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77980 SoCs. config PINCTRL_PFC_R8A77990 - bool "Renesas RCar Gen3 R8A77990 pin control driver" + bool "Renesas R-Car Gen3 R8A77990 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77990 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77990 SoCs. config PINCTRL_PFC_R8A77995 - bool "Renesas RCar Gen3 R8A77995 pin control driver" + bool "Renesas R-Car Gen3 R8A77995 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77995 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77995 SoCs. config PINCTRL_PFC_R8A779A0 - bool "Renesas RCar Gen3 R8A779A0 pin control driver" + bool "Renesas R-Car Gen3 R8A779A0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A779A0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A779A0 SoCs. config PINCTRL_PFC_R8A779F0 - bool "Renesas RCar Gen4 R8A779F0 pin control driver" + bool "Renesas R-Car Gen4 R8A779F0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen4 R8A779F0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen4 R8A779F0 SoCs. config PINCTRL_PFC_R8A779G0 - bool "Renesas RCar Gen4 R8A779G0 pin control driver" + bool "Renesas R-Car Gen4 R8A779G0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen4 R8A779G0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen4 R8A779G0 SoCs. config PINCTRL_PFC_R8A779H0 - bool "Renesas RCar Gen4 R8A779H0 pin control driver" + bool "Renesas R-Car Gen4 R8A779H0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen4 R8A779H0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen4 R8A779H0 SoCs. config PINCTRL_RZA1 bool "Renesas RZ/A1 R7S72100 pin control driver" From b1c2886cf2ac34d76795500018fba79adef91b1d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 11 Dec 2024 08:30:35 +0100 Subject: [PATCH 12/70] serial: renesas: Fix R-Car spelling The correct spelling is R-Car, including the dash, update the usage. Kconfig strings and comment changes only, no functional change. Signed-off-by: Marek Vasut --- drivers/serial/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 8b27ad9a77e..c4f4a8d78df 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -920,7 +920,7 @@ config SCIF_CONSOLE depends on SH || ARCH_RENESAS help Select this to enable Renesas SCIF UART. To operate serial ports - on systems with RCar or SH SoCs, say Y to this option. If unsure, + on systems with R-Car or SH SoCs, say Y to this option. If unsure, say N. choice From 14655e62cf1a1fa6ce279fdd055fbf8fb99731d2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 11 Dec 2024 08:30:36 +0100 Subject: [PATCH 13/70] spi: renesas: Fix R-Car spelling The correct spelling is R-Car, including the dash, update the usage. Kconfig strings and comment changes only, no functional change. Signed-off-by: Marek Vasut --- drivers/spi/Kconfig | 2 +- drivers/spi/renesas_rpc_spi.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index fd5cb3694f6..96ea033082b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -420,7 +420,7 @@ config RENESAS_RPC_SPI imply SPI_FLASH_SFDP_SUPPORT help Enable the Renesas RPC SPI driver, used to access SPI NOR flash - on Renesas RCar Gen3 SoCs. This uses driver model and requires a + on Renesas R-Car Gen3 SoCs. This uses driver model and requires a device tree binding to operate. config ROCKCHIP_SFC diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index f1e6f9f4e01..7103d786c7e 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 RPC QSPI driver + * Renesas R-Car Gen3 RPC QSPI driver * * Copyright (C) 2018 Marek Vasut */ From 802b08805c1775c576c7f09b52169e462a728592 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 11 Dec 2024 08:30:37 +0100 Subject: [PATCH 14/70] usb: renesas: Fix R-Car spelling The correct spelling is R-Car, including the dash, update the usage. Kconfig strings and comment changes only, no functional change. Signed-off-by: Marek Vasut --- drivers/usb/gadget/Kconfig | 4 ++-- drivers/usb/host/Kconfig | 4 ++-- drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h | 2 +- drivers/usb/host/xhci-rcar.c | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 010084ef7f3..c815764c2bc 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -115,10 +115,10 @@ config USB_GADGET_DWC2_OTG USB_GADGET to be enabled. config USB_RENESAS_USBHS - bool "Renesas RCar USB2.0 HS controller (gadget mode)" + bool "Renesas R-Car USB2.0 HS controller (gadget mode)" select USB_GADGET_DUALSPEED help - The Renesas Rcar USB 2.0 high-speed gadget controller + The Renesas R-Car USB 2.0 high-speed gadget controller integrated into Salvator and Kingfisher boards. Select this option if you want the driver to operate in Peripheral mode. This option requires USB_GADGET to be enabled. diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index bb5893d56db..24786a2bc91 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -103,12 +103,12 @@ config USB_XHCI_PCI Enables support for the PCI-based xHCI controller. config USB_XHCI_RCAR - bool "Renesas RCar USB 3.0 support" + bool "Renesas R-Car USB 3.0 support" default y depends on ARCH_RENESAS help Choose this option to add support for USB 3.0 driver on Renesas - RCar Gen3 SoCs. + R-Car Gen3 SoCs. config USB_XHCI_STI bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller" diff --git a/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h b/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h index 8db88f0dcfa..7c909b4697a 100644 --- a/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h +++ b/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h @@ -1,5 +1,5 @@ /* - * Renesas RCar xHCI controller firmware version 3 + * Renesas R-Car xHCI controller firmware version 3 * * Copyright (c) 2014, Renesas Electronics Corporation * All rights reserved. diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c index 38c5928faed..b72807053c4 100644 --- a/drivers/usb/host/xhci-rcar.c +++ b/drivers/usb/host/xhci-rcar.c @@ -2,7 +2,7 @@ /* * Copyright (C) 2017 Marek Vasut * - * Renesas RCar USB HOST xHCI Controller + * Renesas R-Car USB HOST xHCI Controller */ #include From 28a620d2815ca65f1ef884236d026409bf15bbbb Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 11 Oct 2024 18:09:11 +0100 Subject: [PATCH 15/70] board: rpi: Pass CMA through from firmware DT For a lot of usecases, such as display, camera, media the Raspberry Pi needs a lot more CMA than distros configure as default so we should pass this parameter through so things work as expected. Fix a spelling mistake while we're at it. Signed-off-by: Peter Robinson Reviewed-by: Simon Glass Acked-by: Matthias Brugger --- board/raspberrypi/rpi/rpi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 9122f33d88d..5b6df53bbf9 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -545,12 +545,15 @@ void update_fdt_from_fw(void *fdt, void *fw_fdt) if (fdt == fw_fdt) return; - /* The firmware provides a more precie model; so copy that */ + /* The firmware provides a more precise model; so copy that */ copy_property(fdt, fw_fdt, "/", "model"); /* memory reserve as suggested by the firmware */ copy_property(fdt, fw_fdt, "/", "memreserve"); + /* copy the CMA memory setting from the firmware DT to linux */ + copy_property(fdt, fw_fdt, "/reserved-memory/linux,cma", "size"); + /* Adjust dma-ranges for the SD card and PCI bus as they can depend on * the SoC revision */ From 8b81010a2fe385524b58bea9116f1b6954c3d2bd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 9 Dec 2024 12:11:50 +0100 Subject: [PATCH 16/70] video: zynqmp: Add support for reset In Kria SOM configuration DP is under reset and access to DP is causing hang that's why call reset at probe to avoid this situation. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/0504474a91a9839828aecd37f8855fd154cdf2e1.1733742708.git.michal.simek@amd.com --- drivers/video/zynqmp/zynqmp_dpsub.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c index 76abfeac443..52af23c3c83 100644 --- a/drivers/video/zynqmp/zynqmp_dpsub.c +++ b/drivers/video/zynqmp/zynqmp_dpsub.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -2093,10 +2094,15 @@ static int zynqmp_dpsub_probe(struct udevice *dev) { struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct zynqmp_dpsub_priv *priv = dev_get_priv(dev); + struct reset_ctl_bulk resets; struct clk clk; int ret; int mode = RGBA8888; + ret = reset_get_bulk(dev, &resets); + if (!ret) + reset_deassert_bulk(&resets); + ret = clk_get_by_name(dev, "dp_apb_clk", &clk); if (ret < 0) { dev_err(dev, "failed to get clock\n"); From 6a5fc32fd20b5e5367fda9a75f0e8de1a4b76649 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Fri, 13 Sep 2024 12:53:15 +0300 Subject: [PATCH 17/70] board: rpi: Enable capsule updates Since RPI works well using EFI and has no size limitations with regards to U-Boot, add the needed structures to support capsule updates. While at it update the most commonly used defconfigs and include capsule support and U-Boot commands needed by EFI Tested-by: Sughosh Ganu Signed-off-by: Ilias Apalodimas --- board/raspberrypi/rpi/rpi.c | 13 +++++++++++++ configs/rpi_3_b_plus_defconfig | 8 ++++++++ configs/rpi_3_defconfig | 8 ++++++++ configs/rpi_4_defconfig | 5 +++++ configs/rpi_arm64_defconfig | 8 ++++++++ 5 files changed, 42 insertions(+) diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 5b6df53bbf9..18be244aa79 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -68,6 +68,19 @@ struct msg_get_clock_rate { u32 end_tag; }; +struct efi_fw_image fw_images[] = { + { + .fw_name = u"RPI_UBOOT", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=u-boot.bin fat 0 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + #ifdef CONFIG_ARM64 #define DTB_DIR "broadcom/" #else diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index 3c8f8fc1bb7..a6a8431c8ff 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -19,14 +19,19 @@ CONFIG_SYS_PBSIZE=1049 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y +CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000 CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y @@ -49,3 +54,6 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y +# CONFIG_HEXDUMP is not set +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index 9853c448809..358096f3d1c 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -19,14 +19,19 @@ CONFIG_SYS_PBSIZE=1049 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y +CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000 CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y @@ -49,3 +54,6 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y +# CONFIG_HEXDUMP is not set +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index f5fb322aa8f..17b6688e75c 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -20,11 +20,13 @@ CONFIG_SYS_PBSIZE=1049 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -65,3 +67,6 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y +# CONFIG_HEXDUMP is not set +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index 02f942cf344..a8723ea24e1 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -18,15 +18,20 @@ CONFIG_SYS_PBSIZE=1049 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y CONFIG_DM_DMA=y +CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000 CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y @@ -56,3 +61,6 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y +# CONFIG_HEXDUMP is not set +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y From e371dfef21badd708d94586a11b5437895655b35 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 3 Dec 2024 22:40:29 +0200 Subject: [PATCH 18/70] configs: am62x_evm_*: Fix USB DFU configuration CONFIG_USB_XHCI_DWC3 is not required for AM62x as the XHCI driver is registered through the dwc3-generic driver. CONFIG_USB_XHCI_DWC3 causes problems by hijacking the USB controller even if it is not set for Host mode in device tree. 'dm tree' output after 'usb start' is fixed from simple_bus 5 [ + ] dwc3-am62 | |-- dwc3-usb@f900000 usb_gadget 0 [ ] dwc3-generic-periphe | | |-- usb@31000000 usb 0 [ + ] xhci-dwc3 | | `-- usb@31000000 usb_hub 0 [ + ] usb_hub | | `-- usb_hub simple_bus 6 [ + ] dwc3-am62 | |-- dwc3-usb@f910000 usb 1 [ + ] dwc3-generic-host | | |-- usb@31100000 usb_hub 1 [ + ] usb_hub | | | `-- usb_hub usb 1 [ + ] xhci-dwc3 | | `-- usb@31100000 usb_hub 2 [ + ] usb_hub | | `-- usb_hub [notice that 'xhci-dwc3' and 'usb_hub' drivers are probed for both USB instances although the first instance is supposed to be 'peripheral' only] to simple_bus 5 [ ] dwc3-am62 | |-- dwc3-usb@f900000 usb_gadget 0 [ ] dwc3-generic-periphe | | `-- usb@31000000 simple_bus 6 [ + ] dwc3-am62 | |-- dwc3-usb@f910000 usb 1 [ + ] dwc3-generic-host | | `-- usb@31100000 usb_hub 0 [ + ] usb_hub | | `-- usb_hub Fixes: dfc2dff5a844 ("configs: am62x_evm_*: Enable USB and DFU support") Signed-off-by: Roger Quadros Reviewed-by: Siddharth Vadapalli --- configs/am62x_a53_usbdfu.config | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/am62x_a53_usbdfu.config b/configs/am62x_a53_usbdfu.config index 3a19cf23287..0d3c6df1e73 100644 --- a/configs/am62x_a53_usbdfu.config +++ b/configs/am62x_a53_usbdfu.config @@ -16,7 +16,6 @@ CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_GENERIC=y From 8b8b35a4f5edc8c3579ff82500b32655f94ec4c8 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Tue, 10 Dec 2024 20:17:01 -0600 Subject: [PATCH 19/70] lmb: Return -EEXIST in lmb_add_region_flags() if region already added An attempt to add the already added LMB region using lmb_add_region_flags() ends up in lmb_addrs_overlap() check, which eventually leads to either returning 0 if 'flags' is LMB_NONE, or -1 otherwise. It makes it impossible for the user of this function to catch the case when the region is already added and differentiate it from regular errors. That in turn may lead to incorrect error handling in the caller code, like reporting misleading errors or interrupting the normal code path where it could be treated as the normal case. An example is boot_fdt_reserve_region() function, which might be called twice (e.g. during board startup in initr_lmb(), and then during 'booti' command booting the OS), thus trying to reserve exactly the same memory regions described in the device tree twice, which produces an error message on second call. Return -EEXIST error code in case when the added region exists and it's not LMB_NONE; for LMB_NONE return 0, to conform to unit tests (specifically test_alloc_addr() in test/lib/lmb.c) and the preferred behavior described in commit 1d9aa4a283da ("lmb: Fix the allocation of overlapping memory areas with !LMB_NONE"). The change of lmb_add_region_flags() return values is described in the table below: Return case Pre-1d9 1d9 New ----------------------------------------------------------- Added successfully 0 0 0 Failed to add -1 -1 -1 Already added, flags == LMB_NONE 0 0 0 Already added, flags != LMB_NONE 0 -1 -EEXIST Rework all affected functions and their documentation. Also fix the corresponding unit test which checks reserving the same region with the same flags to account for the changed return value. No functional change is intended (by this patch itself). Fixes: 1d9aa4a283da ("lmb: Fix the allocation of overlapping memory areas with !LMB_NONE") Signed-off-by: Sam Protsenko Reviewed-by: Ilias Apalodimas Tested-by: Michal Simek --- lib/lmb.c | 26 +++++++++++++------------- test/lib/lmb.c | 2 +- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/lib/lmb.c b/lib/lmb.c index b03237bc06c..a695edf70df 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -183,8 +183,10 @@ static long lmb_resize_regions(struct alist *lmb_rgn_lst, * the function might resize an already existing region or coalesce two * adjacent regions. * - * - * Returns: 0 if the region addition successful, -1 on failure + * Return: + * * %0 - Added successfully, or it's already added (only if LMB_NONE) + * * %-EEXIST - The region is already added, and flags != LMB_NONE + * * %-1 - Failure */ static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base, phys_size_t size, enum lmb_flags flags) @@ -217,17 +219,15 @@ static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base, coalesced++; break; } else if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) { - if (flags == LMB_NONE) { - ret = lmb_resize_regions(lmb_rgn_lst, i, base, - size); - if (ret < 0) - return -1; + if (flags != LMB_NONE) + return -EEXIST; - coalesced++; - break; - } else { + ret = lmb_resize_regions(lmb_rgn_lst, i, base, size); + if (ret < 0) return -1; - } + + coalesced++; + break; } } @@ -667,7 +667,7 @@ long lmb_add(phys_addr_t base, phys_size_t size) * * Free up a region of memory. * - * Return: 0 if successful, -1 on failure + * Return: 0 if successful, negative error code on failure */ long lmb_free_flags(phys_addr_t base, phys_size_t size, uint flags) @@ -818,7 +818,7 @@ static phys_addr_t _lmb_alloc_addr(phys_addr_t base, phys_size_t size, lmb_memory[rgn].size, base + size - 1, 1)) { /* ok, reserve the memory */ - if (lmb_reserve_flags(base, size, flags) >= 0) + if (!lmb_reserve_flags(base, size, flags)) return base; } } diff --git a/test/lib/lmb.c b/test/lib/lmb.c index 0bd29e2a4fe..48c3c966f8f 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -754,7 +754,7 @@ static int lib_test_lmb_flags(struct unit_test_state *uts) /* reserve again, same flag */ ret = lmb_reserve_flags(0x40010000, 0x10000, LMB_NOMAP); - ut_asserteq(ret, -1L); + ut_asserteq(ret, -EEXIST); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000, 0, 0, 0, 0); From 5a6aa7d59133ab991f718a5bbd83cd2607782fec Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Tue, 10 Dec 2024 20:17:02 -0600 Subject: [PATCH 20/70] boot: fdt: Handle already reserved memory in boot_fdt_reserve_region() The boot_fdt_add_mem_rsv_regions() function can be called twice, e.g. first time during the board init (as a part of LMB init), and then when booting the OS with 'booti' command: lmb_add_region_flags lmb_reserve_flags boot_fdt_reserve_region boot_fdt_add_mem_rsv_regions ^ | +-----------------------+ | (1) | (2) lmb_reserve_common image_setup_linux lmb_init ... initr_lmb do_booti board_init_r 'booti' That consequently leads to the attempt of reserving the same memory areas (described in the 'reserved-memory' dts node) in LMB. The lmb_add_region_flags() returns -EEXIST error code in such cases, but boot_fdt_reserve_region() handles all negative error codes as a failure to reserve fdt memory region, printing corresponding error messages, which are essentially harmless, but misleading. For example, this is the output of 'booti' command on E850-96 board: => booti $loadaddr - $fdtaddr ... ERROR: reserving fdt memory region failed (addr=bab00000 size=5500000 flags=2) ERROR: reserving fdt memory region failed (addr=f0000000 size=200000 flags=4) ... Starting kernel ... The mentioned false positive error messages are observed starting with commit 1d9aa4a283da ("lmb: Fix the allocation of overlapping memory areas with !LMB_NONE"), which removes the check for the already added memory regions in lmb_add_region_flags(), making it return -1 for !LMB_NONE cases. Another commit 827dee587b75 ("fdt: lmb: add reserved regions as no-overwrite") changes flags used for reserving memory in boot_fdt_add_mem_rsv_regions() from LMB_NONE to LMB_NOOVERWRITE. So together with the patch mentioned earlier, it makes lmb_add_region_flags() return -1 when called from boot_fdt_reserve_region(). Since then, the different patch was implemented, returning -EEXIST error code in described cases, which is: lmb: Return -EEXIST in lmb_add_region_flags() if region already added Handle -EEXIST error code as a normal (successful) case in lmb_reserve_flags() and don't print any messages. Fixes: 1d9aa4a283da ("lmb: Fix the allocation of overlapping memory areas with !LMB_NONE") Signed-off-by: Sam Protsenko Reviewed-by: Ilias Apalodimas Tested-by: Michal Simek --- boot/image-fdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 3d5b6f9e2dc..73c43c30684 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -77,7 +77,7 @@ static void boot_fdt_reserve_region(u64 addr, u64 size, enum lmb_flags flags) debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n", (unsigned long long)addr, (unsigned long long)size, flags); - } else { + } else if (ret != -EEXIST) { puts("ERROR: reserving fdt memory region failed "); printf("(addr=%llx size=%llx flags=%x)\n", (unsigned long long)addr, From 781a7c660cee194566d8e21f20c156e40bcea322 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 13 Dec 2024 11:23:17 +0100 Subject: [PATCH 21/70] board: sl28: fix linking with disabled watchdog We don't have a reference to the driver used by uclass_get_device_by_driver() in stop_recovery_watchdog(). Fix it by not calling that function if the watchdog driver isn't enabled. Signed-off-by: Michael Walle Reviewed-by: Heiko Thiery Signed-off-by: Peng Fan --- board/kontron/sl28/sl28.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index adfec8ba237..0baf5c63f18 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -156,7 +156,8 @@ int fsl_board_late_init(void) * If the watchdog isn't enabled at reset (which is a configuration * option) disabling it doesn't hurt either. */ - if (!IS_ENABLED(CONFIG_WATCHDOG_AUTOSTART)) + if (IS_ENABLED(CONFIG_WDT_SL28CPLD) && + !IS_ENABLED(CONFIG_WATCHDOG_AUTOSTART)) stop_recovery_watchdog(); return 0; From 6c849340b7ab5953e061885c4f7152bd93e3ba49 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 13 Dec 2024 11:23:18 +0100 Subject: [PATCH 22/70] board: sl28: increase SPL_SYS_MALLOC_SIZE Increase the malloc size to 2MiB because our FIT image exceeds the 1MiB limit either if BL31 mode is enabled or if another device tree is added to the image. Signed-off-by: Michael Walle Tested-by: Heiko Thiery Signed-off-by: Peng Fan --- configs/kontron_sl28_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 35894a10cbe..eae06b546da 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -54,6 +54,7 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_SYS_MALLOC_SIZE=0x200000 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x900 CONFIG_SPL_MPC8XXX_INIT_DDR=y From ad7ebf1b989baf32e8917695a1611ea051356e35 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 13 Dec 2024 11:23:19 +0100 Subject: [PATCH 23/70] board: sl28: fix network on variant 3 Network is broken on variant 3 boards since commit 61ff13283c3b ("board: sl28: move to OF_UPSTREAM") because it was removing the variant 3 handling. That is because at that time the var3 device tree was not upstream. FWIW variant 3 is actually the same as the base variant, but I've missed that the -u-boot.dtsi is not inlcuded in this case which will set the ethernet alias. Now that the var3 device tree is upstream, just re-add it to the SPL handling again. Fixes: 61ff13283c3b ("board: sl28: move to OF_UPSTREAM") Signed-off-by: Michael Walle Reviewed-by: Heiko Thiery Signed-off-by: Peng Fan --- board/kontron/sl28/spl.c | 3 ++- configs/kontron_sl28_defconfig | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c index 45a4fc65120..6b31f5e3a7c 100644 --- a/board/kontron/sl28/spl.c +++ b/board/kontron/sl28/spl.c @@ -50,9 +50,10 @@ int board_fit_config_name_match(const char *name) return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var1"); case 2: return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var2"); + case 3: + return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var3"); case 4: return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var4"); - case 3: default: return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28"); } diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index eae06b546da..1f684093252 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -78,7 +78,7 @@ CONFIG_CMD_RNG=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y -CONFIG_OF_LIST="freescale/fsl-ls1028a-kontron-sl28 freescale/fsl-ls1028a-kontron-sl28-var1 freescale/fsl-ls1028a-kontron-sl28-var2 freescale/fsl-ls1028a-kontron-sl28-var4" +CONFIG_OF_LIST="freescale/fsl-ls1028a-kontron-sl28 freescale/fsl-ls1028a-kontron-sl28-var1 freescale/fsl-ls1028a-kontron-sl28-var2 freescale/fsl-ls1028a-kontron-sl28-var3 freescale/fsl-ls1028a-kontron-sl28-var4" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y From 079ae2734c4641b148932c1758a2524492d35772 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 13 Dec 2024 11:23:20 +0100 Subject: [PATCH 24/70] doc: board: sl28: fix table Convert the table to a correct reST table syntax. Signed-off-by: Michael Walle Signed-off-by: Peng Fan --- doc/board/kontron/sl28.rst | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/doc/board/kontron/sl28.rst b/doc/board/kontron/sl28.rst index 2cb8ec62be4..5d47ce6c158 100644 --- a/doc/board/kontron/sl28.rst +++ b/doc/board/kontron/sl28.rst @@ -65,12 +65,14 @@ wdt command flags The `wdt start` as well as the `wdt expire` command take a flags argument. The supported bitmask is as follows. -| Bit | Description | -| --- | ----------------------------- | -| 0 | Enable failsafe mode | -| 1 | Lock the control register | -| 2 | Disable board reset | -| 3 | Enable WDT_TIME_OUT# line | +=== ============================== +Bit Description +=== ============================== + 0 Enable failsafe mode + 1 Lock the control register + 2 Disable board reset + 3 Enable WDT_TIME_OUT# line +=== ============================== For example, you can use `wdt expire 1` to issue a reset and boot into the failsafe bootloader. From 56aa021f080096e8a0ac24b31c3ff40662c8b81b Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 13 Dec 2024 11:23:21 +0100 Subject: [PATCH 25/70] board: sl28: fix USB0 Since commit 61ff13283c3b ("board: sl28: move to OF_UPSTREAM") USB0 is broken because the former u-boot soc dtsi was setting dr_mode to "host" but the linux device tree isn't. That is because linux fully supports OTG but u-boot doesn't. Therefore, u-boot only ever enabled host mode and never OTG mode. Add it to our board "-u-boot.dtsi" to fix it. Fixes: 61ff13283c3b ("board: sl28: move to OF_UPSTREAM") Reported-by: Heiko Thiery Signed-off-by: Michael Walle Tested-by: Heiko Thiery Signed-off-by: Peng Fan --- arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index aacf181e2dd..4202d1e5654 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -203,3 +203,7 @@ &sysclk { bootph-all; }; + +&usb0 { + dr_mode = "host"; +}; From 69ec7f35e05780b0a9021ba6f9038e2b534f8d17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=2E=20Neusch=C3=A4fer?= Date: Fri, 29 Nov 2024 20:42:28 +0100 Subject: [PATCH 26/70] clk: mpc83xx: Fix typo in "Coherent System Bus" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cosmetic change. Signed-off-by: J. Neuschäfer --- drivers/clk/mpc83xx_clk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/mpc83xx_clk.h b/drivers/clk/mpc83xx_clk.h index c06a51ecd43..6b74fc5f16b 100644 --- a/drivers/clk/mpc83xx_clk.h +++ b/drivers/clk/mpc83xx_clk.h @@ -321,7 +321,7 @@ static inline u32 get_pci_sync_in(immap_t *im) } /** - * get_csb_clk() - Read the CSB (Coheren System Bus) clock speed + * get_csb_clk() - Read the CSB (Coherent System Bus) clock speed * @im: Pointer to the MPC83xx main register map in question * * Return: The CSB clock speed value as a 32-bit number. From a7dc9f3220d55ebab41712b78221ea7dd5c12571 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=2E=20Neusch=C3=A4fer?= Date: Fri, 29 Nov 2024 20:42:29 +0100 Subject: [PATCH 27/70] doc: sending_patches: Fix spelling of "its" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Although it has historically been different, the current standard spelling of the neutral singular possessive pronoun is "its". Signed-off-by: J. Neuschäfer --- doc/develop/sending_patches.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/develop/sending_patches.rst b/doc/develop/sending_patches.rst index e22b5e3e244..ee6e34089b5 100644 --- a/doc/develop/sending_patches.rst +++ b/doc/develop/sending_patches.rst @@ -377,7 +377,7 @@ The following are a "rule of thumb" as to how the states are used in patchwork today. Not all states are used by all custodians. * New: Patch has been submitted to the list, and none of the maintainers has - changed it's state since. + changed its state since. * Under Review: A custodian is reviewing the patch currently. From 4888d1bd0ea4e1a9976890ba221e9d14433231eb Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 30 Nov 2024 22:18:57 +0100 Subject: [PATCH 28/70] doc: remove redundant Rockchip bindings Most Rockchip device tree related bindings are converted to YAML and available in the U-boot /dts/upstream/Bindings/ directory. Remove all redundant U-boot entries. Signed-off-by: Johan Jonker --- .../clock/rockchip,rk3188-cru.txt | 61 ------- .../clock/rockchip,rk3288-cru.txt | 61 ------- doc/device-tree-bindings/clock/rockchip.txt | 77 --------- .../pinctrl/rockchip,pinctrl.txt | 157 ------------------ .../thermal/rockchip-thermal.txt | 68 -------- doc/device-tree-bindings/usb/dwc2.txt | 4 - .../video/rockchip-lvds.txt | 77 --------- 7 files changed, 505 deletions(-) delete mode 100644 doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt delete mode 100644 doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt delete mode 100644 doc/device-tree-bindings/clock/rockchip.txt delete mode 100644 doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt delete mode 100644 doc/device-tree-bindings/thermal/rockchip-thermal.txt delete mode 100644 doc/device-tree-bindings/video/rockchip-lvds.txt diff --git a/doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt b/doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt deleted file mode 100644 index 0c2bf5eba43..00000000000 --- a/doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3188/RK3066 Clock and Reset Unit - -The RK3188/RK3066 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or - "rockchip,rk3066a-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3188-cru.h and -dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. -Similar macros exist for the reset sources in these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "xin27m" - 27mhz crystal input on rk3066 - optional, - - "ext_hsadc" - external HSADC clock - optional, - - "ext_cif0" - external camera clock - optional, - - "ext_rmii" - external RMII clock - optional, - - "ext_jtag" - externalJTAG clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt b/doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt deleted file mode 100644 index c9fbb76573e..00000000000 --- a/doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3288 Clock and Reset Unit - -The RK3288 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3288-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_hsadc" - external HSADC clock - optional, - - "ext_edp_24m" - external display port clock - optional, - - "ext_vip" - external VIP clock - optional, - - "ext_isp" - external ISP clock - optional, - - "ext_jtag" - external JTAG clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/doc/device-tree-bindings/clock/rockchip.txt b/doc/device-tree-bindings/clock/rockchip.txt deleted file mode 100644 index 22f6769e5d4..00000000000 --- a/doc/device-tree-bindings/clock/rockchip.txt +++ /dev/null @@ -1,77 +0,0 @@ -Device Tree Clock bindings for arch-rockchip - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -== Gate clocks == - -These bindings are deprecated! -Please use the soc specific CRU bindings instead. - -The gate registers form a continuos block which makes the dt node -structure a matter of taste, as either all gates can be put into -one gate clock spanning all registers or they can be divided into -the 10 individual gates containing 16 clocks each. -The code supports both approaches. - -Required properties: -- compatible : "rockchip,rk2928-gate-clk" -- reg : shall be the control register address(es) for the clock. -- #clock-cells : from common clock binding; shall be set to 1 -- clock-output-names : the corresponding gate names that the clock controls -- clocks : should contain the parent clock for each individual gate, - therefore the number of clocks elements should match the number of - clock-output-names - -Example using multiple gate clocks: - - clk_gates0: gate-clk@200000d0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d0 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_core_periph", "gate_cpu_gpll", - "gate_ddrphy", "gate_aclk_cpu", - "gate_hclk_cpu", "gate_pclk_cpu", - "gate_atclk_cpu", "gate_i2s0", - "gate_i2s0_frac", "gate_i2s1", - "gate_i2s1_frac", "gate_i2s2", - "gate_i2s2_frac", "gate_spdif", - "gate_spdif_frac", "gate_testclk"; - - #clock-cells = <1>; - }; - - clk_gates1: gate-clk@200000d4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d4 0x4>; - clocks = <&xin24m>, <&xin24m>, - <&xin24m>, <&dummy>, - <&dummy>, <&xin24m>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_timer0", "gate_timer1", - "gate_timer2", "gate_jtag", - "gate_aclk_lcdc1_src", "gate_otgphy0", - "gate_otgphy1", "gate_ddr_gpll", - "gate_uart0", "gate_frac_uart0", - "gate_uart1", "gate_frac_uart1", - "gate_uart2", "gate_frac_uart2", - "gate_uart3", "gate_frac_uart3"; - - #clock-cells = <1>; - }; diff --git a/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt b/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt deleted file mode 100644 index 388b213249f..00000000000 --- a/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt +++ /dev/null @@ -1,157 +0,0 @@ -* Rockchip Pinmux Controller - -The Rockchip Pinmux Controller, enables the IC -to share one PAD to several functional blocks. The sharing is done by -multiplexing the PAD input/output signals. For each PAD there are several -muxing options with option 0 being the use as a GPIO. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The Rockchip pin configuration node is a node of a group of pins which can be -used for a specific device or function. This node represents both mux and -config of the pins in that group. The 'pins' selects the function mode(also -named pin mode) this pin can work on and the 'config' configures various pad -settings such as pull-up, etc. - -The pins are grouped into up to 5 individual pin banks which need to be -defined as gpio sub-nodes of the pinmux controller. - -Required properties for iomux controller: - - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" - "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" - "rockchip,rk3288-pinctrl" - - rockchip,grf: phandle referencing a syscon providing the - "general register files" - -Optional properties for iomux controller: - - rockchip,pmu: phandle referencing a syscon providing the pmu registers - as some SoCs carry parts of the iomux controller registers there. - Required for at least rk3188 and rk3288. - -Deprecated properties for iomux controller: - - reg: first element is the general register space of the iomux controller - It should be large enough to contain also separate pull registers. - second element is the separate pull register space of the rk3188. - Use rockchip,grf and rockchip,pmu described above instead. - -Required properties for gpio sub nodes: - - compatible: "rockchip,gpio-bank" - - reg: register of the gpio bank (different than the iomux registerset) - - interrupts: base interrupt of the gpio bank in the interrupt controller - - clocks: clock that drives this bank - - gpio-controller: identifies the node as a gpio controller and pin bank. - - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See generic - GPIO binding documentation for description of particular cells. - - interrupt-controller: identifies the controller node as interrupt-parent. - - #interrupt-cells: the value of this property should be 2 and the interrupt - cells should use the standard two-cell scheme described in - bindings/interrupt-controller/interrupts.txt - -Deprecated properties for gpio sub nodes: - - compatible: "rockchip,rk3188-gpio-bank0" - - reg: second element: separate pull register for rk3188 bank0, use - rockchip,pmu described above instead - -Required properties for pin configuration node: - - rockchip,pins: 3 integers array, represents a group of pins mux and config - setting. The format is rockchip,pins = . - The MUX 0 means gpio and MUX 1 to N mean the specific device function. - The phandle of a node containing the generic pinconfig options - to use, as described in pinctrl-bindings.txt in this directory. - -Examples: - -#include - -... - -pinctrl@20008000 { - compatible = "rockchip,rk3066a-pinctrl"; - rockchip,grf = <&grf>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20034000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20034000 0x100>; - interrupts = ; - clocks = <&clk_gates8 9>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - ... - - pcfg_pull_default: pcfg_pull_default { - bias-pull-pin-default - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = , - ; - }; - }; -}; - -uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&mux_uart2>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; - -Example for rk3188: - - pinctrl@20008000 { - compatible = "rockchip,rk3188-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@0x2000a000 { - compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&clk_gates8 9>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@0x2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&clk_gates8 10>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - ... - - }; diff --git a/doc/device-tree-bindings/thermal/rockchip-thermal.txt b/doc/device-tree-bindings/thermal/rockchip-thermal.txt deleted file mode 100644 index ef802de4957..00000000000 --- a/doc/device-tree-bindings/thermal/rockchip-thermal.txt +++ /dev/null @@ -1,68 +0,0 @@ -* Temperature Sensor ADC (TSADC) on rockchip SoCs - -Required properties: -- compatible : "rockchip,rk3288-tsadc" -- reg : physical base address of the controller and length of memory mapped - region. -- interrupts : The interrupt number to the cpu. The interrupt specifier format - depends on the interrupt controller. -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for - the peripheral clock. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the name "tsadc-apb". -- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. -- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value. -- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO. -- rockchip,hw-tshut-polarity : The hardware-controlled active polarity 0:LOW - 1:HIGH. - -Exiample: -tsadc: tsadc@ff280000 { - compatible = "rockchip,rk3288-tsadc"; - reg = <0xff280000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "default"; - pinctrl-0 = <&otp_out>; - #thermal-sensor-cells = <1>; - rockchip,hw-tshut-temp = <95000>; - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; -}; - -Example: referring to thermal sensors: -thermal-zones { - cpu_thermal: cpu_thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tsadc 1>; - - trips { - cpu_alert0: cpu_alert { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; diff --git a/doc/device-tree-bindings/usb/dwc2.txt b/doc/device-tree-bindings/usb/dwc2.txt index 61493f7cb0c..7a533f65934 100644 --- a/doc/device-tree-bindings/usb/dwc2.txt +++ b/doc/device-tree-bindings/usb/dwc2.txt @@ -5,10 +5,6 @@ Required properties: - compatible : One of: - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC. - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC. - - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc; - - "rockchip,px30-usb", "rockchip,rk3066-usb", "snps,dwc2": for px30 Soc; - - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc; - - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc; - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs; - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs; - "amlogic,meson8-usb": The DWC2 USB controller instance in Amlogic Meson8 SoCs; diff --git a/doc/device-tree-bindings/video/rockchip-lvds.txt b/doc/device-tree-bindings/video/rockchip-lvds.txt deleted file mode 100644 index 7432e221669..00000000000 --- a/doc/device-tree-bindings/video/rockchip-lvds.txt +++ /dev/null @@ -1,77 +0,0 @@ -Rockchip LVDS interface ------------------- - -Required properties: -- compatible: "rockchip,rk3288-lvds"; - -- reg: physical base address of the controller and length - of memory mapped region. -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. -- clock-names: must contain "pclk_lvds" - -- rockchip,grf: phandle to the general register files syscon - -- rockchip,data-mapping: should be or , - This describes how the color bits are laid out in the - serialized LVDS signal. -- rockchip,data-width : should be <18> or <24>; -- rockchip,output: should be , or - , This describes the output face. - -- display-timings : described by - doc/device-tree-bindings/video/display-timing.txt. - -Example: - lvds: lvds@ff96c000 { - compatible = "rockchip,rk3288-lvds"; - reg = <0xff96c000 0x4000>; - clocks = <&cru PCLK_LVDS_PHY>; - clock-names = "pclk_lvds"; - pinctrl-names = "default"; - pinctrl-0 = <&lcdc0_ctl>; - rockchip,grf = <&grf>; - status = "disabled"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - lvds_in: port@0 { - reg = <0>; - - #address-cells = <1>; - #size-cells = <0>; - - lvds_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_lvds>; - }; - lvds_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_lvds>; - }; - }; - }; - }; - - &lvds { - rockchip,data-mapping = ; - rockchip,data-width = <24>; - rockchip,output = ; - rockchip,panel = <&panel>; - status = "okay"; - - display-timings { - timing@0 { - clock-frequency = <40000000>; - hactive = <1920>; - vactive = <1080>; - hsync-len = <44>; - hfront-porch = <88>; - hback-porch = <148>; - vfront-porch = <4>; - vback-porch = <36>; - vsync-len = <5>; - }; - }; - }; From d9825e8d0f34d47a1a3568390db53b5954ef72b3 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Mon, 2 Dec 2024 20:03:53 +0800 Subject: [PATCH 29/70] doc: coolpi: Fix document style Add a blank line after title "Specification:" to make it render correctly html. And also remove the useless > in bash code block. Signed-off-by: Andy Yan Reviewed-by: Quentin Schulz --- doc/board/coolpi/genbook_cm5_rk3588.rst | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/doc/board/coolpi/genbook_cm5_rk3588.rst b/doc/board/coolpi/genbook_cm5_rk3588.rst index a02e561051a..cad2a28acbd 100644 --- a/doc/board/coolpi/genbook_cm5_rk3588.rst +++ b/doc/board/coolpi/genbook_cm5_rk3588.rst @@ -6,6 +6,7 @@ Cool Pi GenBook is a laptop powered by RK3588, it works with a carrier board connect with CM5. Specification: + * Rockchip RK3588 * LPDDR5X 8/32 GB * eMMC 64 GB @@ -24,11 +25,11 @@ Get the TF-A and DDR init (TPL) binaries .. prompt:: bash - > cd u-boot - > export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin - > export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.46.elf - > make coolpi-genbook-cm5-rk3588_defconfig - > make CROSS_COMPILE=aarch64-linux-gnu- + cd u-boot + export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin + export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.46.elf + make coolpi-genbook-cm5-rk3588_defconfig + make CROSS_COMPILE=aarch64-linux-gnu- This will build ``u-boot-rockchip.bin`` for eMMC and ``u-boot-rockchip-spi.bin`` for SPI Nor. From 920e165ebfc432b7fb91f2c5a10804480e3a9687 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 1 Dec 2024 08:24:21 -0700 Subject: [PATCH 30/70] efi_loader: Fix typos in enum efi_allocate_type Fix 'indicatged' and 'adress' typos. Signed-off-by: Simon Glass Reviewed-by: Heinrich Schuchardt Reviewed-by: Tom Rini --- include/efi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/efi.h b/include/efi.h index c559fda3004..d50b3d3cec9 100644 --- a/include/efi.h +++ b/include/efi.h @@ -175,7 +175,7 @@ enum efi_allocate_type { EFI_ALLOCATE_MAX_ADDRESS, /** * @EFI_ALLOCATE_ADDRESS: - * Allocate a memory block starting at the indicatged adress. + * Allocate a memory block starting at the indicated address. */ EFI_ALLOCATE_ADDRESS, /** From c7360f17fbce8023fb1e634453968007b64e68c0 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Mon, 2 Dec 2024 14:01:26 +0100 Subject: [PATCH 31/70] doc: board: theobroma-systems: fix feature list in introductions Board introductions have a feature list which isn't formatted properly according to rST and is thus rendered incorrectly. Fix this by adding the missing newlines in the appropriate places. Signed-off-by: Quentin Schulz --- doc/board/theobroma-systems/puma_rk3399.rst | 1 + doc/board/theobroma-systems/tiger_rk3588.rst | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/doc/board/theobroma-systems/puma_rk3399.rst b/doc/board/theobroma-systems/puma_rk3399.rst index 5bc6385e451..a2a5e7bca4b 100644 --- a/doc/board/theobroma-systems/puma_rk3399.rst +++ b/doc/board/theobroma-systems/puma_rk3399.rst @@ -27,6 +27,7 @@ RK3399-Q7 features: * Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF) * NOR Flash: onboard SPI NOR * Companion Controller: onboard additional Cortex-M0 microcontroller + * RTC * fan controller * CAN diff --git a/doc/board/theobroma-systems/tiger_rk3588.rst b/doc/board/theobroma-systems/tiger_rk3588.rst index a73eec7fb9b..46112544c82 100644 --- a/doc/board/theobroma-systems/tiger_rk3588.rst +++ b/doc/board/theobroma-systems/tiger_rk3588.rst @@ -8,6 +8,7 @@ connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3588. It provides the following feature set: + * up to 16GB LPDDR4x * on-module eMMC * SD card (on a baseboard) via edge connector @@ -18,14 +19,20 @@ It provides the following feature set: * HDMI input over FPC connector * CAN * USB + - 1x USB 3.0 dual-role (direct connection) - 2x USB 3.0 host + 1x USB 2.0 host + * PCIe + - 1x PCIe 2.1 Gen3, 4 lanes - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes + * on-module ATtiny816 companion controller, implementing: + - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) + * on-module Secure Element with Global Platform 2.2.1 compliant JavaCard environment From d8b0020ddecfcf0d993bcfd45314ba8785d09fb1 Mon Sep 17 00:00:00 2001 From: Jerome Forissier Date: Tue, 3 Dec 2024 14:50:51 +0100 Subject: [PATCH 32/70] doc: environment: NET_LWIP dhcp sets ipaddrN, netmaskN and gatewayipN Document environment variables set by the dhcp command when the network stack is lwIP. Signed-off-by: Jerome Forissier --- doc/usage/environment.rst | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index 7bd9ffce8d8..30fc16794fc 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -499,12 +499,12 @@ Automatically updated variables ------------------------------- The following environment variables may be used and automatically -updated by the network boot commands ("bootp" and "rarpboot"), +updated by the network boot commands ("bootp", "dhcp" and "rarpboot"), depending the information provided by your boot server: -========= =================================================== +========== =================================================================== Variable Notes -========= =================================================== +========== =================================================================== bootfile see above dnsip IP address of your Domain Name Server dnsip2 IP address of your secondary Domain Name Server @@ -514,7 +514,10 @@ ipaddr See above netmask Subnet Mask rootpath Pathname of the root filesystem on the NFS server serverip see above -========= =================================================== +ipaddrN IP address for interface N (>0) (NET_LWIP dhcp only) +netmaskN Subnet mask for interface N (>0) (NET_LWIP dhcp only) +gatewayipN IP address of the Gateway for interface N (>0) (NET_LWIP dhcp only) +========== =================================================================== Special environment variables From 55e8704402350d06e8ebf244515d96c36a3bacf5 Mon Sep 17 00:00:00 2001 From: Leonard Anderweit Date: Fri, 13 Dec 2024 11:20:24 +0100 Subject: [PATCH 33/70] doc: cosmetic: fwu_updates: Fix formatting Remove one of the double colon so ..code-block is used for formatting. Signed-off-by: Leonard Anderweit Acked-by: Ilias Apalodimas Reviewed-by: Heinrich Schuchardt --- doc/develop/uefi/fwu_updates.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/develop/uefi/fwu_updates.rst b/doc/develop/uefi/fwu_updates.rst index 51e8a28efe1..84713581459 100644 --- a/doc/develop/uefi/fwu_updates.rst +++ b/doc/develop/uefi/fwu_updates.rst @@ -170,7 +170,7 @@ build the tool, enable:: CONFIG_TOOLS_MKEFICAPSULE=y -Run the following commands to generate the accept/revert capsules:: +Run the following commands to generate the accept/revert capsules: .. code-block:: bash @@ -180,7 +180,7 @@ Run the following commands to generate the accept/revert capsules:: Some examples of using the mkeficapsule tool for generation of the -empty capsule would be:: +empty capsule would be: .. code-block:: bash From b4626f3934767e2e40cd56fc4368af835fd94126 Mon Sep 17 00:00:00 2001 From: Wei Ming Chen Date: Sun, 13 Oct 2024 15:24:35 +0800 Subject: [PATCH 34/70] configs: ls1028a: Fix bootefi issue on Layerscape ls1028ardb platform MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Without this patch, there will be error indicating that "Cannot use 64 bit addresses with SDMA", and the booting process will stuck. please see full boot log below U-Boot 2022.04-g18185931 (Sep 11 2024 - 13:15:30 +0800) SoC: LS1028AE Rev1.0 (0x870b0010) Clock Configuration: CPU0(A72):1500 MHz CPU1(A72):1500 MHz Bus: 400 MHz DDR: 1600 MT/s Reset Configuration Word (RCW): 00000000: 3c004010 00000030 00000000 00000000 00000010: 00000000 018f0000 0030c000 00000000 00000020: 020031a0 00002580 00000000 00003296 00000030: 00000000 00000010 00000000 00000000 00000040: 00000000 00000000 00000000 00000000 00000050: 00000000 00000000 00000000 00000000 00000060: 00000000 00000000 200e705a 00000000 00000070: bb580000 00000000 Model: LS1028A RDB Board Board: LS1028AE Rev1.0-RDB, Version: C, boot from SD FPGA: v8 (RDB) SERDES1 Reference : Clock1 = 100.00MHz Clock2 = 100.00MHz DRAM: 3.9 GiB DDR 3.9 GiB (DDR4, 32-bit, CL=11, ECC on) Using SERDES1 Protocol: 47960 (0xbb58) PCIe1: pcie@3400000 Root Complex: no link PCIe2: pcie@3500000 Root Complex: x1 gen2 Core: 45 devices, 22 uclasses, devicetree: separate WDT: Started watchdog@c000000 with servicing (60s timeout) WDT: Started watchdog@c010000 with servicing (60s timeout) MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - bad CRC, using default environment EEPROM: Invalid ID (ff ff ff ff) In: serial Out: serial Err: serial SEC0: RNG instantiated Net: Warning: enetc-0 (eth0) using random MAC address - d2:9b:a5:37:7b:b5 eth0: enetc-0 Warning: enetc-2 (eth1) using random MAC address - ca:57:11:de:de:cb , eth1: enetc-2, eth2: swp0, eth3: swp1, eth4: swp2, eth5: swp3 Hit any key to stop autoboot: 0 Trying load HDP firmware from SD.. switch to partitions #0, OK mmc0 is current device Device: FSL_SDHC Manufacturer ID: 9f OEM: 5449 Name: SD32G Bus Speed: 50000000 Mode: SD High Speed (50MHz) Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 28.9 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes MMC read: dev # 0, block # 18944, count 512 ... 512 blocks read: OK Loading hdp firmware from 0x00000000a0000000 offset 0x0000000000002000 Loading hdp firmware Complete switch to partitions #0, OK mmc0 is current device Scanning mmc 0:1... ** Unable to read file / ** Failed to load '/' libfdt fdt_check_header(): FDT_ERR_BADMAGIC Scanning disk mmc@2140000.blk... Scanning disk mmc@2150000.blk... Found 7 disks ERROR: invalid device tree Found EFI removable media binary efi/boot/bootaa64.efi 981992 bytes read in 44 ms (21.3 MiB/s) libfdt fdt_check_header(): FDT_ERR_BADMAGIC WARNING could not find node vivante,gc: FDT_ERR_NOTFOUND. Booting /efi\boot\bootaa64.efi Cannot use 64 bit addresses with SDMA Error reading cluster ** Unable to read file /efi/boot/grubaa64.efi ** Unexpected return from initial read: Device Error, buffersize 29D790 Failed to load image ぀￢ : Device Error start_image() returned Device Error EFI LOAD FAILED: continuing... switch to partitions #0, OK mmc1(part 0) is current device Scanning mmc 1:1... ** Unable to read file / ** Failed to load '/' libfdt fdt_check_header(): FDT_ERR_BADMAGIC BootOrder not defined EFI boot manager: Cannot load any image Scanning mmc 1:2... ** Unable to read file / ** Failed to load '/' libfdt fdt_check_header(): FDT_ERR_BADMAGIC BootOrder not defined EFI boot manager: Cannot load any image starting USB... Bus usb@3100000: Register 200017f NbrPorts 2 Starting the controller USB XHCI 1.00 Bus usb@3110000: Register 200017f NbrPorts 2 Starting the controller USB XHCI 1.00 scanning bus usb@3100000 for devices... 1 USB Device(s) found scanning bus usb@3110000 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Device 0: unknown device Trying load from SD ... switch to partitions #0, OK mmc0 is current device Device: FSL_SDHC Manufacturer ID: 9f OEM: 5449 Name: SD32G Bus Speed: 50000000 Mode: SD High Speed (50MHz) Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 28.9 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes MMC read: dev # 0, block # 32768, count 81920 ... 81920 blocks read: OK Wrong Image Format for bootm command ERROR: can't get kernel image! Signed-off-by: Wei Ming Chen Signed-off-by: Peng Fan --- configs/ls1028ardb_tfa_defconfig | 1 + include/configs/ls1028ardb.h | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 09d5deea1e2..a535e8969b9 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -101,3 +101,4 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_RTL8152=y CONFIG_WDT=y CONFIG_WDT_SP805=y +CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index d44ce45fd6b..9c869ee6840 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -53,6 +53,7 @@ #define CFG_EXTRA_ENV_SETTINGS \ "board=ls1028ardb\0" \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "fdtfile=fsl-ls1028a-rdb.dtb\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ "bootm_size=0x10000000\0" \ From c71aaaf6a896589c97e6ebb45c85f577d435c1e5 Mon Sep 17 00:00:00 2001 From: Francois Berder Date: Wed, 10 Jul 2024 23:37:35 +0200 Subject: [PATCH 35/70] board: freescale: Replace invalid usage of sprintf by strcat buf was used as destination and as parameter to sprintf which triggers an undefined behaviour. This commit removes this usage of sprintf and uses strcat to append strings to buf variable. Signed-off-by: Francois Berder Signed-off-by: Peng Fan --- board/freescale/t208xqds/eth_t208xqds.c | 40 ++++++++++++------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 9f299227e29..b55078c8fe1 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -210,8 +210,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx1"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1"); - sprintf(buf, "%s%s%s", buf, "lane-c,", - (char *)lane_mode[0]); + strcat(buf, "lane-c,"); + strcat(buf, (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIIH_KX_MASK); break; @@ -222,8 +222,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx2"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2"); - sprintf(buf, "%s%s%s", buf, "lane-d,", - (char *)lane_mode[0]); + strcat(buf, "lane-d,"); + strcat(buf, (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIIG_KX_MASK); break; @@ -234,8 +234,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx9"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9"); - sprintf(buf, "%s%s%s", buf, "lane-a,", - (char *)lane_mode[0]); + strcat(buf, "lane-a,"); + strcat(buf, (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIIE_KX_MASK); break; @@ -247,8 +247,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, "phy_1gkx10"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio10"); - sprintf(buf, "%s%s%s", buf, "lane-b,", - (char *)lane_mode[0]); + strcat(buf, "lane-b,"); + strcat(buf, (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIIF_KX_MASK); break; @@ -269,8 +269,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx5"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5"); - sprintf(buf, "%s%s%s", buf, "lane-g,", - (char *)lane_mode[0]); + strcat(buf, "lane-g,"); + strcat(buf, (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIIC_KX_MASK); break; @@ -281,8 +281,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx6"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6"); - sprintf(buf, "%s%s%s", buf, "lane-h,", - (char *)lane_mode[0]); + strcat(buf, "lane-h,"); + strcat(buf, (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIID_KX_MASK); break; @@ -328,8 +328,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_xfi9"); fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9"); - sprintf(buf, "%s%s%s", buf, "lane-a,", - (char *)lane_mode[1]); + strcat(buf, "lane-a,"); + strcat(buf, (char *)lane_mode[1]); } break; case FM1_10GEC2: @@ -339,8 +339,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_xfi10"); fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10"); - sprintf(buf, "%s%s%s", buf, "lane-b,", - (char *)lane_mode[1]); + strcat(buf, "lane-b,"); + strcat(buf, (char *)lane_mode[1]); } break; case FM1_10GEC3: @@ -350,8 +350,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_xfi1"); fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1"); - sprintf(buf, "%s%s%s", buf, "lane-c,", - (char *)lane_mode[1]); + strcat(buf, "lane-c,"); + strcat(buf, (char *)lane_mode[1]); } break; case FM1_10GEC4: @@ -361,8 +361,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_xfi2"); fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2"); - sprintf(buf, "%s%s%s", buf, "lane-d,", - (char *)lane_mode[1]); + strcat(buf, "lane-d,"); + strcat(buf, (char *)lane_mode[1]); } break; default: From 822afeb7bf84ca1c9289a61ea99604b4deb8e091 Mon Sep 17 00:00:00 2001 From: Ronald Wahl Date: Wed, 11 Dec 2024 21:52:00 +0100 Subject: [PATCH 36/70] mmc: Fix potential timer value truncation On 64bit systems the timer value might be truncated to a 32bit value causing malfunctions. For example on ARM the timer might start from 0 again only after a cold reset. The 32bit overflow occurs after a bit more than 49 days (1000 Hz counter) so booting after that time may lead to a surprise because the board might become stuck requiring a cold reset. Signed-off-by: Ronald Wahl Cc: Peng Fan Cc: Jaehoon Chung Reviewed-by: Jaehoon Chung --- drivers/mmc/mmc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index efe98354a0f..799586891af 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -750,7 +750,7 @@ static int mmc_send_op_cond(struct mmc *mmc) { int err, i; int timeout = 1000; - uint start; + ulong start; /* Some cards seem to need this */ mmc_go_idle(mmc); @@ -844,7 +844,8 @@ int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value, bool send_status) { - unsigned int status, start; + ulong start; + unsigned int status; struct mmc_cmd cmd; int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS; bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) && From 1db256a3473645ed12de980355f6089baf544bf4 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 13 Dec 2024 16:53:18 +0200 Subject: [PATCH 37/70] driver: clk: tegra: partially support PLL clocks Return PLL id into struct clk if PLL is parsed from device tree instead of throwing an error. Allow requesting PLL clock rate via get_rate op. Signed-off-by: Svyatoslav Ryhel --- drivers/clk/tegra/tegra-car-clk.c | 47 +++++++++++++++++++++++++------ 1 file changed, 38 insertions(+), 9 deletions(-) diff --git a/drivers/clk/tegra/tegra-car-clk.c b/drivers/clk/tegra/tegra-car-clk.c index 1d61f8dc378..ec89d4b2b2d 100644 --- a/drivers/clk/tegra/tegra-car-clk.c +++ b/drivers/clk/tegra/tegra-car-clk.c @@ -10,6 +10,9 @@ #include #include +#define TEGRA_CAR_CLK_PLL BIT(0) +#define TEGRA_CAR_CLK_PERIPH BIT(1) + static int tegra_car_clk_request(struct clk *clk) { debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, @@ -20,24 +23,41 @@ static int tegra_car_clk_request(struct clk *clk) * varies per SoC) are the peripheral clocks, which use a numbering * scheme that matches HW registers 1:1. There are other clock IDs * beyond this that are assigned arbitrarily by the Tegra CAR DT - * binding. Due to the implementation of this driver, it currently - * only supports the peripheral IDs. + * binding. */ - if (clk->id >= PERIPH_ID_COUNT) - return -EINVAL; + if (clk->id < PERIPH_ID_COUNT) { + clk->data |= TEGRA_CAR_CLK_PERIPH; + return 0; + } - return 0; + /* If check for periph failed, then check for PLL clock id */ + int id = clk_id_to_pll_id(clk->id); + + if (clock_id_is_pll(id)) { + clk->id = id; + clk->data |= TEGRA_CAR_CLK_PLL; + return 0; + } + + return -EINVAL; } static ulong tegra_car_clk_get_rate(struct clk *clk) { - enum clock_id parent; - debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, clk->id); - parent = clock_get_periph_parent(clk->id); - return clock_get_periph_rate(clk->id, parent); + if (clk->data & TEGRA_CAR_CLK_PLL) + return clock_get_rate(clk->id); + + if (clk->data & TEGRA_CAR_CLK_PERIPH) { + enum clock_id parent; + + parent = clock_get_periph_parent(clk->id); + return clock_get_periph_rate(clk->id, parent); + } + + return -1U; } static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate) @@ -47,6 +67,9 @@ static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate) debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate, clk->dev, clk->id); + if (clk->data & TEGRA_CAR_CLK_PLL) + return 0; + parent = clock_get_periph_parent(clk->id); return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL); } @@ -56,6 +79,9 @@ static int tegra_car_clk_enable(struct clk *clk) debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, clk->id); + if (clk->data & TEGRA_CAR_CLK_PLL) + return 0; + clock_enable(clk->id); return 0; @@ -66,6 +92,9 @@ static int tegra_car_clk_disable(struct clk *clk) debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, clk->id); + if (clk->data & TEGRA_CAR_CLK_PLL) + return 0; + clock_disable(clk->id); return 0; From b46bd4f87465bf9b8954590190f8e413d56544b3 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 13 Dec 2024 16:53:19 +0200 Subject: [PATCH 38/70] driver: clk: tegra: init basic clocks on probe In case DM drivers probe earlier than board clock setup is done init of basic clocks should be done in CAR driver probe as well. Add it to avoid possible clock related problems. Acked-by: Thierry Reding Signed-off-by: Svyatoslav Ryhel --- drivers/clk/tegra/tegra-car-clk.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/tegra/tegra-car-clk.c b/drivers/clk/tegra/tegra-car-clk.c index ec89d4b2b2d..880dd4f6ece 100644 --- a/drivers/clk/tegra/tegra-car-clk.c +++ b/drivers/clk/tegra/tegra-car-clk.c @@ -112,6 +112,9 @@ static int tegra_car_clk_probe(struct udevice *dev) { debug("%s(dev=%p)\n", __func__, dev); + clock_init(); + clock_verify(); + return 0; } From a8f09d62821750aa755a8fe40bb72febc9154f20 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 11 Dec 2024 06:18:58 -0700 Subject: [PATCH 39/70] test/py: Always use the current dir as the source tree The logic in get_details() retrieves the default source directory from the Labgrid settings. This is convenient for interactive use, since it allows pytests to be run from any directory and still find the source tree. However, it is not actually correct. Gitlab sets the current directory to the source tree and expects that to be used. At present it is ignored. The result is that Gitlab builds whatever happens to be in the default source directory, ignoring the tree it is supposed to be building. Fix this by using the directory of the source tree, always. This is obtained by looking at the grandparent of the conftest.py file. Signed-off-by: Simon Glass Reported-by: Tom Rini Fixes: bf89a8f1fc2 ("test: Introduce the concept of a role") Tested-by: Tom Rini --- test/py/conftest.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/test/py/conftest.py b/test/py/conftest.py index d9f074f3817..509d19b449d 100644 --- a/test/py/conftest.py +++ b/test/py/conftest.py @@ -144,6 +144,9 @@ def get_details(config): # Get a few provided parameters build_dir = config.getoption('build_dir') build_dir_extra = config.getoption('build_dir_extra') + + # The source tree must be the current directory + source_dir = os.path.dirname(os.path.dirname(TEST_PY_DIR)) if role: # When using a role, build_dir and build_dir_extra are normally not set, # since they are picked up from Labgrid-sjg via the u-boot-test-getrole @@ -172,15 +175,13 @@ def get_details(config): # Read the build directories here, in case none were provided in the # command-line arguments (board_type, board_type_extra, default_build_dir, - default_build_dir_extra, source_dir) = (vals['board'], - vals['board_extra'], vals['build_dir'], vals['build_dir_extra'], - vals['source_dir']) + default_build_dir_extra) = (vals['board'], + vals['board_extra'], vals['build_dir'], vals['build_dir_extra']) else: board_type = config.getoption('board_type') board_type_extra = config.getoption('board_type_extra') board_identity = config.getoption('board_identity') - source_dir = os.path.dirname(os.path.dirname(TEST_PY_DIR)) default_build_dir = source_dir + '/build-' + board_type default_build_dir_extra = source_dir + '/build-' + board_type_extra From 315fd02729eeeb9e1fd4dbbfb0349ab5d774b006 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 7 Dec 2024 07:52:27 -0700 Subject: [PATCH 40/70] boot: Use correct PHASE_ variable for expo This patch was written before the XPL change-over. Update the Makefile condition to the new way. Signed-off-by: Simon Glass Fixes: ae3b5928d61 ("x86: coreboot: Allow building an expo for...") Reviewed-by: Quentin Schulz --- boot/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boot/Makefile b/boot/Makefile index 43def7c33d7..a24fd90c510 100644 --- a/boot/Makefile +++ b/boot/Makefile @@ -60,7 +60,7 @@ obj-$(CONFIG_$(PHASE_)LOAD_FIT) += common_fit.o obj-$(CONFIG_$(PHASE_)EXPO) += expo.o scene.o expo_build.o obj-$(CONFIG_$(PHASE_)EXPO) += scene_menu.o scene_textline.o ifdef CONFIG_COREBOOT_SYSINFO -obj-$(CONFIG_$(SPL_TPL_)EXPO) += expo_build_cb.o +obj-$(CONFIG_$(PHASE_)EXPO) += expo_build_cb.o endif obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE) += vbe.o From 1cde96bee57ead9714d0ee2f484e0be4540f3fad Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 12 Dec 2024 17:59:03 -0700 Subject: [PATCH 41/70] gitlab: Add an rpi to the sjg lab I have an original rpi installed now, loaded with OS Lite (32-bit) Add an entry for it so that it can be used for testing. Signed-off-by: Simon Glass Reviewed-by: Tom Rini Acked-by: Ilias Apalodimas --- .gitlab-ci.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2164ad79a72..579d43eacb7 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -678,3 +678,8 @@ nyan-big: variables: ROLE: nyan-big <<: *lab_dfn + +rpi: + variables: + ROLE: rpi + <<: *lab_dfn From 25fb58e88aba0c4af0af554d7b141be3f2e5e0b5 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 13 Dec 2024 14:26:55 +0100 Subject: [PATCH 42/70] ARM: stm32mp: Fix dram_bank_mmu_setup() for LMB located above ram_top Previously, all LMB marked with LMB_NOMAP (above and below ram_top) are considered as invalid entry in TLB. Since commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank") all LMB located above ram_top are now marked LMB_NOOVERWRITE and no more LMB_MAP. This area above ram_top is reserved for OPTEE and must not be cacheable, otherwise this leads to a Panic on some boards (Issue on STM32MP135F-DK). Restore previous behavior by marking invalid entry all TLB above ram_top. Fixes: 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank") Signed-off-by: Patrice Chotard cc: Sughosh Ganu Acked-by: Sughosh Ganu --- arch/arm/mach-stm32mp/stm32mp1/cpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 62cc98910a7..cb1b84c9af9 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -53,6 +53,7 @@ void dram_bank_mmu_setup(int bank) struct bd_info *bd = gd->bd; int i; phys_addr_t start; + phys_addr_t addr; phys_size_t size; bool use_lmb = false; enum dcache_option option; @@ -77,8 +78,12 @@ void dram_bank_mmu_setup(int bank) for (i = start >> MMU_SECTION_SHIFT; i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); i++) { + addr = i << MMU_SECTION_SHIFT; option = DCACHE_DEFAULT_OPTION; - if (use_lmb && lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP)) + if (use_lmb && + (lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP) || + addr >= gd->ram_top) + ) option = 0; /* INVALID ENTRY in TLB */ set_section_dcache(i, option); } From d4ce588515c182648f05f7f020df5842aa0754d9 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 18 Dec 2024 08:58:33 +0100 Subject: [PATCH 43/70] Kconfig: Set STACK_SIZE to 16KB for STM32 MCUs Since commit 6534d26ee9a5 ("lmb: do away with arch_lmb_reserve()"), STM32F746-disco hangs when loading device tree just before starting kernel: Retrieving file: /stm32f746-disco.dtb Kernel image @ 0xc0008000 [ 0x000000 - 0x19ae00 ] Flattened Device Tree blob at c0408000 Booting using the fdt blob at 0xc0408000 Working FDT set to c0408000 Loading Device Tree to c05f8000, end c05ff71c ... Adjust STACK_SIZE to 16KB for STM32 MCUs (F4/F7 and H7) boards to fix kernel boot process as some of these boards embeds a limited amount of memory. Fixes: 6534d26ee9a5 ("lmb: do away with arch_lmb_reserve()") Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/Kconfig b/Kconfig index 1f5b0f1972d..c087a420a24 100644 --- a/Kconfig +++ b/Kconfig @@ -578,6 +578,7 @@ config STACK_SIZE hex "Define max stack size that can be used by U-Boot" default 0x4000000 if ARCH_VERSAL_NET || ARCH_VERSAL || ARCH_ZYNQMP default 0x200000 if MICROBLAZE + default 0x4000 if ARCH_STM32 default 0x1000000 help Define Max stack size that can be used by U-Boot. This value is used From edc425ef16d30175b15fe6c895b622738fb2f58c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 16 Dec 2024 00:31:38 +0100 Subject: [PATCH 44/70] ARM: dts: stm32: Reinstate missing root oscillators on STM32MP15xx The root oscillators reference used to be in rcc node since 3d15245502c4 ("ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driver") however this is not part of upstream stm32mp151.dtsi . The RCC driver does need this reference, reinstate it globally. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard Tested-by: Patrice Chotard --- arch/arm/dts/stm32mp15-u-boot.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index 66d4c40c6a8..3f57bd5fe0f 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -186,6 +186,9 @@ bootph-all; #address-cells = <1>; #size-cells = <0>; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, + <&clk_lse>, <&clk_lsi>; }; &usart1 { From b6519061228f6076c7be43aca9c537daf53021c5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 16 Dec 2024 00:29:12 +0100 Subject: [PATCH 45/70] ARM: dts: stm32: Reinstate missing root oscillators on DH STM32MP15xx DHCOR The root oscillators reference used to be in rcc node since 3d15245502c4 ("ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driver") however this is not part of upstream stm32mp151.dtsi . The RCC driver does need this reference, reinstate it locally. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 08439342cb2..ab162f39473 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -112,6 +112,10 @@ }; &rcc { + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, + <&clk_lse>, <&clk_lsi>; + st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P From dae1f13daaec6e0d1b1fd8cec95662946e12d1fd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 16 Dec 2024 00:29:13 +0100 Subject: [PATCH 46/70] ARM: dts: stm32: Reinstate SPL_SYS_MMCSD_RAW_MODE on DH STM32MP15xx DHSOM Commit 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") broke booting from SD card on STM32MP15xx , reinstate raw mode SD boot configuration options and select the correct raw mode partition for STM32MP15xx to fix SD boot on STM32MP15xx DHSOM. Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") Reported-by: Patrice Chotard Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- configs/stm32mp15_dhsom.config | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/stm32mp15_dhsom.config b/configs/stm32mp15_dhsom.config index efc149577ea..04ee9bfc444 100644 --- a/configs/stm32mp15_dhsom.config +++ b/configs/stm32mp15_dhsom.config @@ -57,11 +57,14 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_STACK=0x30000000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SPL_TEXT_BASE=0x2FFC2500 CONFIG_SPL_USB_GADGET=y CONFIG_STM32_ADC=y CONFIG_SYSRESET_SYSCON=y CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MALLOC_F_LEN=0x3000 CONFIG_SYS_PBSIZE=1050 CONFIG_PREBOOT="run dh_preboot" From 72c6a40fad72bc1f1b7f1e44172c1017395ecfd7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 16 Dec 2024 00:29:14 +0100 Subject: [PATCH 47/70] ARM: dts: stm32: Drop access-controllers from SPL DT on DH STM32MP15xx DHSOM The access-controllers DT property is not useful in STM32MP15xx SPL, remove it to reduce SPL control DT size. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- configs/stm32mp15_dhcom_basic_defconfig | 2 +- configs/stm32mp15_dhcor_basic_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index b730bf76dca..5add66fb2f4 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -7,5 +7,5 @@ CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_SYS_I2C_EEPROM_BUS=3 CONFIG_OF_LIST="st/stm32mp157c-dhcom-pdk2 st/stm32mp153c-dhcom-drc02 st/stm32mp157c-dhcom-picoitx" -CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks access-controllers" CONFIG_SYS_I2C_EEPROM_ADDR=0x50 diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 42a596505ca..dd14db3b4c5 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -5,7 +5,7 @@ CONFIG_ARCH_STM32MP=y CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-dhcor-avenger96" CONFIG_SYS_I2C_EEPROM_BUS=2 CONFIG_OF_LIST="st/stm32mp157a-dhcor-avenger96 st/stm32mp151a-dhcor-testbench st/stm32mp153c-dhcor-drc-compact" -CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks access-controllers" CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y From 5470a6a0b11c2084fff0e09702a9c9ae716512c6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 16 Dec 2024 00:29:15 +0100 Subject: [PATCH 48/70] ARM: dts: stm32: Deduplicate CONFIG_OF_SPL_REMOVE_PROPS on DH STM32MP15xx DHSOM The content of CONFIG_OF_SPL_REMOVE_PROPS is the same in both STM32MP15xx DHCOM and DHCOR defconfigs, deduplicate the content into stm32mp15_dhsom.config . Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- configs/stm32mp15_dhcom_basic_defconfig | 1 - configs/stm32mp15_dhcor_basic_defconfig | 1 - configs/stm32mp15_dhsom.config | 1 + 3 files changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index 5add66fb2f4..a28f2862048 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -7,5 +7,4 @@ CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_SYS_I2C_EEPROM_BUS=3 CONFIG_OF_LIST="st/stm32mp157c-dhcom-pdk2 st/stm32mp153c-dhcom-drc02 st/stm32mp157c-dhcom-picoitx" -CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks access-controllers" CONFIG_SYS_I2C_EEPROM_ADDR=0x50 diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index dd14db3b4c5..f6f2af6e7a2 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_STM32MP=y CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-dhcor-avenger96" CONFIG_SYS_I2C_EEPROM_BUS=2 CONFIG_OF_LIST="st/stm32mp157a-dhcor-avenger96 st/stm32mp151a-dhcor-testbench st/stm32mp153c-dhcor-drc-compact" -CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks access-controllers" CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/stm32mp15_dhsom.config b/configs/stm32mp15_dhsom.config index 04ee9bfc444..ac3ae82cda9 100644 --- a/configs/stm32mp15_dhsom.config +++ b/configs/stm32mp15_dhsom.config @@ -22,6 +22,7 @@ CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_HWSPINLOCK_STM32=y CONFIG_KS8851_MLL=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks access-controllers" CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PINCTRL_STMFX=y CONFIG_REMOTEPROC_STM32_COPRO=y From 7169576807ec2f70a6f32c2cd8b3717b9451074f Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 16 Dec 2024 11:22:15 +0100 Subject: [PATCH 49/70] configs: stm32mp1: Restore boot SPL from sdcard for stm32mp15 Restore boot SPL from sdcard for STM32MP1 platforms. Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32mp15_basic_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 1c0d0d0a073..dcf44bcc0e7 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -38,6 +38,9 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MTD=y From c8eacfcedc6264af4acad12a0408e5fda45ecc39 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 16 Dec 2024 11:22:16 +0100 Subject: [PATCH 50/70] configs: stm32mp1: Restore boot SPL from sdcard for Engicam i.Core STM32MP1 C.TOUCH 2.0 Restore boot SPL from sdcard for Engicam i.Core STM32MP1 C.TOUCH 2.0. Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig index 4e171200ef2..00c475307c9 100644 --- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig @@ -27,6 +27,9 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y From fb612b4b532c62a38b09580c7f4470bd1159df63 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 16 Dec 2024 11:22:17 +0100 Subject: [PATCH 51/70] configs: stm32mp1: Restore boot SPL from sdcard for Engicam i.Core STM32MP1 EDIMM2.2 Restore boot SPL from sdcard for Engicam i.Core STM32MP1 EDIMM2.2. Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig index 3f7eebd21d8..b733913be01 100644 --- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig @@ -27,6 +27,9 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y From f3f14c2e3b9036bfe52a7da8775f87805b3cedf5 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 16 Dec 2024 11:22:18 +0100 Subject: [PATCH 52/70] configs: stm32mp1: Restore boot SPL from sdcard for Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF Restore boot SPL from sdcard for Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig index b32f71d90eb..35df3ea809d 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig @@ -27,6 +27,9 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y From 06a8063ec95c127a8efea5274955bea6a38fc057 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 16 Dec 2024 11:22:19 +0100 Subject: [PATCH 53/70] configs: stm32mp1: Restore boot SPL from sdcard for Engicam i.Core STM32MP1 C.TOUCH 2.0 Restore boot SPL from sdcard for Engicam i.Core STM32MP1 C.TOUCH 2.0. Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig index 8a16216f926..d1a92cbfbaa 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig @@ -27,6 +27,9 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y From 53a0ddb6d3bed9f9607af79934a7625299c36793 Mon Sep 17 00:00:00 2001 From: Nicolas Belin Date: Tue, 17 Dec 2024 14:29:08 +0100 Subject: [PATCH 54/70] boot: android: fix extra command line support Check that the value at the address kcmdline_extra is not 0 instead of checking the address value itself keeping it consistent with what is done for kcmdline. Fixes: b36b227b ("android: boot: support extra command line") Reviewed-by: Mattijs Korpershoek Signed-off-by: Nicolas Belin Link: https://lore.kernel.org/r/20241217-fix-bootargs-concatenation-v2-1-b2fd7cf4e130@baylibre.com Signed-off-by: Mattijs Korpershoek --- boot/image-android.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boot/image-android.c b/boot/image-android.c index cd01278f211..57158280b41 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -292,7 +292,7 @@ int android_image_get_kernel(const void *hdr, len += strlen(img_data.kcmdline); } - if (img_data.kcmdline_extra) { + if (*img_data.kcmdline_extra) { printf("Kernel extra command line: %s\n", img_data.kcmdline_extra); len += strlen(img_data.kcmdline_extra); } @@ -316,7 +316,7 @@ int android_image_get_kernel(const void *hdr, if (*img_data.kcmdline) strcat(newbootargs, img_data.kcmdline); - if (img_data.kcmdline_extra) { + if (*img_data.kcmdline_extra) { strcat(newbootargs, " "); strcat(newbootargs, img_data.kcmdline_extra); } From fd8b44a81be55b33c7defbe96a1ddd79ed286eb4 Mon Sep 17 00:00:00 2001 From: Nicolas Belin Date: Tue, 17 Dec 2024 14:29:09 +0100 Subject: [PATCH 55/70] boot: android: free newbootargs when done Free newbootargs when the concatenation is done and bootargs env is set. Fixes: 86f4695b ("image: Fix Android boot image support") Reviewed-by: Mattijs Korpershoek Signed-off-by: Nicolas Belin Link: https://lore.kernel.org/r/20241217-fix-bootargs-concatenation-v2-2-b2fd7cf4e130@baylibre.com Signed-off-by: Mattijs Korpershoek --- boot/image-android.c | 1 + 1 file changed, 1 insertion(+) diff --git a/boot/image-android.c b/boot/image-android.c index 57158280b41..362a5c7435a 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -322,6 +322,7 @@ int android_image_get_kernel(const void *hdr, } env_set("bootargs", newbootargs); + free(newbootargs); if (os_data) { if (image_get_magic(ihdr) == IH_MAGIC) { From 9e5fad0f792539ae4258bc116bf408bb6faf7e82 Mon Sep 17 00:00:00 2001 From: Nicolas Belin Date: Tue, 17 Dec 2024 14:29:10 +0100 Subject: [PATCH 56/70] boot: android: rework bootargs concatenation Rework the bootargs concatenation allocating more accurately the length that is needed. Do not forget an extra byte for the null termination byte as, in some cases, the allocation was 1 byte short. Fixes: 86f4695b ("image: Fix Android boot image support") Signed-off-by: Nicolas Belin Reviewed-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20241217-fix-bootargs-concatenation-v2-3-b2fd7cf4e130@baylibre.com Signed-off-by: Mattijs Korpershoek --- boot/image-android.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/boot/image-android.c b/boot/image-android.c index 362a5c7435a..61ac312db7a 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -287,37 +287,40 @@ int android_image_get_kernel(const void *hdr, kernel_addr, DIV_ROUND_UP(img_data.kernel_size, 1024)); int len = 0; + char *bootargs = env_get("bootargs"); + + if (bootargs) + len += strlen(bootargs); + if (*img_data.kcmdline) { printf("Kernel command line: %s\n", img_data.kcmdline); - len += strlen(img_data.kcmdline); + len += strlen(img_data.kcmdline) + (len ? 1 : 0); /* +1 for extra space */ } if (*img_data.kcmdline_extra) { printf("Kernel extra command line: %s\n", img_data.kcmdline_extra); - len += strlen(img_data.kcmdline_extra); + len += strlen(img_data.kcmdline_extra) + (len ? 1 : 0); /* +1 for extra space */ } - char *bootargs = env_get("bootargs"); - if (bootargs) - len += strlen(bootargs); - - char *newbootargs = malloc(len + 2); + char *newbootargs = malloc(len + 1); /* +1 for the '\0' */ if (!newbootargs) { puts("Error: malloc in android_image_get_kernel failed!\n"); return -ENOMEM; } - *newbootargs = '\0'; + *newbootargs = '\0'; /* set to Null in case no components below are present */ - if (bootargs) { + if (bootargs) strcpy(newbootargs, bootargs); - strcat(newbootargs, " "); + + if (*img_data.kcmdline) { + if (*newbootargs) /* If there is something in newbootargs, a space is needed */ + strcat(newbootargs, " "); + strcat(newbootargs, img_data.kcmdline); } - if (*img_data.kcmdline) - strcat(newbootargs, img_data.kcmdline); - if (*img_data.kcmdline_extra) { - strcat(newbootargs, " "); + if (*newbootargs) /* If there is something in newbootargs, a space is needed */ + strcat(newbootargs, " "); strcat(newbootargs, img_data.kcmdline_extra); } From 937830713657640ee610234dabb6c5c648245dd8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 19 Dec 2024 10:19:57 -0600 Subject: [PATCH 57/70] binman: Regenerate tools/binman/entries.rst There have been a few changes to the areas that this file documents without having regenerated the file. Do so now. Signed-off-by: Tom Rini --- tools/binman/entries.rst | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst index e918162fb48..3a3cc647525 100644 --- a/tools/binman/entries.rst +++ b/tools/binman/entries.rst @@ -197,7 +197,7 @@ source files that the tool examples: To run the tool:: - $ tools/binman/fip_util.py -s /path/to/trusted-firmware-a + $ tools/binman/fip_util.py -s /path/to/arm-trusted-firmware Warning: UUID 'UUID_NON_TRUSTED_WORLD_KEY_CERT' is not mentioned in tbbr_config.c file Existing code in 'tools/binman/fip_util.py' is up-to-date @@ -862,14 +862,18 @@ The top-level 'fit' node supports the following special properties: can be provided as a directory. Each .dtb file in the directory is processed, , e.g.:: - fit,fdt-list-dir = "arch/arm/dts + fit,fdt-list-dir = "arch/arm/dts"; + + In this case the input directories are ignored and all devicetree + files must be in that directory. fit,sign Enable signing FIT images via mkimage as described in - verified-boot.rst. If the property is found, the private keys path is - detected among binman include directories and passed to mkimage via - -k flag. All the keys required for signing FIT must be available at - time of signing and must be located in single include directory. + verified-boot.rst. If the property is found, the private keys path + is detected among binman include directories and passed to mkimage + via -k flag. All the keys required for signing FIT must be + available at time of signing and must be located in single include + directory. Substitutions ~~~~~~~~~~~~~ @@ -985,7 +989,8 @@ same approach can of course be used for SPL images. Note that the `of-spl-remove-props` entryarg can be used to indicate additional properties to remove. It is often used to remove properties like -`clock-names` and `pinctrl-names` which are not needed in SPL builds. +`clock-names` and `pinctrl-names` which are not needed in SPL builds. This +value is automatically passed to binman by the U-Boot build. See :ref:`fdtgrep_filter` for more information. From b6691d0add999459393a19f0f02b66243ee2a4ae Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 5 Dec 2024 20:32:53 +0100 Subject: [PATCH 58/70] net: lwip: do not return CMD_RET_USAGE if no interface If the dns command cannot find a network interface, we should return CMD_RETFAIURE and not -1 (CMD_RET_USAGE). Signed-off-by: Heinrich Schuchardt Reviewed-by: Jerome Forissier --- net/lwip/dns.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/lwip/dns.c b/net/lwip/dns.c index 4b937feaee1..1de63c9998b 100644 --- a/net/lwip/dns.c +++ b/net/lwip/dns.c @@ -56,7 +56,7 @@ static int dns_loop(struct udevice *udev, const char *name, const char *var) netif = net_lwip_new_netif(udev); if (!netif) - return -1; + return CMD_RET_FAILURE; dns_init(); From d701c6ab4220a3f5e0fdef06720816d67c46f56d Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Thu, 5 Dec 2024 20:17:36 +0100 Subject: [PATCH 59/70] net: lwip: check if network device is available in do_dhcp eth_get_dev() returns NULL if no network device is available. Not checking the return value leads to a crash when the device pointer is dereferenced. Signed-off-by: Heinrich Schuchardt Reviewed-by: Jerome Forissier --- net/lwip/dhcp.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/net/lwip/dhcp.c b/net/lwip/dhcp.c index 9b882cf5b87..e7d9147455c 100644 --- a/net/lwip/dhcp.c +++ b/net/lwip/dhcp.c @@ -3,6 +3,7 @@ #include #include +#include #include #include #include @@ -112,10 +113,17 @@ static int dhcp_loop(struct udevice *udev) int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { int ret; + struct udevice *dev; eth_set_current(); - ret = dhcp_loop(eth_get_dev()); + dev = eth_get_dev(); + if (!dev) { + log_err("No network device\n"); + return CMD_RET_FAILURE; + } + + ret = dhcp_loop(dev); if (ret) return ret; From ff1d5d87d0a18efb94e4fd5df0bb4c10b72a27bf Mon Sep 17 00:00:00 2001 From: E Shattow Date: Sun, 15 Dec 2024 22:32:12 -0800 Subject: [PATCH 60/70] Revert "configs: JH7110: enable EFI_LOADER_BOUNCE_BUFFER" ("Enable EFI_LOADER_BOUNCE_BUFFER") is not the correct fix for the problem it describes. The change of memory addressing leading to side-effects in commit 22f2c9ed9f53 ("efi: memory: use the lmb API's for allocating and freeing memory") is remedied by commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank"). This reverts commit 9c792ab336f7146e8d49bca6d9d093d2392ded5d. --- configs/starfive_visionfive2_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 20f89ae6796..1c70d1d4b70 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -32,7 +32,6 @@ CONFIG_CMODEL_MEDANY=y CONFIG_RISCV_SMODE=y # CONFIG_OF_BOARD_FIXUP is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y CONFIG_FIT=y CONFIG_BOOTSTD_DEFAULTS=y CONFIG_BOOTSTAGE=y From 0b7f4c7cf3270103a9aa8ffe2c2fb43d09b4ced5 Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Wed, 18 Dec 2024 11:00:06 +0200 Subject: [PATCH 61/70] imx: Fix usable memory ranges for imx8m SOCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit e27bddff4b97 ("imx8m: Restrict usable memory to space below 4G boundary") tried to adjust the usable memory limits on a 4GB boundary. ram_top is described as 'top address of RAM used by U-Boot' and we want to preserve that. This is defined as a phys_addr_t and unfortunately its size differs across architectures. This has lead us to a weird state where 32bit boards define it 'SZ_4GB - 1' and 64bit boards as 'SZ_4GB' unless it was otherwise defined. With some recent LMB changes and specifically commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank") the board fails to boot properly although the commit above is correct since it's making sure that no memory above ram_top is usable -- but added to our memory map so EFI can hand it over to the booted OS. The reason for that is that during the LMB init we add all usable memory in lmb_add_memory(). In that function any memory above ram_top gets added as 'reserved' for LMB. With the current values tha's set to 0xFFFF_FFFF for this board. Later LMB is trying to protect the memory area U-Boot lives in with lmb_reserve_common(). The latter fails though since it tries to add U-Boot top (which is 0xFFFF_FFFF as well) to U-Boot 'bottom'. This call will fail since 1 byte of that memory range is already marked as 'reserved'. Since we are close to the release, LMB seems to assume that the address is rounded up and is the 'next address' and so does parsing and adding memory ranges from DT files, bump the ram_top of the board by 1byte. In the long run we should change all of the above and have 32b and 64b platforms define ram_top identically. Add a Fixes tag although the commit is correct, so people can figure out the broken scenarios in the future. Suggested-by: Sughosh Ganu Fixes: commit 1a48b0be93d4 ("lmb: prohibit allocations above ram_top even from same bank") Signed-off-by: Ilias Apalodimas Reviewed-by: Frieder Schrempf Reported-by: João Paulo Gonçalves Closes: https://lore.kernel.org/all/20241216114231.qpfwug3zfqkxn3d5@joaog-nb.corp.toradex.com/ Reviewed-by: Peng Fan Fixes: 74f88b72219e ("ARM: imx: imx8m: Fix board_get_usable_ram_top()") --- arch/arm/mach-imx/imx8m/soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 9588b8b28bf..85dc8b51a14 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -362,7 +362,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) * space below the 4G address boundary (which is 3GiB big), * even when the effective available memory is bigger. */ - top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, 0xffffffff); + top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, SZ_4G); /* * rom_pointer[0] stores the TEE memory start address. From c06705a9a13d58e799b98927c360e93954b62860 Mon Sep 17 00:00:00 2001 From: Manorit Chawdhry Date: Tue, 10 Dec 2024 14:46:45 +0530 Subject: [PATCH 62/70] Makefile: Match the full path to ccache for filtering One can use ccache by keeping ccache in PATH or by providing the full path to ccache as well. Providing the full path to ccache fails as the current regex tries to look for ccache being the initial token during filtering. Do a greedy search to remove anything before ccache for regex matching. Fixes: 04b1d84221d5 ("Makefile: fix empty MK_ARCH when using ccache") Signed-off-by: Manorit Chawdhry --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 2e49f6088cc..70ed4983aa4 100644 --- a/Makefile +++ b/Makefile @@ -21,7 +21,7 @@ include include/host_arch.h ifeq ("", "$(CROSS_COMPILE)") MK_ARCH="${shell uname -m}" else - MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(ccache\)\{0,1\}[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}" + MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(.*ccache\)\{0,1\}[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}" endif unexport HOST_ARCH ifeq ("x86_64", $(MK_ARCH)) From 1b70b6c9cc98290fbd46da09c9f5a95f45121148 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Fri, 20 Dec 2024 08:37:42 +0530 Subject: [PATCH 63/70] common: memtop: Fix the return type for find_ram_top As the return type is "int" for find_ram_top() function and returning the "base" which is of phys_addr_t is breaking when the "base" address is 64-bit. So fix this by updating the return type as phys_addr_t. Signed-off-by: Venkatesh Yadav Abbarapu Reviewed-by: Michal Simek Acked-by: Sughosh Ganu Link: https://lore.kernel.org/r/20241220030742.1745984-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- common/memtop.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/memtop.c b/common/memtop.c index 841d89e0799..bff27d8211e 100644 --- a/common/memtop.c +++ b/common/memtop.c @@ -121,8 +121,8 @@ static long region_overlap_check(struct mem_region *mem_rgn, phys_addr_t base, return (i < mem_rgn->count) ? i : -1; } -static int find_ram_top(struct mem_region *free_mem, - struct mem_region *reserved_mem, phys_size_t size) +static phys_addr_t find_ram_top(struct mem_region *free_mem, + struct mem_region *reserved_mem, phys_size_t size) { long i, rgn; phys_addr_t base = 0; From 08806a6e5224e2500f54c2c29acbb6724fe7f5a9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 20 Dec 2024 01:04:08 +0100 Subject: [PATCH 64/70] clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Early revisions of the R-Car V4M Series Hardware User’s Manual contained an incorrect formula for the CPU core clocks: ZCnφ = (PLL2VCO x 1/2) x mult/32 Dang-san fixed this by using CLK_PLL2_DIV2 instead of CLK_PLL2 as the parent clock. In Rev.0.70 of the documentation, the formula was corrected to: ZCnφ = (PLL2VCO x 1/4) x mult/32 As the CPG Block Diagram now shows a separate 1/4 post-divider for PLL2, the use of CLK_PLL2_DIV2 is a recurring source of confusion. Hence get rid of CLK_PLL2_DIV2, and include the proper 1/4 post-divider in the invocation of the DEF_GEN4_Z() macro, like is done on other R-Car Gen4 (and Gen3) SoCs. Ported from Linux commit 92850bed9d4d ("clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks") Reported-by: Vinh Nguyen Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/0d2789cac2bf306145fe0bbf269c2da5942bb68f.1728377724.git.geert+renesas@glider.be Signed-off-by: Marek Vasut --- drivers/clk/renesas/r8a779h0-cpg-mssr.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 2e98e262fb0..70fa8ff2871 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -39,7 +39,6 @@ enum clk_ids { CLK_PLL6, CLK_PLL7, CLK_PLL1_DIV2, - CLK_PLL2_DIV2, CLK_PLL3_DIV2, CLK_PLL4_DIV2, CLK_PLL4_DIV5, @@ -82,7 +81,6 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { DEF_BASE(".pll7", CLK_PLL7, CLK_TYPE_GEN4_PLL7, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), - DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1), DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5, CLK_PLL4, 5, 1), @@ -106,10 +104,10 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { DEF_RATE(".oco", CLK_OCO, 32768), /* Core Clock Outputs */ - DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 0), - DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 8), - DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 32), - DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 40), + DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 0), + DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 8), + DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 32), + DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 40), DEF_FIXED("s0d2", R8A779H0_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A779H0_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A779H0_CLK_S0D4, CLK_S0, 4, 1), From 9899a6a7506c99c5c9e9265b8dbafb716089b6d9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 18 Dec 2024 20:41:28 +0100 Subject: [PATCH 65/70] net: renesas: Enable TFTP_TSIZE on all Renesas hardware TFTP transfer size can be used to re-size the TFTP progress bar on single line based on the server reported file size. Enable it by default for Renesas hardware to avoid long scrolling walls of '#' character during long TFTP transfers. Signed-off-by: Marek Vasut --- net/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/Kconfig b/net/Kconfig index 76ab7d91eeb..489ac19f8d1 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -90,7 +90,7 @@ config TFTP_WINDOWSIZE config TFTP_TSIZE bool "Track TFTP transfers based on file size option" depends on CMD_TFTPBOOT - default y if (ARCH_OMAP2PLUS || ARCH_K3) + default y if (ARCH_OMAP2PLUS || ARCH_K3 || ARCH_RENESAS) help By default, TFTP progress bar is increased for each received UDP frame, which can lead into long time being spent for sending From fa0f9e83a0654360506321e38c6d92888cb6f7ff Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 19 Dec 2024 11:52:46 +0100 Subject: [PATCH 66/70] net: rswitch: Add missing cache invalidate of TX descriptor TFTP transfers of large files, for example 128 MiB, can sporadically get stuck and the transfer slows down considerably. This happens because the TX DMA descriptor in DRAM becomes out of sync with the view of the TX DMA descriptor content from the CPU side, which is viewed through the CPU caches. In order to guarantee these two views are consistent, the cache over TX DMA descriptor that has possibly been written by the rswitch hardware must first be invalidated, only then can the descriptor be cleared and updated by the CPU, and finally the cache over that area must be flushed back into DRAM to make sure the rswitch hardware has consistent view of the updated descriptor content. The very first invalidation operation was missing, which led to sporadic corruption of the TX DMA descriptor. Fix it, add the missing invalidation operation. Reported-by: Enric Balletbo i Serra Signed-off-by: Marek Vasut Tested-by: Enric Balletbo i Serra --- drivers/net/rswitch.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index 8e1b6e2f6f6..97b5d1b75c1 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -837,6 +837,7 @@ static int rswitch_send(struct udevice *dev, void *packet, int len) /* Update TX descriptor */ rswitch_flush_dcache((uintptr_t)packet, len); + rswitch_invalidate_dcache((uintptr_t)desc, sizeof(*desc)); memset(desc, 0x0, sizeof(*desc)); desc->die_dt = DT_FSINGLE; desc->info_ds = len; From 118a10e1ddef895e078e48a0a9755141341e1585 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 22 Dec 2024 00:58:24 +0100 Subject: [PATCH 67/70] ARM: renesas: Consistently enable ENV_OVERWRITE on Renesas R-Car Move CONFIG_ENV_OVERWRITE=y into commont renesas_rcar.config to make sure this configuration option is consistently enabled on all of Renesas R-Car Gen2, Gen3, Gen4. Currently this option is not enabled on Gen4, this fix corrects that omission. Signed-off-by: Marek Vasut --- configs/renesas_rcar.config | 1 + configs/renesas_rcar2.config | 1 - configs/renesas_rcar3.config | 1 - 3 files changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/renesas_rcar.config b/configs/renesas_rcar.config index 351803b743a..d0a12f266aa 100644 --- a/configs/renesas_rcar.config +++ b/configs/renesas_rcar.config @@ -17,6 +17,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_OVERWRITE=y CONFIG_FIT=y CONFIG_HUSH_PARSER=y CONFIG_MTD=y diff --git a/configs/renesas_rcar2.config b/configs/renesas_rcar2.config index 74dfd41f1a3..4ffc4d05882 100644 --- a/configs/renesas_rcar2.config +++ b/configs/renesas_rcar2.config @@ -14,7 +14,6 @@ CONFIG_CMD_USB=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_OVERWRITE=y CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_SIZE=0x40000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/renesas_rcar3.config b/configs/renesas_rcar3.config index 228e1b4c679..7f7fab7df1d 100644 --- a/configs/renesas_rcar3.config +++ b/configs/renesas_rcar3.config @@ -2,5 +2,4 @@ CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y -CONFIG_ENV_OVERWRITE=y CONFIG_SYS_PBSIZE=2068 From 70da4f28592d0a2296b27a9126da97cc3b30891e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 21 Dec 2024 22:48:19 +0100 Subject: [PATCH 68/70] net: rswitch: Do not register disabled ports as ethernet devices In case an rswitch port is described as disabled in DT, do not register it as ethernet device in U-Boot. This way, such ports cannot be accessed from U-Boot command line. Signed-off-by: Marek Vasut --- drivers/net/rswitch.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index 97b5d1b75c1..57eff748c90 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -1113,6 +1113,9 @@ static int rswitch_bind(struct udevice *parent) return -ENOENT; ofnode_for_each_subnode(node, ports_np) { + if (!ofnode_is_enabled(node)) + continue; + ret = device_bind_with_driver_data(parent, drv, ofnode_get_name(node), (ulong)priv, node, &dev); From d532df3a614cf834213f6740fd56f0fd4e2d3662 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 23 Dec 2024 08:50:09 -0600 Subject: [PATCH 69/70] configs: Resync with savedefconfig Resync all defconfig files using qconfig.py Signed-off-by: Tom Rini --- configs/ls1028ardb_tfa_defconfig | 2 +- configs/rpi_3_b_plus_defconfig | 4 ++-- configs/rpi_3_defconfig | 4 ++-- configs/rpi_4_defconfig | 4 ++-- configs/rpi_arm64_defconfig | 4 ++-- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index a535e8969b9..89e452bdb1a 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -67,6 +67,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y @@ -101,4 +102,3 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_RTL8152=y CONFIG_WDT=y CONFIG_WDT_SP805=y -CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index a6a8431c8ff..b05a9193666 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -10,6 +10,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b-plus" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_BOOTSTD_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_FDT_SIMPLEFB=y @@ -55,5 +57,3 @@ CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y # CONFIG_HEXDUMP is not set -CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y -CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index 358096f3d1c..267e4978e6e 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -10,6 +10,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_BOOTSTD_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_FDT_SIMPLEFB=y @@ -55,5 +57,3 @@ CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y # CONFIG_HEXDUMP is not set -CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y -CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index 17b6688e75c..993b79703b7 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -10,6 +10,8 @@ CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_PCI=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_BOOTSTD_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_FDT_SIMPLEFB=y @@ -68,5 +70,3 @@ CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y # CONFIG_HEXDUMP is not set -CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y -CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index a8723ea24e1..9fe5d177943 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -8,6 +8,8 @@ CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_PCI=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_BOOTSTD_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_FDT_SIMPLEFB=y @@ -62,5 +64,3 @@ CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y # CONFIG_HEXDUMP is not set -CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y -CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y From 3391587e3fe22db6c71882f652e13543a4501694 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 23 Dec 2024 20:40:49 -0600 Subject: [PATCH 70/70] Prepare v2025.01-rc5 Signed-off-by: Tom Rini --- Makefile | 2 +- doc/develop/release_cycle.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 70ed4983aa4..ccc0b2fada8 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2025 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc4 +EXTRAVERSION = -rc5 NAME = # *DOCUMENTATION* diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 9f9252b18d2..c0e394f77cc 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -75,7 +75,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2025.01-rc4 was released on Mon 09 December 2024. -.. * U-Boot v2025.01-rc5 was released on Mon 23 December 2024. +* U-Boot v2025.01-rc5 was released on Mon 23 December 2024. .. * U-Boot v2025.01-rc6 was released on Mon 30 December 2024.