diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index a7bae035319..ff36d330e88 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -669,3 +669,8 @@ nyan-big: variables: ROLE: nyan-big <<: *lab_dfn + +rpi: + variables: + ROLE: rpi + <<: *lab_dfn diff --git a/Kconfig b/Kconfig index 2e63896c477..6379a454166 100644 --- a/Kconfig +++ b/Kconfig @@ -578,6 +578,7 @@ config STACK_SIZE hex "Define max stack size that can be used by U-Boot" default 0x4000000 if ARCH_VERSAL_NET || ARCH_VERSAL || ARCH_ZYNQMP default 0x200000 if MICROBLAZE + default 0x4000 if ARCH_STM32 default 0x1000000 help Define Max stack size that can be used by U-Boot. This value is used diff --git a/Makefile b/Makefile index 54fdf67c0d4..8da32868bae 100644 --- a/Makefile +++ b/Makefile @@ -3,7 +3,7 @@ VERSION = 2025 PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = -rc4 +EXTRAVERSION = -rc5 NAME = # *DOCUMENTATION* @@ -21,7 +21,7 @@ include include/host_arch.h ifeq ("", "$(CROSS_COMPILE)") MK_ARCH="${shell uname -m}" else - MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(ccache\)\{0,1\}[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}" + MK_ARCH="${shell echo $(CROSS_COMPILE) | sed -n 's/^\(.*ccache\)\{0,1\}[[:space:]]*\([^\/]*\/\)*\([^-]*\)-[^[:space:]]*/\3/p'}" endif unexport HOST_ARCH ifeq ("x86_64", $(MK_ARCH)) diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index aacf181e2dd..4202d1e5654 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -203,3 +203,7 @@ &sysclk { bootph-all; }; + +&usb0 { + dr_mode = "host"; +}; diff --git a/arch/arm/dts/r8a7790-u-boot.dtsi b/arch/arm/dts/r8a7790-u-boot.dtsi index 45e2fa6f9f0..2a7d76bd7b1 100644 --- a/arch/arm/dts/r8a7790-u-boot.dtsi +++ b/arch/arm/dts/r8a7790-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A7790 SoC + * Device Tree Source extras for U-Boot on R-Car R8A7790 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a7791-u-boot.dtsi b/arch/arm/dts/r8a7791-u-boot.dtsi index 7143ffc1658..bb0e2fd106c 100644 --- a/arch/arm/dts/r8a7791-u-boot.dtsi +++ b/arch/arm/dts/r8a7791-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A7791 SoC + * Device Tree Source extras for U-Boot on R-Car R8A7791 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a7792-u-boot.dtsi b/arch/arm/dts/r8a7792-u-boot.dtsi index 214cfde1f89..ebbdcb7efd5 100644 --- a/arch/arm/dts/r8a7792-u-boot.dtsi +++ b/arch/arm/dts/r8a7792-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A7792 SoC + * Device Tree Source extras for U-Boot on R-Car R8A7792 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a7793-u-boot.dtsi b/arch/arm/dts/r8a7793-u-boot.dtsi index fb947462c54..08f2248e1f3 100644 --- a/arch/arm/dts/r8a7793-u-boot.dtsi +++ b/arch/arm/dts/r8a7793-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A7793 SoC + * Device Tree Source extras for U-Boot on R-Car R8A7793 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a7794-u-boot.dtsi b/arch/arm/dts/r8a7794-u-boot.dtsi index 53b54c88917..303afaeb4ce 100644 --- a/arch/arm/dts/r8a7794-u-boot.dtsi +++ b/arch/arm/dts/r8a7794-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A7794 SoC + * Device Tree Source extras for U-Boot on R-Car R8A7794 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a77951-u-boot.dtsi b/arch/arm/dts/r8a77951-u-boot.dtsi index 4cbec591479..c16c5116592 100644 --- a/arch/arm/dts/r8a77951-u-boot.dtsi +++ b/arch/arm/dts/r8a77951-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A7795 SoC + * Device Tree Source extras for U-Boot on R-Car R8A7795 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a77960-u-boot.dtsi b/arch/arm/dts/r8a77960-u-boot.dtsi index 15a91474324..2245be2aa76 100644 --- a/arch/arm/dts/r8a77960-u-boot.dtsi +++ b/arch/arm/dts/r8a77960-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A7796 SoC + * Device Tree Source extras for U-Boot on R-Car R8A7796 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi index 54107d1ae35..f39acc237d3 100644 --- a/arch/arm/dts/r8a77965-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A77965 SoC + * Device Tree Source extras for U-Boot on R-Car R8A77965 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a77970-u-boot.dtsi b/arch/arm/dts/r8a77970-u-boot.dtsi index d252c2e8e6c..7900c641ba1 100644 --- a/arch/arm/dts/r8a77970-u-boot.dtsi +++ b/arch/arm/dts/r8a77970-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A77970 SoC + * Device Tree Source extras for U-Boot on R-Car R8A77970 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a77980-u-boot.dtsi b/arch/arm/dts/r8a77980-u-boot.dtsi index 9f7bf499bc0..aa7e058c585 100644 --- a/arch/arm/dts/r8a77980-u-boot.dtsi +++ b/arch/arm/dts/r8a77980-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A77980 SoC + * Device Tree Source extras for U-Boot on R-Car R8A77980 SoC * * Copyright (C) 2019 Marek Vasut */ diff --git a/arch/arm/dts/r8a77990-u-boot.dtsi b/arch/arm/dts/r8a77990-u-boot.dtsi index 50bbbe18647..b701f68db81 100644 --- a/arch/arm/dts/r8a77990-u-boot.dtsi +++ b/arch/arm/dts/r8a77990-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A77990 SoC + * Device Tree Source extras for U-Boot on R-Car R8A77990 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a77995-u-boot.dtsi b/arch/arm/dts/r8a77995-u-boot.dtsi index 347b59ac42c..f4bafb6d088 100644 --- a/arch/arm/dts/r8a77995-u-boot.dtsi +++ b/arch/arm/dts/r8a77995-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar R8A77995 SoC + * Device Tree Source extras for U-Boot on R-Car R8A77995 SoC * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/r8a779x-u-boot.dtsi b/arch/arm/dts/r8a779x-u-boot.dtsi index 001ac59adb9..d1441f1f9df 100644 --- a/arch/arm/dts/r8a779x-u-boot.dtsi +++ b/arch/arm/dts/r8a779x-u-boot.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source extras for U-Boot on RCar Gen3 + * Device Tree Source extras for U-Boot on R-Car Gen3 * * Copyright (C) 2018 Marek Vasut */ diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index 66d4c40c6a8..3f57bd5fe0f 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -186,6 +186,9 @@ bootph-all; #address-cells = <1>; #size-cells = <0>; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, + <&clk_lse>, <&clk_lsi>; }; &usart1 { diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 08439342cb2..ab162f39473 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -112,6 +112,10 @@ }; &rcc { + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, + <&clk_lse>, <&clk_lsi>; + st,clksrc = < CLK_MPU_PLL1P CLK_AXI_PLL2P diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 9588b8b28bf..85dc8b51a14 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -362,7 +362,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) * space below the 4G address boundary (which is 3GiB big), * even when the effective available memory is bigger. */ - top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, 0xffffffff); + top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, SZ_4G); /* * rom_pointer[0] stores the TEE memory start address. diff --git a/arch/arm/mach-renesas/Kconfig.32 b/arch/arm/mach-renesas/Kconfig.32 index 693a5abba0d..bbc61ccf480 100644 --- a/arch/arm/mach-renesas/Kconfig.32 +++ b/arch/arm/mach-renesas/Kconfig.32 @@ -1,11 +1,11 @@ if RCAR_32 config ARCH_RENESAS_BOARD_STRING - string "Renesas RCar Gen2 board name" + string "Renesas R-Car Gen2 board name" default "Board" config RCAR_GEN2 - bool "Renesas RCar Gen2" + bool "Renesas R-Car Gen2" select PHY select PHY_RCAR_GEN2 select TMU_TIMER diff --git a/arch/arm/mach-renesas/include/mach/boot0.h b/arch/arm/mach-renesas/include/mach/boot0.h index fe88a2e0373..2128eccd8a4 100644 --- a/arch/arm/mach-renesas/include/mach/boot0.h +++ b/arch/arm/mach-renesas/include/mach/boot0.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Specialty padding for the RCar Gen2 SPL JTAG loading + * Specialty padding for the R-Car Gen2 SPL JTAG loading */ #ifndef __BOOT0_H diff --git a/arch/arm/mach-renesas/memmap-gen3.c b/arch/arm/mach-renesas/memmap-gen3.c index c50700df078..d24419f5daa 100644 --- a/arch/arm/mach-renesas/memmap-gen3.c +++ b/arch/arm/mach-renesas/memmap-gen3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 memory map tables + * Renesas R-Car Gen3 memory map tables * * Copyright (C) 2017 Marek Vasut */ diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 62cc98910a7..cb1b84c9af9 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -53,6 +53,7 @@ void dram_bank_mmu_setup(int bank) struct bd_info *bd = gd->bd; int i; phys_addr_t start; + phys_addr_t addr; phys_size_t size; bool use_lmb = false; enum dcache_option option; @@ -77,8 +78,12 @@ void dram_bank_mmu_setup(int bank) for (i = start >> MMU_SECTION_SHIFT; i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); i++) { + addr = i << MMU_SECTION_SHIFT; option = DCACHE_DEFAULT_OPTION; - if (use_lmb && lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP)) + if (use_lmb && + (lmb_is_reserved_flags(i << MMU_SECTION_SHIFT, LMB_NOMAP) || + addr >= gd->ram_top) + ) option = 0; /* INVALID ENTRY in TLB */ set_section_dcache(i, option); } diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 9f299227e29..b55078c8fe1 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -210,8 +210,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx1"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1"); - sprintf(buf, "%s%s%s", buf, "lane-c,", - (char *)lane_mode[0]); + strcat(buf, "lane-c,"); + strcat(buf, (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIIH_KX_MASK); break; @@ -222,8 +222,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx2"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2"); - sprintf(buf, "%s%s%s", buf, "lane-d,", - (char *)lane_mode[0]); + strcat(buf, "lane-d,"); + strcat(buf, (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIIG_KX_MASK); break; @@ -234,8 +234,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx9"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9"); - sprintf(buf, "%s%s%s", buf, "lane-a,", - (char *)lane_mode[0]); + strcat(buf, "lane-a,"); + strcat(buf, (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIIE_KX_MASK); break; @@ -247,8 +247,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, "phy_1gkx10"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio10"); - sprintf(buf, "%s%s%s", buf, "lane-b,", - (char *)lane_mode[0]); + strcat(buf, "lane-b,"); + strcat(buf, (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIIF_KX_MASK); break; @@ -269,8 +269,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx5"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5"); - sprintf(buf, "%s%s%s", buf, "lane-g,", - (char *)lane_mode[0]); + strcat(buf, "lane-g,"); + strcat(buf, (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIIC_KX_MASK); break; @@ -281,8 +281,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_1gkx6"); fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6"); - sprintf(buf, "%s%s%s", buf, "lane-h,", - (char *)lane_mode[0]); + strcat(buf, "lane-h,"); + strcat(buf, (char *)lane_mode[0]); out_be32(&srds_regs->srdspccr1, srds1_pccr1 | PCCR1_SGMIID_KX_MASK); break; @@ -328,8 +328,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_xfi9"); fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9"); - sprintf(buf, "%s%s%s", buf, "lane-a,", - (char *)lane_mode[1]); + strcat(buf, "lane-a,"); + strcat(buf, (char *)lane_mode[1]); } break; case FM1_10GEC2: @@ -339,8 +339,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_xfi10"); fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10"); - sprintf(buf, "%s%s%s", buf, "lane-b,", - (char *)lane_mode[1]); + strcat(buf, "lane-b,"); + strcat(buf, (char *)lane_mode[1]); } break; case FM1_10GEC3: @@ -350,8 +350,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_xfi1"); fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1"); - sprintf(buf, "%s%s%s", buf, "lane-c,", - (char *)lane_mode[1]); + strcat(buf, "lane-c,"); + strcat(buf, (char *)lane_mode[1]); } break; case FM1_10GEC4: @@ -361,8 +361,8 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, fdt_set_phy_handle(fdt, compat, addr, "phy_xfi2"); fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2"); - sprintf(buf, "%s%s%s", buf, "lane-d,", - (char *)lane_mode[1]); + strcat(buf, "lane-d,"); + strcat(buf, (char *)lane_mode[1]); } break; default: diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index adfec8ba237..0baf5c63f18 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -156,7 +156,8 @@ int fsl_board_late_init(void) * If the watchdog isn't enabled at reset (which is a configuration * option) disabling it doesn't hurt either. */ - if (!IS_ENABLED(CONFIG_WATCHDOG_AUTOSTART)) + if (IS_ENABLED(CONFIG_WDT_SL28CPLD) && + !IS_ENABLED(CONFIG_WATCHDOG_AUTOSTART)) stop_recovery_watchdog(); return 0; diff --git a/board/kontron/sl28/spl.c b/board/kontron/sl28/spl.c index 45a4fc65120..6b31f5e3a7c 100644 --- a/board/kontron/sl28/spl.c +++ b/board/kontron/sl28/spl.c @@ -50,9 +50,10 @@ int board_fit_config_name_match(const char *name) return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var1"); case 2: return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var2"); + case 3: + return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var3"); case 4: return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28-var4"); - case 3: default: return strcmp(name, "freescale/fsl-ls1028a-kontron-sl28"); } diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index c46fe4b2350..aa39afa338a 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -68,6 +68,19 @@ struct msg_get_clock_rate { u32 end_tag; }; +struct efi_fw_image fw_images[] = { + { + .fw_name = u"RPI_UBOOT", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=u-boot.bin fat 0 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; + #ifdef CONFIG_ARM64 #define DTB_DIR "broadcom/" #else @@ -544,12 +557,15 @@ void update_fdt_from_fw(void *fdt, void *fw_fdt) if (fdt == fw_fdt) return; - /* The firmware provides a more precie model; so copy that */ + /* The firmware provides a more precise model; so copy that */ copy_property(fdt, fw_fdt, "/", "model"); /* memory reserve as suggested by the firmware */ copy_property(fdt, fw_fdt, "/", "memreserve"); + /* copy the CMA memory setting from the firmware DT to linux */ + copy_property(fdt, fw_fdt, "/reserved-memory/linux,cma", "size"); + /* Adjust dma-ranges for the SD card and PCI bus as they can depend on * the SoC revision */ diff --git a/boot/Makefile b/boot/Makefile index 43def7c33d7..a24fd90c510 100644 --- a/boot/Makefile +++ b/boot/Makefile @@ -60,7 +60,7 @@ obj-$(CONFIG_$(PHASE_)LOAD_FIT) += common_fit.o obj-$(CONFIG_$(PHASE_)EXPO) += expo.o scene.o expo_build.o obj-$(CONFIG_$(PHASE_)EXPO) += scene_menu.o scene_textline.o ifdef CONFIG_COREBOOT_SYSINFO -obj-$(CONFIG_$(SPL_TPL_)EXPO) += expo_build_cb.o +obj-$(CONFIG_$(PHASE_)EXPO) += expo_build_cb.o endif obj-$(CONFIG_$(PHASE_)BOOTMETH_VBE) += vbe.o diff --git a/boot/image-android.c b/boot/image-android.c index 93b54bf8d79..60a422dfb74 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -332,41 +332,45 @@ int android_image_get_kernel(const void *hdr, kernel_addr, DIV_ROUND_UP(img_data.kernel_size, 1024)); int len = 0; - if (*img_data.kcmdline) { - printf("Kernel command line: %s\n", img_data.kcmdline); - len += strlen(img_data.kcmdline); - } - - if (img_data.kcmdline_extra) { - printf("Kernel extra command line: %s\n", img_data.kcmdline_extra); - len += strlen(img_data.kcmdline_extra); - } - char *bootargs = env_get("bootargs"); + if (bootargs) len += strlen(bootargs); - char *newbootargs = malloc(len + 2); + if (*img_data.kcmdline) { + printf("Kernel command line: %s\n", img_data.kcmdline); + len += strlen(img_data.kcmdline) + (len ? 1 : 0); /* +1 for extra space */ + } + + if (*img_data.kcmdline_extra) { + printf("Kernel extra command line: %s\n", img_data.kcmdline_extra); + len += strlen(img_data.kcmdline_extra) + (len ? 1 : 0); /* +1 for extra space */ + } + + char *newbootargs = malloc(len + 1); /* +1 for the '\0' */ if (!newbootargs) { puts("Error: malloc in android_image_get_kernel failed!\n"); return -ENOMEM; } - *newbootargs = '\0'; + *newbootargs = '\0'; /* set to Null in case no components below are present */ - if (bootargs) { + if (bootargs) strcpy(newbootargs, bootargs); - strcat(newbootargs, " "); + + if (*img_data.kcmdline) { + if (*newbootargs) /* If there is something in newbootargs, a space is needed */ + strcat(newbootargs, " "); + strcat(newbootargs, img_data.kcmdline); } - if (*img_data.kcmdline) - strcat(newbootargs, img_data.kcmdline); - - if (img_data.kcmdline_extra) { - strcat(newbootargs, " "); + if (*img_data.kcmdline_extra) { + if (*newbootargs) /* If there is something in newbootargs, a space is needed */ + strcat(newbootargs, " "); strcat(newbootargs, img_data.kcmdline_extra); } env_set("bootargs", newbootargs); + free(newbootargs); if (os_data) { if (image_get_magic(ihdr) == IH_MAGIC) { diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 3d5b6f9e2dc..73c43c30684 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -77,7 +77,7 @@ static void boot_fdt_reserve_region(u64 addr, u64 size, enum lmb_flags flags) debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n", (unsigned long long)addr, (unsigned long long)size, flags); - } else { + } else if (ret != -EEXIST) { puts("ERROR: reserving fdt memory region failed "); printf("(addr=%llx size=%llx flags=%x)\n", (unsigned long long)addr, diff --git a/common/memtop.c b/common/memtop.c index 841d89e0799..bff27d8211e 100644 --- a/common/memtop.c +++ b/common/memtop.c @@ -121,8 +121,8 @@ static long region_overlap_check(struct mem_region *mem_rgn, phys_addr_t base, return (i < mem_rgn->count) ? i : -1; } -static int find_ram_top(struct mem_region *free_mem, - struct mem_region *reserved_mem, phys_size_t size) +static phys_addr_t find_ram_top(struct mem_region *free_mem, + struct mem_region *reserved_mem, phys_size_t size) { long i, rgn; phys_addr_t base = 0; diff --git a/common/usb_onboard_hub.c b/common/usb_onboard_hub.c index 6f28036e095..7fe62b043e6 100644 --- a/common/usb_onboard_hub.c +++ b/common/usb_onboard_hub.c @@ -183,7 +183,12 @@ static int usb_onboard_hub_bind(struct udevice *dev) int ret, off; ret = dev_read_phandle_with_args(dev, "peer-hub", NULL, 0, 0, &phandle); - if (ret) { + if (ret == -ENOENT) { + dev_dbg(dev, "peer-hub property not present\n"); + return 0; + } + + if (ret) { dev_err(dev, "peer-hub not specified\n"); return ret; } diff --git a/configs/am62x_a53_usbdfu.config b/configs/am62x_a53_usbdfu.config index 3a19cf23287..0d3c6df1e73 100644 --- a/configs/am62x_a53_usbdfu.config +++ b/configs/am62x_a53_usbdfu.config @@ -16,7 +16,6 @@ CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_GENERIC=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 35894a10cbe..1f684093252 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -54,6 +54,7 @@ CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_SYS_MALLOC_SIZE=0x200000 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x900 CONFIG_SPL_MPC8XXX_INIT_DDR=y @@ -77,7 +78,7 @@ CONFIG_CMD_RNG=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y -CONFIG_OF_LIST="freescale/fsl-ls1028a-kontron-sl28 freescale/fsl-ls1028a-kontron-sl28-var1 freescale/fsl-ls1028a-kontron-sl28-var2 freescale/fsl-ls1028a-kontron-sl28-var4" +CONFIG_OF_LIST="freescale/fsl-ls1028a-kontron-sl28 freescale/fsl-ls1028a-kontron-sl28-var1 freescale/fsl-ls1028a-kontron-sl28-var2 freescale/fsl-ls1028a-kontron-sl28-var3 freescale/fsl-ls1028a-kontron-sl28-var4" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 09d5deea1e2..89e452bdb1a 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -67,6 +67,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_SYS_I2C_EEPROM_ADDR=0x57 CONFIG_FSL_ESDHC=y +CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/renesas_rcar.config b/configs/renesas_rcar.config index 351803b743a..d0a12f266aa 100644 --- a/configs/renesas_rcar.config +++ b/configs/renesas_rcar.config @@ -17,6 +17,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_OVERWRITE=y CONFIG_FIT=y CONFIG_HUSH_PARSER=y CONFIG_MTD=y diff --git a/configs/renesas_rcar2.config b/configs/renesas_rcar2.config index 74dfd41f1a3..4ffc4d05882 100644 --- a/configs/renesas_rcar2.config +++ b/configs/renesas_rcar2.config @@ -14,7 +14,6 @@ CONFIG_CMD_USB=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_OVERWRITE=y CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_SIZE=0x40000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/renesas_rcar3.config b/configs/renesas_rcar3.config index 228e1b4c679..7f7fab7df1d 100644 --- a/configs/renesas_rcar3.config +++ b/configs/renesas_rcar3.config @@ -2,5 +2,4 @@ CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y -CONFIG_ENV_OVERWRITE=y CONFIG_SYS_PBSIZE=2068 diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig index 3c8f8fc1bb7..b05a9193666 100644 --- a/configs/rpi_3_b_plus_defconfig +++ b/configs/rpi_3_b_plus_defconfig @@ -10,6 +10,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b-plus" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_BOOTSTD_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_FDT_SIMPLEFB=y @@ -19,14 +21,19 @@ CONFIG_SYS_PBSIZE=1049 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y +CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000 CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y @@ -49,3 +56,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y +# CONFIG_HEXDUMP is not set diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index 9853c448809..267e4978e6e 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -10,6 +10,8 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="bcm2837-rpi-3-b" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_BOOTSTD_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_FDT_SIMPLEFB=y @@ -19,14 +21,19 @@ CONFIG_SYS_PBSIZE=1049 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y +CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000 CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y @@ -49,3 +56,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y +# CONFIG_HEXDUMP is not set diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig index f5fb322aa8f..993b79703b7 100644 --- a/configs/rpi_4_defconfig +++ b/configs/rpi_4_defconfig @@ -10,6 +10,8 @@ CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_PCI=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_BOOTSTD_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_FDT_SIMPLEFB=y @@ -20,11 +22,13 @@ CONFIG_SYS_PBSIZE=1049 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -65,3 +69,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y +# CONFIG_HEXDUMP is not set diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig index 02f942cf344..9fe5d177943 100644 --- a/configs/rpi_arm64_defconfig +++ b/configs/rpi_arm64_defconfig @@ -8,6 +8,8 @@ CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_PCI=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_BOOTSTD_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_FDT_SIMPLEFB=y @@ -18,15 +20,20 @@ CONFIG_SYS_PBSIZE=1049 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_FS_UUID=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_TFTP_TSIZE=y CONFIG_DM_DMA=y +CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000 CONFIG_BCM2835_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y @@ -56,3 +63,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_BCM2835=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_PHYS_TO_BUS=y +# CONFIG_HEXDUMP is not set diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 96056c50c84..c3f2142ae1b 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -32,7 +32,6 @@ CONFIG_CMODEL_MEDANY=y CONFIG_RISCV_SMODE=y # CONFIG_OF_BOARD_FIXUP is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y CONFIG_FIT=y CONFIG_BOOTSTD_DEFAULTS=y CONFIG_BOOTSTAGE=y diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig index 4e171200ef2..00c475307c9 100644 --- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig @@ -27,6 +27,9 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig index 3f7eebd21d8..b733913be01 100644 --- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig @@ -27,6 +27,9 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig index b32f71d90eb..35df3ea809d 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig @@ -27,6 +27,9 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig index 8a16216f926..d1a92cbfbaa 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig @@ -27,6 +27,9 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 1c0d0d0a073..dcf44bcc0e7 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -38,6 +38,9 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xc0300000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y CONFIG_SPL_MTD=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index b730bf76dca..a28f2862048 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -7,5 +7,4 @@ CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_SYS_I2C_EEPROM_BUS=3 CONFIG_OF_LIST="st/stm32mp157c-dhcom-pdk2 st/stm32mp153c-dhcom-drc02 st/stm32mp157c-dhcom-picoitx" -CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_SYS_I2C_EEPROM_ADDR=0x50 diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 42a596505ca..f6f2af6e7a2 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_STM32MP=y CONFIG_DEFAULT_DEVICE_TREE="st/stm32mp157a-dhcor-avenger96" CONFIG_SYS_I2C_EEPROM_BUS=2 CONFIG_OF_LIST="st/stm32mp157a-dhcor-avenger96 st/stm32mp151a-dhcor-testbench st/stm32mp153c-dhcor-drc-compact" -CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_SYS_I2C_EEPROM_ADDR=0x53 CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/stm32mp15_dhsom.config b/configs/stm32mp15_dhsom.config index efc149577ea..ac3ae82cda9 100644 --- a/configs/stm32mp15_dhsom.config +++ b/configs/stm32mp15_dhsom.config @@ -22,6 +22,7 @@ CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_HWSPINLOCK_STM32=y CONFIG_KS8851_MLL=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks access-controllers" CONFIG_PHY_ANEG_TIMEOUT=20000 CONFIG_PINCTRL_STMFX=y CONFIG_REMOTEPROC_STM32_COPRO=y @@ -57,11 +58,14 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_STACK=0x30000000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x1d00000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SPL_TEXT_BASE=0x2FFC2500 CONFIG_SPL_USB_GADGET=y CONFIG_STM32_ADC=y CONFIG_SYSRESET_SYSCON=y CONFIG_SYS_BOOTCOUNT_ADDR=0x5C00A14C +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x3 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MALLOC_F_LEN=0x3000 CONFIG_SYS_PBSIZE=1050 CONFIG_PREBOOT="run dh_preboot" diff --git a/doc/board/coolpi/genbook_cm5_rk3588.rst b/doc/board/coolpi/genbook_cm5_rk3588.rst index a02e561051a..cad2a28acbd 100644 --- a/doc/board/coolpi/genbook_cm5_rk3588.rst +++ b/doc/board/coolpi/genbook_cm5_rk3588.rst @@ -6,6 +6,7 @@ Cool Pi GenBook is a laptop powered by RK3588, it works with a carrier board connect with CM5. Specification: + * Rockchip RK3588 * LPDDR5X 8/32 GB * eMMC 64 GB @@ -24,11 +25,11 @@ Get the TF-A and DDR init (TPL) binaries .. prompt:: bash - > cd u-boot - > export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin - > export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.46.elf - > make coolpi-genbook-cm5-rk3588_defconfig - > make CROSS_COMPILE=aarch64-linux-gnu- + cd u-boot + export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.17.bin + export BL31=../rkbin/bin/rk35/rk3588_bl31_v1.46.elf + make coolpi-genbook-cm5-rk3588_defconfig + make CROSS_COMPILE=aarch64-linux-gnu- This will build ``u-boot-rockchip.bin`` for eMMC and ``u-boot-rockchip-spi.bin`` for SPI Nor. diff --git a/doc/board/kontron/sl28.rst b/doc/board/kontron/sl28.rst index 2cb8ec62be4..5d47ce6c158 100644 --- a/doc/board/kontron/sl28.rst +++ b/doc/board/kontron/sl28.rst @@ -65,12 +65,14 @@ wdt command flags The `wdt start` as well as the `wdt expire` command take a flags argument. The supported bitmask is as follows. -| Bit | Description | -| --- | ----------------------------- | -| 0 | Enable failsafe mode | -| 1 | Lock the control register | -| 2 | Disable board reset | -| 3 | Enable WDT_TIME_OUT# line | +=== ============================== +Bit Description +=== ============================== + 0 Enable failsafe mode + 1 Lock the control register + 2 Disable board reset + 3 Enable WDT_TIME_OUT# line +=== ============================== For example, you can use `wdt expire 1` to issue a reset and boot into the failsafe bootloader. diff --git a/doc/board/theobroma-systems/puma_rk3399.rst b/doc/board/theobroma-systems/puma_rk3399.rst index 5bc6385e451..a2a5e7bca4b 100644 --- a/doc/board/theobroma-systems/puma_rk3399.rst +++ b/doc/board/theobroma-systems/puma_rk3399.rst @@ -27,6 +27,7 @@ RK3399-Q7 features: * Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF) * NOR Flash: onboard SPI NOR * Companion Controller: onboard additional Cortex-M0 microcontroller + * RTC * fan controller * CAN diff --git a/doc/board/theobroma-systems/tiger_rk3588.rst b/doc/board/theobroma-systems/tiger_rk3588.rst index a73eec7fb9b..46112544c82 100644 --- a/doc/board/theobroma-systems/tiger_rk3588.rst +++ b/doc/board/theobroma-systems/tiger_rk3588.rst @@ -8,6 +8,7 @@ connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3588. It provides the following feature set: + * up to 16GB LPDDR4x * on-module eMMC * SD card (on a baseboard) via edge connector @@ -18,14 +19,20 @@ It provides the following feature set: * HDMI input over FPC connector * CAN * USB + - 1x USB 3.0 dual-role (direct connection) - 2x USB 3.0 host + 1x USB 2.0 host + * PCIe + - 1x PCIe 2.1 Gen3, 4 lanes - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes + * on-module ATtiny816 companion controller, implementing: + - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) + * on-module Secure Element with Global Platform 2.2.1 compliant JavaCard environment diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 9f9252b18d2..c0e394f77cc 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -75,7 +75,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2025.01-rc4 was released on Mon 09 December 2024. -.. * U-Boot v2025.01-rc5 was released on Mon 23 December 2024. +* U-Boot v2025.01-rc5 was released on Mon 23 December 2024. .. * U-Boot v2025.01-rc6 was released on Mon 30 December 2024. diff --git a/doc/develop/sending_patches.rst b/doc/develop/sending_patches.rst index e22b5e3e244..ee6e34089b5 100644 --- a/doc/develop/sending_patches.rst +++ b/doc/develop/sending_patches.rst @@ -377,7 +377,7 @@ The following are a "rule of thumb" as to how the states are used in patchwork today. Not all states are used by all custodians. * New: Patch has been submitted to the list, and none of the maintainers has - changed it's state since. + changed its state since. * Under Review: A custodian is reviewing the patch currently. diff --git a/doc/develop/uefi/fwu_updates.rst b/doc/develop/uefi/fwu_updates.rst index 51e8a28efe1..84713581459 100644 --- a/doc/develop/uefi/fwu_updates.rst +++ b/doc/develop/uefi/fwu_updates.rst @@ -170,7 +170,7 @@ build the tool, enable:: CONFIG_TOOLS_MKEFICAPSULE=y -Run the following commands to generate the accept/revert capsules:: +Run the following commands to generate the accept/revert capsules: .. code-block:: bash @@ -180,7 +180,7 @@ Run the following commands to generate the accept/revert capsules:: Some examples of using the mkeficapsule tool for generation of the -empty capsule would be:: +empty capsule would be: .. code-block:: bash diff --git a/doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt b/doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt deleted file mode 100644 index 0c2bf5eba43..00000000000 --- a/doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3188/RK3066 Clock and Reset Unit - -The RK3188/RK3066 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or - "rockchip,rk3066a-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3188-cru.h and -dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. -Similar macros exist for the reset sources in these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "xin27m" - 27mhz crystal input on rk3066 - optional, - - "ext_hsadc" - external HSADC clock - optional, - - "ext_cif0" - external camera clock - optional, - - "ext_rmii" - external RMII clock - optional, - - "ext_jtag" - externalJTAG clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt b/doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt deleted file mode 100644 index c9fbb76573e..00000000000 --- a/doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3288 Clock and Reset Unit - -The RK3288 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3288-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_hsadc" - external HSADC clock - optional, - - "ext_edp_24m" - external display port clock - optional, - - "ext_vip" - external VIP clock - optional, - - "ext_isp" - external ISP clock - optional, - - "ext_jtag" - external JTAG clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/doc/device-tree-bindings/clock/rockchip.txt b/doc/device-tree-bindings/clock/rockchip.txt deleted file mode 100644 index 22f6769e5d4..00000000000 --- a/doc/device-tree-bindings/clock/rockchip.txt +++ /dev/null @@ -1,77 +0,0 @@ -Device Tree Clock bindings for arch-rockchip - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -== Gate clocks == - -These bindings are deprecated! -Please use the soc specific CRU bindings instead. - -The gate registers form a continuos block which makes the dt node -structure a matter of taste, as either all gates can be put into -one gate clock spanning all registers or they can be divided into -the 10 individual gates containing 16 clocks each. -The code supports both approaches. - -Required properties: -- compatible : "rockchip,rk2928-gate-clk" -- reg : shall be the control register address(es) for the clock. -- #clock-cells : from common clock binding; shall be set to 1 -- clock-output-names : the corresponding gate names that the clock controls -- clocks : should contain the parent clock for each individual gate, - therefore the number of clocks elements should match the number of - clock-output-names - -Example using multiple gate clocks: - - clk_gates0: gate-clk@200000d0 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d0 0x4>; - clocks = <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>, - <&dummy>, <&dummy>; - - clock-output-names = - "gate_core_periph", "gate_cpu_gpll", - "gate_ddrphy", "gate_aclk_cpu", - "gate_hclk_cpu", "gate_pclk_cpu", - "gate_atclk_cpu", "gate_i2s0", - "gate_i2s0_frac", "gate_i2s1", - "gate_i2s1_frac", "gate_i2s2", - "gate_i2s2_frac", "gate_spdif", - "gate_spdif_frac", "gate_testclk"; - - #clock-cells = <1>; - }; - - clk_gates1: gate-clk@200000d4 { - compatible = "rockchip,rk2928-gate-clk"; - reg = <0x200000d4 0x4>; - clocks = <&xin24m>, <&xin24m>, - <&xin24m>, <&dummy>, - <&dummy>, <&xin24m>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>, - <&xin24m>, <&dummy>; - - clock-output-names = - "gate_timer0", "gate_timer1", - "gate_timer2", "gate_jtag", - "gate_aclk_lcdc1_src", "gate_otgphy0", - "gate_otgphy1", "gate_ddr_gpll", - "gate_uart0", "gate_frac_uart0", - "gate_uart1", "gate_frac_uart1", - "gate_uart2", "gate_frac_uart2", - "gate_uart3", "gate_frac_uart3"; - - #clock-cells = <1>; - }; diff --git a/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt b/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt deleted file mode 100644 index 388b213249f..00000000000 --- a/doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt +++ /dev/null @@ -1,157 +0,0 @@ -* Rockchip Pinmux Controller - -The Rockchip Pinmux Controller, enables the IC -to share one PAD to several functional blocks. The sharing is done by -multiplexing the PAD input/output signals. For each PAD there are several -muxing options with option 0 being the use as a GPIO. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The Rockchip pin configuration node is a node of a group of pins which can be -used for a specific device or function. This node represents both mux and -config of the pins in that group. The 'pins' selects the function mode(also -named pin mode) this pin can work on and the 'config' configures various pad -settings such as pull-up, etc. - -The pins are grouped into up to 5 individual pin banks which need to be -defined as gpio sub-nodes of the pinmux controller. - -Required properties for iomux controller: - - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" - "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" - "rockchip,rk3288-pinctrl" - - rockchip,grf: phandle referencing a syscon providing the - "general register files" - -Optional properties for iomux controller: - - rockchip,pmu: phandle referencing a syscon providing the pmu registers - as some SoCs carry parts of the iomux controller registers there. - Required for at least rk3188 and rk3288. - -Deprecated properties for iomux controller: - - reg: first element is the general register space of the iomux controller - It should be large enough to contain also separate pull registers. - second element is the separate pull register space of the rk3188. - Use rockchip,grf and rockchip,pmu described above instead. - -Required properties for gpio sub nodes: - - compatible: "rockchip,gpio-bank" - - reg: register of the gpio bank (different than the iomux registerset) - - interrupts: base interrupt of the gpio bank in the interrupt controller - - clocks: clock that drives this bank - - gpio-controller: identifies the node as a gpio controller and pin bank. - - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See generic - GPIO binding documentation for description of particular cells. - - interrupt-controller: identifies the controller node as interrupt-parent. - - #interrupt-cells: the value of this property should be 2 and the interrupt - cells should use the standard two-cell scheme described in - bindings/interrupt-controller/interrupts.txt - -Deprecated properties for gpio sub nodes: - - compatible: "rockchip,rk3188-gpio-bank0" - - reg: second element: separate pull register for rk3188 bank0, use - rockchip,pmu described above instead - -Required properties for pin configuration node: - - rockchip,pins: 3 integers array, represents a group of pins mux and config - setting. The format is rockchip,pins = . - The MUX 0 means gpio and MUX 1 to N mean the specific device function. - The phandle of a node containing the generic pinconfig options - to use, as described in pinctrl-bindings.txt in this directory. - -Examples: - -#include - -... - -pinctrl@20008000 { - compatible = "rockchip,rk3066a-pinctrl"; - rockchip,grf = <&grf>; - - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@20034000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20034000 0x100>; - interrupts = ; - clocks = <&clk_gates8 9>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - ... - - pcfg_pull_default: pcfg_pull_default { - bias-pull-pin-default - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = , - ; - }; - }; -}; - -uart2: serial@20064000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20064000 0x400>; - interrupts = ; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&mux_uart2>; - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; -}; - -Example for rk3188: - - pinctrl@20008000 { - compatible = "rockchip,rk3188-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@0x2000a000 { - compatible = "rockchip,rk3188-gpio-bank0"; - reg = <0x2000a000 0x100>; - interrupts = ; - clocks = <&clk_gates8 9>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@0x2003c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2003c000 0x100>; - interrupts = ; - clocks = <&clk_gates8 10>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - ... - - }; diff --git a/doc/device-tree-bindings/thermal/rockchip-thermal.txt b/doc/device-tree-bindings/thermal/rockchip-thermal.txt deleted file mode 100644 index ef802de4957..00000000000 --- a/doc/device-tree-bindings/thermal/rockchip-thermal.txt +++ /dev/null @@ -1,68 +0,0 @@ -* Temperature Sensor ADC (TSADC) on rockchip SoCs - -Required properties: -- compatible : "rockchip,rk3288-tsadc" -- reg : physical base address of the controller and length of memory mapped - region. -- interrupts : The interrupt number to the cpu. The interrupt specifier format - depends on the interrupt controller. -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for - the peripheral clock. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the name "tsadc-apb". -- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. -- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value. -- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO. -- rockchip,hw-tshut-polarity : The hardware-controlled active polarity 0:LOW - 1:HIGH. - -Exiample: -tsadc: tsadc@ff280000 { - compatible = "rockchip,rk3288-tsadc"; - reg = <0xff280000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "default"; - pinctrl-0 = <&otp_out>; - #thermal-sensor-cells = <1>; - rockchip,hw-tshut-temp = <95000>; - rockchip,hw-tshut-mode = <0>; - rockchip,hw-tshut-polarity = <0>; -}; - -Example: referring to thermal sensors: -thermal-zones { - cpu_thermal: cpu_thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tsadc 1>; - - trips { - cpu_alert0: cpu_alert { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; diff --git a/doc/device-tree-bindings/usb/dwc2.txt b/doc/device-tree-bindings/usb/dwc2.txt index 61493f7cb0c..7a533f65934 100644 --- a/doc/device-tree-bindings/usb/dwc2.txt +++ b/doc/device-tree-bindings/usb/dwc2.txt @@ -5,10 +5,6 @@ Required properties: - compatible : One of: - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC. - hisilicon,hi6220-usb: The DWC2 USB controller instance in the hi6220 SoC. - - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc; - - "rockchip,px30-usb", "rockchip,rk3066-usb", "snps,dwc2": for px30 Soc; - - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc; - - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc; - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs; - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs; - "amlogic,meson8-usb": The DWC2 USB controller instance in Amlogic Meson8 SoCs; diff --git a/doc/device-tree-bindings/video/rockchip-lvds.txt b/doc/device-tree-bindings/video/rockchip-lvds.txt deleted file mode 100644 index 7432e221669..00000000000 --- a/doc/device-tree-bindings/video/rockchip-lvds.txt +++ /dev/null @@ -1,77 +0,0 @@ -Rockchip LVDS interface ------------------- - -Required properties: -- compatible: "rockchip,rk3288-lvds"; - -- reg: physical base address of the controller and length - of memory mapped region. -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. -- clock-names: must contain "pclk_lvds" - -- rockchip,grf: phandle to the general register files syscon - -- rockchip,data-mapping: should be or , - This describes how the color bits are laid out in the - serialized LVDS signal. -- rockchip,data-width : should be <18> or <24>; -- rockchip,output: should be , or - , This describes the output face. - -- display-timings : described by - doc/device-tree-bindings/video/display-timing.txt. - -Example: - lvds: lvds@ff96c000 { - compatible = "rockchip,rk3288-lvds"; - reg = <0xff96c000 0x4000>; - clocks = <&cru PCLK_LVDS_PHY>; - clock-names = "pclk_lvds"; - pinctrl-names = "default"; - pinctrl-0 = <&lcdc0_ctl>; - rockchip,grf = <&grf>; - status = "disabled"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - lvds_in: port@0 { - reg = <0>; - - #address-cells = <1>; - #size-cells = <0>; - - lvds_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_lvds>; - }; - lvds_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_lvds>; - }; - }; - }; - }; - - &lvds { - rockchip,data-mapping = ; - rockchip,data-width = <24>; - rockchip,output = ; - rockchip,panel = <&panel>; - status = "okay"; - - display-timings { - timing@0 { - clock-frequency = <40000000>; - hactive = <1920>; - vactive = <1080>; - hsync-len = <44>; - hfront-porch = <88>; - hback-porch = <148>; - vfront-porch = <4>; - vback-porch = <36>; - vsync-len = <5>; - }; - }; - }; diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index 7bd9ffce8d8..30fc16794fc 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -499,12 +499,12 @@ Automatically updated variables ------------------------------- The following environment variables may be used and automatically -updated by the network boot commands ("bootp" and "rarpboot"), +updated by the network boot commands ("bootp", "dhcp" and "rarpboot"), depending the information provided by your boot server: -========= =================================================== +========== =================================================================== Variable Notes -========= =================================================== +========== =================================================================== bootfile see above dnsip IP address of your Domain Name Server dnsip2 IP address of your secondary Domain Name Server @@ -514,7 +514,10 @@ ipaddr See above netmask Subnet Mask rootpath Pathname of the root filesystem on the NFS server serverip see above -========= =================================================== +ipaddrN IP address for interface N (>0) (NET_LWIP dhcp only) +netmaskN Subnet mask for interface N (>0) (NET_LWIP dhcp only) +gatewayipN IP address of the Gateway for interface N (>0) (NET_LWIP dhcp only) +========== =================================================================== Special environment variables diff --git a/drivers/clk/mpc83xx_clk.h b/drivers/clk/mpc83xx_clk.h index c06a51ecd43..6b74fc5f16b 100644 --- a/drivers/clk/mpc83xx_clk.h +++ b/drivers/clk/mpc83xx_clk.h @@ -321,7 +321,7 @@ static inline u32 get_pci_sync_in(immap_t *im) } /** - * get_csb_clk() - Read the CSB (Coheren System Bus) clock speed + * get_csb_clk() - Read the CSB (Coherent System Bus) clock speed * @im: Pointer to the MPC83xx main register map in question * * Return: The CSB clock speed value as a 32-bit number. diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index a093027eb0e..12966d02a22 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -5,20 +5,20 @@ config CLK_RENESAS Enable support for clock present on Renesas SoCs. config CLK_RCAR - bool "Renesas RCar clock driver support" + bool "Renesas R-Car clock driver support" help - Enable common code for clocks on Renesas RCar SoCs. + Enable common code for clocks on Renesas R-Car SoCs. config CLK_RCAR_CPG_LIB bool "CPG/MSSR library functions" config CLK_RCAR_GEN2 - bool "Renesas RCar Gen2 clock driver" + bool "Renesas R-Car Gen2 clock driver" def_bool y if RCAR_32 depends on CLK_RENESAS select CLK_RCAR help - Enable this to support the clocks on Renesas RCar Gen2 SoC. + Enable this to support the clocks on Renesas R-Car Gen2 SoC. config CLK_R8A7790 bool "Renesas R8A7790 clock driver" @@ -51,14 +51,14 @@ config CLK_R8A7794 Enable this to support the clocks on Renesas R8A7794 SoC. config CLK_RCAR_GEN3 - bool "Renesas RCar Gen3 and Gen4 clock driver" + bool "Renesas R-Car Gen3 and Gen4 clock driver" def_bool y if RCAR_64 depends on CLK_RENESAS select CLK_RCAR select CLK_RCAR_CPG_LIB select DM_RESET help - Enable this to support the clocks on Renesas RCar Gen3 and Gen4 SoCs. + Enable this to support the clocks on Renesas R-Car Gen3 and Gen4 SoCs. config CLK_R8A774A1 bool "Renesas R8A774A1 clock driver" diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c index 89f2d966746..9b6fce4675c 100644 --- a/drivers/clk/renesas/clk-rcar-gen2.c +++ b/drivers/clk/renesas/clk-rcar-gen2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen2 CPG MSSR driver + * Renesas R-Car Gen2 CPG MSSR driver * * Copyright (C) 2017 Marek Vasut * diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index aa38c0f7dd0..375cc4a4930 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2017 Marek Vasut * diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 2e98e262fb0..70fa8ff2871 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -39,7 +39,6 @@ enum clk_ids { CLK_PLL6, CLK_PLL7, CLK_PLL1_DIV2, - CLK_PLL2_DIV2, CLK_PLL3_DIV2, CLK_PLL4_DIV2, CLK_PLL4_DIV5, @@ -82,7 +81,6 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { DEF_BASE(".pll7", CLK_PLL7, CLK_TYPE_GEN4_PLL7, CLK_MAIN), DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), - DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 2, 1), DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2, CLK_PLL4, 2, 1), DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5, CLK_PLL4, 5, 1), @@ -106,10 +104,10 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { DEF_RATE(".oco", CLK_OCO, 32768), /* Core Clock Outputs */ - DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 0), - DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 8), - DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 32), - DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2_DIV2, 2, 40), + DEF_GEN4_Z("zc0", R8A779H0_CLK_ZC0, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 0), + DEF_GEN4_Z("zc1", R8A779H0_CLK_ZC1, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 8), + DEF_GEN4_Z("zc2", R8A779H0_CLK_ZC2, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 32), + DEF_GEN4_Z("zc3", R8A779H0_CLK_ZC3, CLK_TYPE_GEN4_Z, CLK_PLL2, 4, 40), DEF_FIXED("s0d2", R8A779H0_CLK_S0D2, CLK_S0, 2, 1), DEF_FIXED("s0d3", R8A779H0_CLK_S0D3, CLK_S0, 3, 1), DEF_FIXED("s0d4", R8A779H0_CLK_S0D4, CLK_S0, 4, 1), diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c index 8862fbc7579..ea33bfd3239 100644 --- a/drivers/clk/renesas/rcar-cpg-lib.c +++ b/drivers/clk/renesas/rcar-cpg-lib.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2017 Marek Vasut * diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index 35bad7f5f73..39ff4541c1e 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2018 Marek Vasut * diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h index 71e409f3eb0..d5db14baf06 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.h +++ b/drivers/clk/renesas/renesas-cpg-mssr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Renesas RCar Gen3 CPG MSSR driver + * Renesas R-Car Gen3 CPG MSSR driver * * Copyright (C) 2017-2018 Marek Vasut * diff --git a/drivers/clk/tegra/tegra-car-clk.c b/drivers/clk/tegra/tegra-car-clk.c index 1d61f8dc378..880dd4f6ece 100644 --- a/drivers/clk/tegra/tegra-car-clk.c +++ b/drivers/clk/tegra/tegra-car-clk.c @@ -10,6 +10,9 @@ #include #include +#define TEGRA_CAR_CLK_PLL BIT(0) +#define TEGRA_CAR_CLK_PERIPH BIT(1) + static int tegra_car_clk_request(struct clk *clk) { debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, @@ -20,24 +23,41 @@ static int tegra_car_clk_request(struct clk *clk) * varies per SoC) are the peripheral clocks, which use a numbering * scheme that matches HW registers 1:1. There are other clock IDs * beyond this that are assigned arbitrarily by the Tegra CAR DT - * binding. Due to the implementation of this driver, it currently - * only supports the peripheral IDs. + * binding. */ - if (clk->id >= PERIPH_ID_COUNT) - return -EINVAL; + if (clk->id < PERIPH_ID_COUNT) { + clk->data |= TEGRA_CAR_CLK_PERIPH; + return 0; + } - return 0; + /* If check for periph failed, then check for PLL clock id */ + int id = clk_id_to_pll_id(clk->id); + + if (clock_id_is_pll(id)) { + clk->id = id; + clk->data |= TEGRA_CAR_CLK_PLL; + return 0; + } + + return -EINVAL; } static ulong tegra_car_clk_get_rate(struct clk *clk) { - enum clock_id parent; - debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, clk->id); - parent = clock_get_periph_parent(clk->id); - return clock_get_periph_rate(clk->id, parent); + if (clk->data & TEGRA_CAR_CLK_PLL) + return clock_get_rate(clk->id); + + if (clk->data & TEGRA_CAR_CLK_PERIPH) { + enum clock_id parent; + + parent = clock_get_periph_parent(clk->id); + return clock_get_periph_rate(clk->id, parent); + } + + return -1U; } static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate) @@ -47,6 +67,9 @@ static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate) debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate, clk->dev, clk->id); + if (clk->data & TEGRA_CAR_CLK_PLL) + return 0; + parent = clock_get_periph_parent(clk->id); return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL); } @@ -56,6 +79,9 @@ static int tegra_car_clk_enable(struct clk *clk) debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, clk->id); + if (clk->data & TEGRA_CAR_CLK_PLL) + return 0; + clock_enable(clk->id); return 0; @@ -66,6 +92,9 @@ static int tegra_car_clk_disable(struct clk *clk) debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, clk->id); + if (clk->data & TEGRA_CAR_CLK_PLL) + return 0; + clock_disable(clk->id); return 0; @@ -83,6 +112,9 @@ static int tegra_car_clk_probe(struct udevice *dev) { debug("%s(dev=%p)\n", __func__, dev); + clock_init(); + clock_verify(); + return 0; } diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 92a8597420a..f4a453e1cdd 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -358,10 +358,10 @@ config PCF8575_GPIO chips are from NXP and TI. config RCAR_GPIO - bool "Renesas RCar GPIO driver" + bool "Renesas R-Car GPIO driver" depends on DM_GPIO && ARCH_RENESAS help - This driver supports the GPIO banks on Renesas RCar SoCs. + This driver supports the GPIO banks on Renesas R-Car SoCs. config RZA1_GPIO bool "Renesas RZ/A1 GPIO driver" diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 52067fa7c1f..cdae6825736 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -504,16 +504,16 @@ config SYS_I2C_OMAP24XX Add support for the OMAP2+ I2C driver. config SYS_I2C_RCAR_I2C - bool "Renesas RCar I2C driver" + bool "Renesas R-Car I2C driver" depends on (RCAR_GEN2 || RCAR_64) && DM_I2C help - Support for Renesas RCar I2C controller. + Support for Renesas R-Car I2C controller. config SYS_I2C_RCAR_IIC - bool "Renesas RCar Gen3 IIC driver" + bool "Renesas R-Car Gen3 IIC driver" depends on (RCAR_GEN2 || RCAR_GEN3) && DM_I2C help - Support for Renesas RCar Gen3 IIC controller. + Support for Renesas R-Car Gen3 IIC controller. config SYS_I2C_ROCKCHIP bool "Rockchip I2C driver" diff --git a/drivers/i2c/rcar_iic.c b/drivers/i2c/rcar_iic.c index 2aa0f5fbfae..e019d06be41 100644 --- a/drivers/i2c/rcar_iic.c +++ b/drivers/i2c/rcar_iic.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar IIC driver + * Renesas R-Car IIC driver * * Copyright (C) 2017 Marek Vasut * diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index efe98354a0f..799586891af 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -750,7 +750,7 @@ static int mmc_send_op_cond(struct mmc *mmc) { int err, i; int timeout = 1000; - uint start; + ulong start; /* Some cards seem to need this */ mmc_go_idle(mmc); @@ -844,7 +844,8 @@ int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value, bool send_status) { - unsigned int status, start; + ulong start; + unsigned int status; struct mmc_cmd cmd; int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS; bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) && diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 92afa6adcda..556f07eaf8f 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -571,7 +571,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) int i, ret = 0, sret; u32 caps, reg; - /* Only supported on Renesas RCar */ + /* Only supported on Renesas R-Car */ if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS)) return -EINVAL; diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h index f489fb70766..657aba75148 100644 --- a/drivers/mmc/tmio-common.h +++ b/drivers/mmc/tmio-common.h @@ -64,7 +64,7 @@ #define TMIO_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ #define TMIO_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ #define TMIO_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */ -#define TMIO_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */ +#define TMIO_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (R-Car ver.) */ #define TMIO_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ #define TMIO_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ #define TMIO_SD_SIZE 0x04c /* block size */ @@ -90,7 +90,7 @@ #define TMIO_SD_VOLT_180 (2 << 0)/* 1.8V signal */ #define TMIO_SD_DMA_MODE 0x410 #define TMIO_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */ -#define TMIO_SD_DMA_MODE_BUS_WIDTH (BIT(5) | BIT(4)) /* RCar, 64bit */ +#define TMIO_SD_DMA_MODE_BUS_WIDTH (BIT(5) | BIT(4)) /* R-Car, 64bit */ #define TMIO_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */ #define TMIO_SD_DMA_CTL 0x414 #define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */ @@ -128,9 +128,9 @@ struct tmio_sd_priv { #define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ #define TMIO_SD_CAP_64BIT BIT(3) /* Controller is 64bit */ #define TMIO_SD_CAP_16BIT BIT(4) /* Controller is 16bit */ -#define TMIO_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas RCar version of IP */ -#define TMIO_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas RCar version of IP */ -#define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas RCar UHS/SDR modes */ +#define TMIO_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas R-Car version of IP */ +#define TMIO_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas R-Car version of IP */ +#define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas R-Car UHS/SDR modes */ #define TMIO_SD_CAP_RCAR \ (TMIO_SD_CAP_RCAR_GEN2 | TMIO_SD_CAP_RCAR_GEN3) struct udevice *vqmmc_dev; diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 678bbde89e6..c71c1e5547c 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -194,11 +194,11 @@ config ALTERA_QSPI "Embedded Peripherals IP User Guide" of Altera. config RENESAS_RPC_HF - bool "Renesas RCar Gen3 RPC HyperFlash driver" + bool "Renesas R-Car Gen3 RPC HyperFlash driver" depends on RCAR_GEN3 && DM_MTD help This enables access to HyperFlash memory through the Renesas - RCar Gen3 RPC controller. + R-Car Gen3 RPC controller. config HBMC_AM654 bool "HyperBus controller driver for AM65x SoC" diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c index 03545822b07..50a6191d9c2 100644 --- a/drivers/mtd/renesas_rpc_hf.c +++ b/drivers/mtd/renesas_rpc_hf.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen3 RPC HyperFlash driver + * Renesas R-Car Gen3 RPC HyperFlash driver * * Copyright (C) 2016 Renesas Electronics Corporation * Copyright (C) 2016 Cogent Embedded, Inc. diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index 8e1b6e2f6f6..57eff748c90 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -837,6 +837,7 @@ static int rswitch_send(struct udevice *dev, void *packet, int len) /* Update TX descriptor */ rswitch_flush_dcache((uintptr_t)packet, len); + rswitch_invalidate_dcache((uintptr_t)desc, sizeof(*desc)); memset(desc, 0x0, sizeof(*desc)); desc->die_dt = DT_FSINGLE; desc->info_ds = len; @@ -1112,6 +1113,9 @@ static int rswitch_bind(struct udevice *parent) return -ENOENT; ofnode_for_each_subnode(node, ports_np) { + if (!ofnode_is_enabled(node)) + continue; + ret = device_bind_with_driver_data(parent, drv, ofnode_get_name(node), (ulong)priv, node, &dev); diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 876a5fa57ee..41901433e8c 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -189,19 +189,19 @@ config PCI_MSC01 depends on TARGET_MALTA config PCI_RCAR_GEN2 - bool "Renesas RCar Gen2 PCIe driver" + bool "Renesas R-Car Gen2 PCIe driver" depends on RCAR_32 help Say Y here if you want to enable PCIe controller support on - Renesas RCar Gen2 SoCs. The PCIe controller on RCar Gen2 is + Renesas R-Car Gen2 SoCs. The PCIe controller on R-Car Gen2 is also used to access EHCI USB controller on the SoC. config PCI_RCAR_GEN3 - bool "Renesas RCar Gen3 PCIe driver" + bool "Renesas R-Car Gen3 PCIe driver" depends on RCAR_GEN3 help Say Y here if you want to enable PCIe controller support on - Renesas RCar Gen3 SoCs. + Renesas R-Car Gen3 SoCs. config PCI_SANDBOX bool "Sandbox PCI support" diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c index 12c31e74087..08d5c4fbb8b 100644 --- a/drivers/pci/pci-rcar-gen2.c +++ b/drivers/pci/pci-rcar-gen2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen2 PCIEC driver + * Renesas R-Car Gen2 PCIEC driver * * Copyright (C) 2018 Marek Vasut */ diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 76878246f1e..d4b4037ce19 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen3 PCIEC driver + * Renesas R-Car Gen3 PCIEC driver * * Copyright (C) 2018-2019 Marek Vasut * diff --git a/drivers/phy/phy-rcar-gen2.c b/drivers/phy/phy-rcar-gen2.c index f9428c7ad12..be736629d51 100644 --- a/drivers/phy/phy-rcar-gen2.c +++ b/drivers/phy/phy-rcar-gen2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen2 USB PHY driver + * Renesas R-Car Gen2 USB PHY driver * * Copyright (C) 2018 Marek Vasut */ diff --git a/drivers/phy/phy-rcar-gen3.c b/drivers/phy/phy-rcar-gen3.c index b278f995f37..8c004eaf4c6 100644 --- a/drivers/phy/phy-rcar-gen3.c +++ b/drivers/phy/phy-rcar-gen3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas RCar Gen3 USB PHY driver + * Renesas R-Car Gen3 USB PHY driver * * Copyright (C) 2018 Marek Vasut */ diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 7ced7d784b3..560f7275454 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -23,34 +23,34 @@ config PINCTRL_PFC_FULL U-Boot driver. config PINCTRL_PFC_R8A7790 - bool "Renesas RCar Gen2 R8A7790 pin control driver" + bool "Renesas R-Car Gen2 R8A7790 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7790 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7790 SoCs. config PINCTRL_PFC_R8A7791 - bool "Renesas RCar Gen2 R8A7791 pin control driver" + bool "Renesas R-Car Gen2 R8A7791 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7791 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7791 SoCs. config PINCTRL_PFC_R8A7792 - bool "Renesas RCar Gen2 R8A7792 pin control driver" + bool "Renesas R-Car Gen2 R8A7792 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7792 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7792 SoCs. config PINCTRL_PFC_R8A7793 - bool "Renesas RCar Gen2 R8A7793 pin control driver" + bool "Renesas R-Car Gen2 R8A7793 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7793 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7793 SoCs. config PINCTRL_PFC_R8A7794 - bool "Renesas RCar Gen2 R8A7794 pin control driver" + bool "Renesas R-Car Gen2 R8A7794 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen2 R8A7794 SoCs. + Support pin multiplexing control on Renesas R-Car Gen2 R8A7794 SoCs. config PINCTRL_PFC_R8A774A1 bool "Renesas RZ/G2 R8A774A1 pin control driver" @@ -77,76 +77,76 @@ config PINCTRL_PFC_R8A774E1 Support pin multiplexing control on Renesas RZ/G2H R8A774E1 SoCs. config PINCTRL_PFC_R8A77951 - bool "Renesas RCar Gen3 R8A7795 pin control driver" + bool "Renesas R-Car Gen3 R8A7795 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A7795 SoCs. config PINCTRL_PFC_R8A77960 - bool "Renesas RCar Gen3 R8A77960 pin control driver" + bool "Renesas R-Car Gen3 R8A77960 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77960 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77960 SoCs. config PINCTRL_PFC_R8A77961 - bool "Renesas RCar Gen3 R8A77961 pin control driver" + bool "Renesas R-Car Gen3 R8A77961 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77961 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77961 SoCs. config PINCTRL_PFC_R8A77965 - bool "Renesas RCar Gen3 R8A77965 pin control driver" + bool "Renesas R-Car Gen3 R8A77965 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77965 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77965 SoCs. config PINCTRL_PFC_R8A77970 - bool "Renesas RCar Gen3 R8A77970 pin control driver" + bool "Renesas R-Car Gen3 R8A77970 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77970 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77970 SoCs. config PINCTRL_PFC_R8A77980 - bool "Renesas RCar Gen3 R8A77980 pin control driver" + bool "Renesas R-Car Gen3 R8A77980 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77980 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77980 SoCs. config PINCTRL_PFC_R8A77990 - bool "Renesas RCar Gen3 R8A77990 pin control driver" + bool "Renesas R-Car Gen3 R8A77990 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77990 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77990 SoCs. config PINCTRL_PFC_R8A77995 - bool "Renesas RCar Gen3 R8A77995 pin control driver" + bool "Renesas R-Car Gen3 R8A77995 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A77995 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A77995 SoCs. config PINCTRL_PFC_R8A779A0 - bool "Renesas RCar Gen3 R8A779A0 pin control driver" + bool "Renesas R-Car Gen3 R8A779A0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A779A0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen3 R8A779A0 SoCs. config PINCTRL_PFC_R8A779F0 - bool "Renesas RCar Gen4 R8A779F0 pin control driver" + bool "Renesas R-Car Gen4 R8A779F0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen4 R8A779F0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen4 R8A779F0 SoCs. config PINCTRL_PFC_R8A779G0 - bool "Renesas RCar Gen4 R8A779G0 pin control driver" + bool "Renesas R-Car Gen4 R8A779G0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen4 R8A779G0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen4 R8A779G0 SoCs. config PINCTRL_PFC_R8A779H0 - bool "Renesas RCar Gen4 R8A779H0 pin control driver" + bool "Renesas R-Car Gen4 R8A779H0 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen4 R8A779H0 SoCs. + Support pin multiplexing control on Renesas R-Car Gen4 R8A779H0 SoCs. config PINCTRL_RZA1 bool "Renesas RZ/A1 R7S72100 pin control driver" diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 8b27ad9a77e..c4f4a8d78df 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -920,7 +920,7 @@ config SCIF_CONSOLE depends on SH || ARCH_RENESAS help Select this to enable Renesas SCIF UART. To operate serial ports - on systems with RCar or SH SoCs, say Y to this option. If unsure, + on systems with R-Car or SH SoCs, say Y to this option. If unsure, say N. choice diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index fd5cb3694f6..96ea033082b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -420,7 +420,7 @@ config RENESAS_RPC_SPI imply SPI_FLASH_SFDP_SUPPORT help Enable the Renesas RPC SPI driver, used to access SPI NOR flash - on Renesas RCar Gen3 SoCs. This uses driver model and requires a + on Renesas R-Car Gen3 SoCs. This uses driver model and requires a device tree binding to operate. config ROCKCHIP_SFC diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index f1e6f9f4e01..7103d786c7e 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Renesas RCar Gen3 RPC QSPI driver + * Renesas R-Car Gen3 RPC QSPI driver * * Copyright (C) 2018 Marek Vasut */ diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 010084ef7f3..c815764c2bc 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -115,10 +115,10 @@ config USB_GADGET_DWC2_OTG USB_GADGET to be enabled. config USB_RENESAS_USBHS - bool "Renesas RCar USB2.0 HS controller (gadget mode)" + bool "Renesas R-Car USB2.0 HS controller (gadget mode)" select USB_GADGET_DUALSPEED help - The Renesas Rcar USB 2.0 high-speed gadget controller + The Renesas R-Car USB 2.0 high-speed gadget controller integrated into Salvator and Kingfisher boards. Select this option if you want the driver to operate in Peripheral mode. This option requires USB_GADGET to be enabled. diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index bb5893d56db..24786a2bc91 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -103,12 +103,12 @@ config USB_XHCI_PCI Enables support for the PCI-based xHCI controller. config USB_XHCI_RCAR - bool "Renesas RCar USB 3.0 support" + bool "Renesas R-Car USB 3.0 support" default y depends on ARCH_RENESAS help Choose this option to add support for USB 3.0 driver on Renesas - RCar Gen3 SoCs. + R-Car Gen3 SoCs. config USB_XHCI_STI bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller" diff --git a/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h b/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h index 8db88f0dcfa..7c909b4697a 100644 --- a/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h +++ b/drivers/usb/host/xhci-rcar-r8a779x_usb3_v3.h @@ -1,5 +1,5 @@ /* - * Renesas RCar xHCI controller firmware version 3 + * Renesas R-Car xHCI controller firmware version 3 * * Copyright (c) 2014, Renesas Electronics Corporation * All rights reserved. diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c index 38c5928faed..b72807053c4 100644 --- a/drivers/usb/host/xhci-rcar.c +++ b/drivers/usb/host/xhci-rcar.c @@ -2,7 +2,7 @@ /* * Copyright (C) 2017 Marek Vasut * - * Renesas RCar USB HOST xHCI Controller + * Renesas R-Car USB HOST xHCI Controller */ #include diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c index 76abfeac443..52af23c3c83 100644 --- a/drivers/video/zynqmp/zynqmp_dpsub.c +++ b/drivers/video/zynqmp/zynqmp_dpsub.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -2093,10 +2094,15 @@ static int zynqmp_dpsub_probe(struct udevice *dev) { struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct zynqmp_dpsub_priv *priv = dev_get_priv(dev); + struct reset_ctl_bulk resets; struct clk clk; int ret; int mode = RGBA8888; + ret = reset_get_bulk(dev, &resets); + if (!ret) + reset_deassert_bulk(&resets); + ret = clk_get_by_name(dev, "dp_apb_clk", &clk); if (ret < 0) { dev_err(dev, "failed to get clock\n"); diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index d44ce45fd6b..9c869ee6840 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -53,6 +53,7 @@ #define CFG_EXTRA_ENV_SETTINGS \ "board=ls1028ardb\0" \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "fdtfile=fsl-ls1028a-rdb.dtb\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ "bootm_size=0x10000000\0" \ diff --git a/include/efi.h b/include/efi.h index c559fda3004..d50b3d3cec9 100644 --- a/include/efi.h +++ b/include/efi.h @@ -175,7 +175,7 @@ enum efi_allocate_type { EFI_ALLOCATE_MAX_ADDRESS, /** * @EFI_ALLOCATE_ADDRESS: - * Allocate a memory block starting at the indicatged adress. + * Allocate a memory block starting at the indicated address. */ EFI_ALLOCATE_ADDRESS, /** diff --git a/lib/lmb.c b/lib/lmb.c index b03237bc06c..a695edf70df 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -183,8 +183,10 @@ static long lmb_resize_regions(struct alist *lmb_rgn_lst, * the function might resize an already existing region or coalesce two * adjacent regions. * - * - * Returns: 0 if the region addition successful, -1 on failure + * Return: + * * %0 - Added successfully, or it's already added (only if LMB_NONE) + * * %-EEXIST - The region is already added, and flags != LMB_NONE + * * %-1 - Failure */ static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base, phys_size_t size, enum lmb_flags flags) @@ -217,17 +219,15 @@ static long lmb_add_region_flags(struct alist *lmb_rgn_lst, phys_addr_t base, coalesced++; break; } else if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) { - if (flags == LMB_NONE) { - ret = lmb_resize_regions(lmb_rgn_lst, i, base, - size); - if (ret < 0) - return -1; + if (flags != LMB_NONE) + return -EEXIST; - coalesced++; - break; - } else { + ret = lmb_resize_regions(lmb_rgn_lst, i, base, size); + if (ret < 0) return -1; - } + + coalesced++; + break; } } @@ -667,7 +667,7 @@ long lmb_add(phys_addr_t base, phys_size_t size) * * Free up a region of memory. * - * Return: 0 if successful, -1 on failure + * Return: 0 if successful, negative error code on failure */ long lmb_free_flags(phys_addr_t base, phys_size_t size, uint flags) @@ -818,7 +818,7 @@ static phys_addr_t _lmb_alloc_addr(phys_addr_t base, phys_size_t size, lmb_memory[rgn].size, base + size - 1, 1)) { /* ok, reserve the memory */ - if (lmb_reserve_flags(base, size, flags) >= 0) + if (!lmb_reserve_flags(base, size, flags)) return base; } } diff --git a/net/Kconfig b/net/Kconfig index b4bb68dd613..24508026200 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -90,7 +90,7 @@ config TFTP_WINDOWSIZE config TFTP_TSIZE bool "Track TFTP transfers based on file size option" depends on CMD_TFTPBOOT - default y if (ARCH_OMAP2PLUS || ARCH_K3) + default y if (ARCH_OMAP2PLUS || ARCH_K3 || ARCH_RENESAS) help By default, TFTP progress bar is increased for each received UDP frame, which can lead into long time being spent for sending diff --git a/net/lwip/dhcp.c b/net/lwip/dhcp.c index 9b882cf5b87..e7d9147455c 100644 --- a/net/lwip/dhcp.c +++ b/net/lwip/dhcp.c @@ -3,6 +3,7 @@ #include #include +#include #include #include #include @@ -112,10 +113,17 @@ static int dhcp_loop(struct udevice *udev) int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { int ret; + struct udevice *dev; eth_set_current(); - ret = dhcp_loop(eth_get_dev()); + dev = eth_get_dev(); + if (!dev) { + log_err("No network device\n"); + return CMD_RET_FAILURE; + } + + ret = dhcp_loop(dev); if (ret) return ret; diff --git a/net/lwip/dns.c b/net/lwip/dns.c index 4b937feaee1..1de63c9998b 100644 --- a/net/lwip/dns.c +++ b/net/lwip/dns.c @@ -56,7 +56,7 @@ static int dns_loop(struct udevice *udev, const char *name, const char *var) netif = net_lwip_new_netif(udev); if (!netif) - return -1; + return CMD_RET_FAILURE; dns_init(); diff --git a/test/lib/lmb.c b/test/lib/lmb.c index 0bd29e2a4fe..48c3c966f8f 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -754,7 +754,7 @@ static int lib_test_lmb_flags(struct unit_test_state *uts) /* reserve again, same flag */ ret = lmb_reserve_flags(0x40010000, 0x10000, LMB_NOMAP); - ut_asserteq(ret, -1L); + ut_asserteq(ret, -EEXIST); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, 0x40010000, 0x10000, 0, 0, 0, 0); diff --git a/test/py/conftest.py b/test/py/conftest.py index d9f074f3817..509d19b449d 100644 --- a/test/py/conftest.py +++ b/test/py/conftest.py @@ -144,6 +144,9 @@ def get_details(config): # Get a few provided parameters build_dir = config.getoption('build_dir') build_dir_extra = config.getoption('build_dir_extra') + + # The source tree must be the current directory + source_dir = os.path.dirname(os.path.dirname(TEST_PY_DIR)) if role: # When using a role, build_dir and build_dir_extra are normally not set, # since they are picked up from Labgrid-sjg via the u-boot-test-getrole @@ -172,15 +175,13 @@ def get_details(config): # Read the build directories here, in case none were provided in the # command-line arguments (board_type, board_type_extra, default_build_dir, - default_build_dir_extra, source_dir) = (vals['board'], - vals['board_extra'], vals['build_dir'], vals['build_dir_extra'], - vals['source_dir']) + default_build_dir_extra) = (vals['board'], + vals['board_extra'], vals['build_dir'], vals['build_dir_extra']) else: board_type = config.getoption('board_type') board_type_extra = config.getoption('board_type_extra') board_identity = config.getoption('board_identity') - source_dir = os.path.dirname(os.path.dirname(TEST_PY_DIR)) default_build_dir = source_dir + '/build-' + board_type default_build_dir_extra = source_dir + '/build-' + board_type_extra diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst index 83068ba6d39..780e9817fb6 100644 --- a/tools/binman/entries.rst +++ b/tools/binman/entries.rst @@ -197,7 +197,7 @@ source files that the tool examples: To run the tool:: - $ tools/binman/fip_util.py -s /path/to/trusted-firmware-a + $ tools/binman/fip_util.py -s /path/to/arm-trusted-firmware Warning: UUID 'UUID_NON_TRUSTED_WORLD_KEY_CERT' is not mentioned in tbbr_config.c file Existing code in 'tools/binman/fip_util.py' is up-to-date @@ -862,14 +862,18 @@ The top-level 'fit' node supports the following special properties: can be provided as a directory. Each .dtb file in the directory is processed, , e.g.:: - fit,fdt-list-dir = "arch/arm/dts + fit,fdt-list-dir = "arch/arm/dts"; + + In this case the input directories are ignored and all devicetree + files must be in that directory. fit,sign Enable signing FIT images via mkimage as described in - verified-boot.rst. If the property is found, the private keys path is - detected among binman include directories and passed to mkimage via - -k flag. All the keys required for signing FIT must be available at - time of signing and must be located in single include directory. + verified-boot.rst. If the property is found, the private keys path + is detected among binman include directories and passed to mkimage + via -k flag. All the keys required for signing FIT must be + available at time of signing and must be located in single include + directory. fit,encrypt Enable data encryption in FIT images via mkimage. If the property @@ -1010,7 +1014,8 @@ same approach can of course be used for SPL images. Note that the `of-spl-remove-props` entryarg can be used to indicate additional properties to remove. It is often used to remove properties like -`clock-names` and `pinctrl-names` which are not needed in SPL builds. +`clock-names` and `pinctrl-names` which are not needed in SPL builds. This +value is automatically passed to binman by the U-Boot build. See :ref:`fdtgrep_filter` for more information.