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7a4a07078b
This patch allocates level 0 GPT at the top of SRAM for FVP. This helps to meet L0 GPT alignment requirements and prevent the occurrence of possible unused gaps in SRAM. Load addresses for FVP TB_FW, SOC_FW and TOS_FW DTBs are defined in fvp_fw_config.dts via ARM_BL_RAM_BASE macro. Change-Id: Iaa52e302373779d9fdbaf4e1ba40c10aa8d1f8bd Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com> |
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|---|---|---|
| .. | ||
| aarch32 | ||
| aarch64 | ||
| fconf | ||
| fdts | ||
| include | ||
| sp_min | ||
| trp | ||
| tsp | ||
| fvp_bl1_measured_boot.c | ||
| fvp_bl1_setup.c | ||
| fvp_bl2_el3_setup.c | ||
| fvp_bl2_measured_boot.c | ||
| fvp_bl2_setup.c | ||
| fvp_bl2u_setup.c | ||
| fvp_bl31_setup.c | ||
| fvp_common.c | ||
| fvp_common_measured_boot.c | ||
| fvp_console.c | ||
| fvp_cpu_errata.mk | ||
| fvp_cpu_pwr.c | ||
| fvp_def.h | ||
| fvp_drtm_addr.c | ||
| fvp_drtm_dma_prot.c | ||
| fvp_drtm_err.c | ||
| fvp_drtm_measurement.c | ||
| fvp_drtm_stub.c | ||
| fvp_el3_spmc.c | ||
| fvp_el3_spmc_logical_sp.c | ||
| fvp_el3_token_sign.c | ||
| fvp_err.c | ||
| fvp_gicv3.c | ||
| fvp_io_storage.c | ||
| fvp_plat_attest_token.c | ||
| fvp_pm.c | ||
| fvp_private.h | ||
| fvp_realm_attest_key.c | ||
| fvp_security.c | ||
| fvp_spmd.c | ||
| fvp_spmd_logical_sp.c | ||
| fvp_stack_protector.c | ||
| fvp_sync_traps.c | ||
| fvp_topology.c | ||
| fvp_trusted_boot.c | ||
| jmptbl.i | ||
| jmptbl_mbedtls.i | ||
| platform.mk | ||