AlexeiFedorov 7a4a07078b feat(fvp): allocate L0 GPT at the top of SRAM ... This patch allocates level 0 GPT at the top of SRAM for FVP. This helps to meet L0 GPT alignment requirements and prevent the occurrence of possible unused gaps in SRAM. Load addresses for FVP TB_FW, SOC_FW and TOS_FW DTBs are defined in fvp_fw_config.dts via ARM_BL_RAM_BASE macro. Change-Id: Iaa52e302373779d9fdbaf4e1ba40c10aa8d1f8bd Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>		2025-02-11 15:10:49 +00:00
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a5ds	build: remove Windows compatibility layer	2025-01-14 16:21:51 +00:00
arm_fpga	perf(build): be clever about uppercasing	2024-11-08 12:27:46 +00:00
automotive_rd/platform/rd1ae	feat(rd1ae): add support for OP-TEE SPMC	2024-11-14 13:56:39 +00:00
common	fix(arm): create build directory before key generation	2025-02-03 09:37:50 +00:00
corstone700	build(bl32): added check for AARCH32_SP	2023-08-24 14:22:34 -05:00
corstone1000	fix(corstone-1000): fix Makefile error reporting	2024-08-27 10:39:41 +01:00
fvp	feat(fvp): allocate L0 GPT at the top of SRAM	2025-02-11 15:10:49 +00:00
fvp_r	fix(arm): add extra hash config to validate ROTPK	2024-09-09 11:22:28 +01:00
fvp_ve	feat(fvp): add flash areas for secure partition	2024-07-29 09:55:43 +01:00
juno	refactor(arm): rename ARM_ROTPK_HEADER_LEN	2024-12-30 12:32:34 +01:00
morello	fix(morello): remove stray white-space in 'morello/platform.mk'	2025-01-02 23:34:29 +01:00
n1sdp	refactor(arm): remove unused SP_MIN UART macros	2024-04-02 13:36:31 +01:00
neoverse_rd	feat(fvp): allocate L0 GPT at the top of SRAM	2025-02-11 15:10:49 +00:00
tc	Merge changes from topic "us_tc_trng" into integration	2025-02-04 13:19:10 +01:00