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feat(fvp): define single Root region

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For FVP model define single Root PAS which
includes EL3 DRAM data, L1 GPTs and SCP TZC.
This allows to decrease the number of PAS
regions passed to GPT library and use GPT
mapping with Contiguous descriptor of
larger block size.

Change-Id: I70f6babaebc14e5e0bce033783ec423c8a26c542
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
This commit is contained in:
AlexeiFedorov 2024-03-13 17:52:37 +00:00 • committed by Jean-Philippe Brucker
parent 0f38b9f87e
commit 665a8fdf3a
3 changed files with 27 additions and 20 deletions
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6
include/plat/arm/common/arm_def.h
View file

@ -20,7 +20,6 @@
* Definitions common to all ARM standard platforms
*****************************************************************************/
/* Special value used to verify platform parameters from BL2 to BL31 */
#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
@ -110,6 +109,7 @@
* placed here. 3MB region is reserved if RME is enabled, 2MB otherwise.
*/
#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */
/* 8 x 128KB L1 pages (GPCCR_PPS_64GB, GPCCR_PGS_4K) */
#define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */
/* 32MB - ARM_EL3_RMM_SHARED_SIZE */
#define ARM_REALM_SIZE (UL(0x02000000) - \
@ -150,7 +150,7 @@ MEASURED_BOOT
#endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */
#if ENABLE_RME
#define ARM_L1_GPT_BASE (ARM_DRAM1_BASE + \
#define ARM_L1_GPT_BASE (ARM_DRAM1_BASE + \
ARM_DRAM1_SIZE - \
ARM_L1_GPT_SIZE)
#define ARM_L1_GPT_END (ARM_L1_GPT_BASE + \
@ -546,7 +546,7 @@ MEASURED_BOOT
* configuration memory, 4KB aligned.
*/
#define ARM_L0_GPT_SIZE (PAGE_SIZE)
#define ARM_L0_GPT_BASE (ARM_FW_CONFIGS_LIMIT)
#define ARM_L0_GPT_BASE (ARM_FW_CONFIGS_LIMIT)
#define ARM_L0_GPT_LIMIT (ARM_L0_GPT_BASE + ARM_L0_GPT_SIZE)
#else
#define ARM_L0_GPT_SIZE U(0)

2
plat/arm/board/fvp/fvp_bl2_setup.c
View file

@ -30,7 +30,9 @@ static pas_region_t pas_regions[] = {
ARM_PAS_SECURE,
ARM_PAS_REALM,
ARM_PAS_EL3_DRAM,
#ifdef ARM_PAS_GPTS
ARM_PAS_GPTS,
#endif
ARM_PAS_KERNEL_1
};

39
plat/arm/board/fvp/include/fvp_pas_def.h
View file

@ -21,30 +21,27 @@
* ============================================================================
* 0GB | 1GB |L0 GPT|ANY |TBROM (EL3 code) |Fixed mapping
* | | | |TSRAM (EL3 data) |
* 00000000 | | | |IO (incl.UARTs & GIC) |
* 00000000 | 40000000 | | |IO (incl.UARTs & GIC) |
* ----------------------------------------------------------------------------
* 1GB | 1GB |L0 GPT|ANY |IO |Fixed mapping
* 40000000 | | | | |
* 40000000 | 40000000 | | | |
* ----------------------------------------------------------------------------
* 2GB |2GB-64MB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip
* 80000000 | | | | |
* 2GB | 2GB-64MB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip
* 80000000 | 7C000000 | | | |
* ----------------------------------------------------------------------------
* 4GB-64MB |64MB-32MB-4MB|L1 GPT|SECURE|DRAM TZC |Use T.Descrip
* FC000000 | | | | |
* FC000000 | 1C00000 | | | |
* ----------------------------------------------------------------------------
* 4GB-32MB | | | | |
* -3MB-1MB |32MB |L1 GPT|REALM |RMM |Use T.Descrip
* FDC00000 | | | | |
* -3MB-1MB | 32MB |L1 GPT|REALM |RMM |Use T.Descrip
* FDC00000 | 2000000 | | | |
* ----------------------------------------------------------------------------
* 4GB-3MB | | | | |
* -1MB |3MB |L1 GPT|ROOT |EL3 DRAM data |Use T.Descrip
* FFC00000 | | | | |
* -1MB | 4MB |L1 GPT|ROOT |EL3 DRAM data, L1 GPTs, |Use T.Descrip
* FFC00000 | 400000 | | |SCP TZC |
* ----------------------------------------------------------------------------
* 4GB-1MB |1MB |L1 GPT|ROOT |DRAM (L1 GPTs, SCP TZC) |Fixed mapping
* FFF00000 | | | | |
* ----------------------------------------------------------------------------
* 34GB |2GB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip
* 880000000| | | | |
* 34GB | 2GB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip
* 880000000| 80000000 | | | |
* ============================================================================
*
* - 4KB of L0 GPT reside in TSRAM, on top of the CONFIG section.
@ -61,7 +58,7 @@
/* Device memory 0 to 2GB */
#define ARM_PAS_1_BASE (U(0))
#define ARM_PAS_1_SIZE ((ULL(1) << 31)) /* 2GB */
#define ARM_PAS_1_SIZE (SZ_2G) /* 2GB */
/* NS memory 2GB to (end - 64MB) */
#define ARM_PAS_2_BASE (ARM_PAS_1_BASE + ARM_PAS_1_SIZE)
@ -77,7 +74,7 @@
/* NS memory 2GB */
#define ARM_PAS_4_BASE ARM_DRAM2_BASE
#define ARM_PAS_4_SIZE ((ULL(1) << 31)) /* 2GB */
#define ARM_PAS_4_SIZE (SZ_2G) /* 2GB */
#define ARM_PAS_GPI_ANY MAP_GPT_REGION(ARM_PAS_1_BASE, \
ARM_PAS_1_SIZE, \
@ -102,7 +99,8 @@
(ARM_PAS_SHARED_SIZE + \
ARM_REALM_SIZE), \
GPT_GPI_REALM)
/* Check if the EL3 TZC DRAM is contiguous with L1 GPT region. */
#if (ARM_L1_GPT_BASE != (ARM_EL3_TZC_DRAM1_BASE + ARM_EL3_TZC_DRAM1_SIZE))
#define ARM_PAS_EL3_DRAM GPT_MAP_REGION_GRANULE(ARM_EL3_TZC_DRAM1_BASE, \
ARM_EL3_TZC_DRAM1_SIZE, \
GPT_GPI_ROOT)
@ -110,6 +108,13 @@
#define ARM_PAS_GPTS GPT_MAP_REGION_GRANULE(ARM_L1_GPT_BASE, \
ARM_L1_GPT_SIZE, \
GPT_GPI_ROOT)
#else
/* Contiguous ROOT region */
#define ARM_PAS_EL3_DRAM GPT_MAP_REGION_GRANULE(ARM_EL3_TZC_DRAM1_BASE, \
ARM_EL3_TZC_DRAM1_SIZE + \
ARM_L1_GPT_SIZE, \
GPT_GPI_ROOT)
#endif
/* GPT Configuration options */
#define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS