mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 10:04:26 +00:00
742bf3ea23
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.
Testing was conducted by:
* Building for release with all errata flags enabled and running script
in change 19136 to compare output of objdump for each errata. Only
ERRATA_A75_764081 and ERRATA_A75_790748 could be verified this way,
rest had to be manually verified.
* Manual comparison of disassembly of converted functions with non-
converted functions
aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf
* Build for release with all errata flags enabled and run default tftf
tests
CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp HW_ASSISTED_COHERENCY=1 \
USE_COHERENT_MEM=0 CTX_INCLUDE_AARCH32_REGS=1 \
BL33=/home/katcap01/tf-a-tests/build/fvp/debug/tftf.bin \
ERRATA_A75_764081=1 ERRATA_A75_790748=1 WORKAROUND_CVE_2017_5715=1 \
WORKAROUND_CVE_2018_3639=1 \
ERRATA_DSU_798953=1 ERRATA_DSU_936184=1 \
WORKAROUND_CVE_2022_23960=1 \
fip all
* Build for debug with all errata enabled and step through ArmDS
at reset to ensure all functions are entered.
Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I0cd393db825fcb5c7ddea3aa2a5934ffc4b6046e
|
||
|---|---|---|
| .. | ||
| a64fx.S | ||
| aem_generic.S | ||
| cortex_a35.S | ||
| cortex_a53.S | ||
| cortex_a55.S | ||
| cortex_a57.S | ||
| cortex_a65.S | ||
| cortex_a65ae.S | ||
| cortex_a72.S | ||
| cortex_a73.S | ||
| cortex_a75.S | ||
| cortex_a75_pubsub.c | ||
| cortex_a76.S | ||
| cortex_a76ae.S | ||
| cortex_a77.S | ||
| cortex_a78.S | ||
| cortex_a78_ae.S | ||
| cortex_a78c.S | ||
| cortex_a510.S | ||
| cortex_a710.S | ||
| cortex_a715.S | ||
| cortex_blackhawk.S | ||
| cortex_chaberton.S | ||
| cortex_hayes.S | ||
| cortex_hunter.S | ||
| cortex_hunter_elp_arm.S | ||
| cortex_x1.S | ||
| cortex_x2.S | ||
| cortex_x3.S | ||
| cpu_helpers.S | ||
| cpuamu.c | ||
| cpuamu_helpers.S | ||
| denver.S | ||
| dsu_helpers.S | ||
| generic.S | ||
| neoverse_e1.S | ||
| neoverse_n1.S | ||
| neoverse_n1_pubsub.c | ||
| neoverse_n2.S | ||
| neoverse_n_common.S | ||
| neoverse_poseidon.S | ||
| neoverse_v1.S | ||
| neoverse_v2.S | ||
| qemu_max.S | ||
| rainier.S | ||
| wa_cve_2017_5715_bpiall.S | ||
| wa_cve_2017_5715_mmu.S | ||
| wa_cve_2022_23960_bhb.S | ||
| wa_cve_2022_23960_bhb_vector.S | ||