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fix(cpus): use hint instruction for "tsb csync"

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The "tsb csync" instruction is part of the Armv8.4 architecture
extension, and is not supported by many older assemblers.
We already cater for this in lib/extensions/trbe/trbe.c, where we use
the equivalent "hint #18" encoding for this, but use the new mnemonic
in the Cortex-A510 CPU support code.

Replace "tsb csync" with the hint encoding there as well, to support
building with older binutils versions.

Change-Id: Idf39f5c6c4dbf72802c3c120047b8bc499145e3b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Andre Przywara 2023-03-23 11:50:32 +00:00
parent b7253a14cd
commit 7a181b7d04
1 changed files with 5 additions and 1 deletions
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6
lib/cpus/aarch64/cortex_a510.S
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@ -382,7 +382,11 @@ func errata_cortex_a510_2684597_wa
bl check_errata_2684597
cbz x0, 2f
tsb csync
/*
* Many assemblers do not yet understand the "tsb csync" mnemonic,
* so use the equivalent hint instruction.
*/
hint #18 /* tsb csync */
2:
ret x17
endfunc errata_cortex_a510_2684597_wa