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refactor(amu): unify ENABLE_AMU and ENABLE_FEAT_AMUv1

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So far we have the ENABLE_AMU build option to include AMU register
handling code for enabling and context switch. There is also an
ENABLE_FEAT_AMUv1 option, solely to protect the HAFGRTR_EL2 system
register handling. The latter needs some alignment with the new feature
scheme, but it conceptually overlaps with the ENABLE_AMU option.

Since there is no real need for two separate options, unify both into a
new ENABLE_FEAT_AMU name in a first step. This is mostly just renaming at
this point, a subsequent patch will make use of the new feature handling
scheme.

Change-Id: I97d8a55bdee2ed1e1509fa9f2b09fd0bdd82736e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Andre Przywara 2023-03-21 13:53:19 +00:00 • committed by Manish Pandey
parent 82f5b5098b
commit d23acc9e4f
26 changed files with 36 additions and 48 deletions
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6
Makefile
View file

@ -1092,7 +1092,6 @@ $(eval $(call assert_booleans,\
DISABLE_MTPMU \
DYN_DISABLE_AUTH \
EL3_EXCEPTION_HANDLING \
ENABLE_AMU \
ENABLE_AMU_AUXILIARY_COUNTERS \
ENABLE_AMU_FCONF \
AMU_RESTRICT_COUNTERS \
@ -1172,7 +1171,7 @@ $(eval $(call assert_numerics,\
ENABLE_TRBE_FOR_NS \
ENABLE_BTI \
ENABLE_PAUTH \
ENABLE_FEAT_AMUv1 \
ENABLE_FEAT_AMU \
ENABLE_FEAT_AMUv1p1 \
ENABLE_FEAT_CSV2_2 \
ENABLE_FEAT_DIT \
@ -1229,7 +1228,7 @@ $(eval $(call add_defines,\
CTX_INCLUDE_NEVE_REGS \
DECRYPTION_SUPPORT_${DECRYPTION_SUPPORT} \
DISABLE_MTPMU \
ENABLE_AMU \
ENABLE_FEAT_AMU \
ENABLE_AMU_AUXILIARY_COUNTERS \
ENABLE_AMU_FCONF \
AMU_RESTRICT_COUNTERS \
@ -1310,7 +1309,6 @@ $(eval $(call add_defines,\
ENABLE_MPMM \
ENABLE_MPMM_FCONF \
ENABLE_FEAT_FGT \
ENABLE_FEAT_AMUv1 \
ENABLE_FEAT_ECV \
SIMICS_BUILD \
ENABLE_FEAT_AMUv1p1 \

2
bl31/bl31.mk
View file

@ -91,7 +91,7 @@ ifneq (${ENABLE_SPE_FOR_NS},0)
BL31_SOURCES += lib/extensions/spe/spe.c
endif
ifeq (${ENABLE_AMU},1)
ifneq (${ENABLE_FEAT_AMU},0)
BL31_SOURCES += ${AMU_SOURCES}
endif

2
bl32/sp_min/sp_min.mk
View file

@ -28,7 +28,7 @@ ifeq (${ENABLE_PMF}, 1)
BL32_SOURCES += lib/pmf/pmf_main.c
endif
ifeq (${ENABLE_AMU},1)
ifneq (${ENABLE_FEAT_AMU},0)
BL32_SOURCES += ${AMU_SOURCES}
endif

2
common/feat_detect.c
View file

@ -187,7 +187,7 @@ void detect_arch_features(void)
/* v8.4 features */
read_feat_dit();
check_feature(ENABLE_FEAT_AMUv1, read_feat_amu_id_field(),
check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(),
"AMUv1", 1, 2);
check_feature(ENABLE_MPAM_FOR_LOWER_ELS, read_feat_mpam_version(),
"MPAM", 1, 17);

6
docs/components/activity-monitors.rst
View file

@ -6,9 +6,9 @@ extension. This extension describes the architecture for the Activity Monitor
Unit (|AMU|), an optional non-invasive component for monitoring core events
through a set of 64-bit counters.
When the ``ENABLE_AMU=1`` build option is provided, Trusted Firmware-A sets up
the |AMU| prior to its exit from EL3, and will save and restore architected
|AMU| counters as necessary upon suspend and resume.
When the ``ENABLE_FEAT_AMU=1`` build option is provided, Trusted Firmware-A
sets up the |AMU| prior to its exit from EL3, and will save and restore
architected |AMU| counters as necessary upon suspend and resume.
.. _Activity Monitor Auxiliary Counters:

18
docs/getting_started/build-options.rst
View file

@ -230,11 +230,6 @@ Common build options
payload. Please refer to the "Booting an EL3 payload" section for more
details.
- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
This is an optional architectural feature available on v8.4 onwards. Some
v8.2 implementations also implement an AMU and this option can be used to
enable this feature on those systems as well. Default is 0.
- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters
(also known as group 1 counters). These are implementation-defined counters,
and as such require additional platform configuration. Default is 0.
@ -261,13 +256,12 @@ Common build options
builds, but this behaviour can be overridden in each platform's Makefile or
in the build command line.
- ``ENABLE_FEAT_AMUv1``: Numeric value to enable access to the HAFGRTR_EL2
(Hypervisor Activity Monitors Fine-Grained Read Trap Register) during EL2
to EL3 context save/restore operations. This flag can take the values 0 to 2,
to align with the ``FEATURE_DETECTION`` mechanism. It is an optional feature
available on v8.4 and onwards and must be set to either 1 or 2 alongside
``ENABLE_FEAT_FGT``, to access the HAFGRTR_EL2 register.
Default value is ``0``.
- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit
extensions. This flag can take the values 0 to 2, to align with the
``FEATURE_DETECTION`` mechanism. This is an optional architectural feature
available on v8.4 onwards. Some v8.2 implementations also implement an AMU
and this option can be used to enable this feature on those systems as well.
This flag can take the values 0 to 2, the default is 0.
- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1``
extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6

4
include/arch/aarch64/arch_features.h
View file

@ -244,11 +244,11 @@ static unsigned int read_feat_amu_id_field(void)
static inline bool is_feat_amu_supported(void)
{
if (ENABLE_FEAT_AMUv1 == FEAT_STATE_DISABLED) {
if (ENABLE_FEAT_AMU == FEAT_STATE_DISABLED) {
return false;
}
if (ENABLE_FEAT_AMUv1 == FEAT_STATE_ALWAYS) {
if (ENABLE_FEAT_AMU == FEAT_STATE_ALWAYS) {
return true;
}

2
lib/cpus/aarch64/cortex_a75.S
View file

@ -121,7 +121,7 @@ func cortex_a75_reset_func
bl errata_dsu_936184_wa
#endif
#if ENABLE_AMU
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT

2
lib/cpus/aarch64/cortex_a78.S
View file

@ -483,7 +483,7 @@ func cortex_a78_reset_func
bl errata_a78_2779479_wa
#endif
#if ENABLE_AMU
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT

2
lib/cpus/aarch64/cortex_a78_ae.S
View file

@ -214,7 +214,7 @@ func cortex_a78_ae_reset_func
bl errata_a78_ae_2395408_wa
#endif
#if ENABLE_AMU
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT

2
lib/cpus/aarch64/neoverse_n1.S
View file

@ -585,7 +585,7 @@ func neoverse_n1_reset_func
bl errata_n1_1946160_wa
#endif
#if ENABLE_AMU
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT

2
lib/cpus/aarch64/neoverse_n2.S
View file

@ -545,7 +545,7 @@ func neoverse_n2_reset_func
bl errata_n2_2388450_wa
#endif
#if ENABLE_AMU
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, cptr_el3
orr x0, x0, #TAM_BIT

2
lib/cpus/aarch64/rainier.S
View file

@ -94,7 +94,7 @@ func rainier_reset_func
bl errata_n1_1868343_wa
#endif
#if ENABLE_AMU
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
orr x0, x0, #RAINIER_ACTLR_AMEN_BIT

2
lib/el3_runtime/aarch32/context_mgmt.c
View file

@ -136,7 +136,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
static void enable_extensions_nonsecure(bool el2_unused)
{
#if IMAGE_BL32
#if ENABLE_AMU
#if ENABLE_FEAT_AMU
amu_enable(el2_unused);
#endif

2
lib/el3_runtime/aarch64/context_mgmt.c
View file

@ -485,7 +485,7 @@ static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx)
spe_enable(el2_unused);
}
#if ENABLE_AMU
#if ENABLE_FEAT_AMU
amu_enable(el2_unused, ctx);
#endif

4
lib/extensions/amu/amu.mk
View file

@ -10,8 +10,8 @@ AMU_SOURCES := lib/extensions/amu/${ARCH}/amu.c \
lib/extensions/amu/${ARCH}/amu_helpers.S
ifneq (${ENABLE_AMU_AUXILIARY_COUNTERS},0)
ifeq (${ENABLE_AMU},0)
$(error AMU auxiliary counter support (`ENABLE_AMU_AUXILIARY_COUNTERS`) requires AMU support (`ENABLE_AMU`))
ifeq (${ENABLE_FEAT_AMU},0)
$(error AMU auxiliary counter support (`ENABLE_AMU_AUXILIARY_COUNTERS`) requires AMU support (`ENABLE_FEAT_AMU`))
endif
endif

5
make_helpers/defaults.mk
View file

@ -133,9 +133,6 @@ ENABLE_BTI := 0
# Use BRANCH_PROTECTION to enable PAUTH.
ENABLE_PAUTH := 0
# Flag to enable access to the HAFGRTR_EL2 register
ENABLE_FEAT_AMUv1 := 0
# Flag to enable AMUv1p1 extension.
ENABLE_FEAT_AMUv1p1 := 0
@ -367,7 +364,7 @@ endif
# enabled at ELX.
CTX_INCLUDE_MTE_REGS := 0
ENABLE_AMU := 0
ENABLE_FEAT_AMU := 0
ENABLE_AMU_AUXILIARY_COUNTERS := 0
ENABLE_AMU_FCONF := 0
AMU_RESTRICT_COUNTERS := 0

2
plat/arm/board/arm_fpga/platform.mk
View file

@ -33,7 +33,7 @@ $(eval $(call add_define,FPGA_PRELOADED_DTB_BASE))
FPGA_PRELOADED_CMD_LINE := 0x1000
$(eval $(call add_define,FPGA_PRELOADED_CMD_LINE))
ENABLE_AMU := 1
ENABLE_FEAT_AMU := 2
# Treating this as a memory-constrained port for now
USE_COHERENT_MEM := 0

4
plat/arm/board/fvp/platform.mk
View file

@ -319,12 +319,12 @@ $(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG}))
endif
# Enable Activity Monitor Unit extensions by default
ENABLE_AMU := 1
ENABLE_FEAT_AMU := 2
# Enable dynamic mitigation support by default
DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
ifeq (${ENABLE_AMU},1)
ifneq (${ENABLE_FEAT_AMU},0)
BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \
lib/cpus/aarch64/cpuamu_helpers.S

2
plat/arm/board/fvp_r/platform.mk
View file

@ -69,7 +69,7 @@ FVP_R_BL_COMMON_SOURCES += drivers/delay_timer/generic_delay_timer.c
endif
# Enable Activity Monitor Unit extensions by default
ENABLE_AMU := 1
ENABLE_FEAT_AMU := 2
ifneq (${ENABLE_STACK_PROTECTOR},0)
FVP_R_BL_COMMON_SOURCES += plat/arm/board/fvp_r/fvp_r_stack_protector.c

2
plat/arm/board/rdn2/platform.mk
View file

@ -87,4 +87,4 @@ NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
override CTX_INCLUDE_AARCH32_REGS := 0
override ENABLE_AMU := 1
override ENABLE_FEAT_AMU := 1

2
plat/arm/board/rdv1/platform.mk
View file

@ -57,7 +57,7 @@ NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
override CTX_INCLUDE_AARCH32_REGS := 0
override ENABLE_AMU := 1
override ENABLE_FEAT_AMU := 1
ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
$(error "CSS_SGI_PLATFORM_VARIANT for RD-V1 should always be 0, \

2
plat/arm/board/rdv1mc/platform.mk
View file

@ -68,7 +68,7 @@ NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
override CTX_INCLUDE_AARCH32_REGS := 0
override ENABLE_AMU := 1
override ENABLE_FEAT_AMU := 1
ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
$(error "CSS_SGI_PLATFORM_VARIANT for RD-V1-MC should always be 0, \

2
plat/arm/board/tc/platform.mk
View file

@ -163,7 +163,7 @@ override CTX_INCLUDE_PAUTH_REGS := 1
override ENABLE_SPE_FOR_NS := 0
override ENABLE_AMU := 1
override ENABLE_FEAT_AMU := 1
override ENABLE_AMU_AUXILIARY_COUNTERS := 1
override ENABLE_AMU_FCONF := 1

2
plat/mediatek/common/common_config.mk
View file

@ -19,7 +19,7 @@ GIC_DEBUG := 0
ENABLE_STACK_PROTECTOR := strong
# AMU, Kernel will access amuserenr_el0 if PE supported
# Firmware _must_ implement AMU support
ENABLE_AMU := 1
ENABLE_FEAT_AMU := 2
VENDOR_EXTEND_PUBEVENT_ENABLE := 1
# MTK define options

1
plat/qti/msm8916/platform.mk
View file

@ -43,7 +43,6 @@ SEPARATE_CODE_AND_RODATA := 1
WARMBOOT_ENABLE_DCACHE_EARLY := 1
# Disable features unsupported in ARMv8.0
ENABLE_AMU := 0
ENABLE_SPE_FOR_NS := 0
ENABLE_SVE_FOR_NS := 0