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chore: rename Makalu to Cortex-A715
Change-Id: I017c955cb643e2befb6b01e1b5a07c22172b08b9 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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Harrison Mutai
parent
c0d8ee3861
commit
15889d1332
4 changed files with 40 additions and 40 deletions
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@ -1,26 +1,26 @@
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/*
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_MAKALU_H
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#define CORTEX_MAKALU_H
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#ifndef CORTEX_A715_H
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#define CORTEX_A715_H
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#define CORTEX_MAKALU_MIDR U(0x410FD4D0)
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#define CORTEX_A715_MIDR U(0x410FD4D0)
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/* Cortex Makalu loop count for CVE-2022-23960 mitigation */
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#define CORTEX_MAKALU_BHB_LOOP_COUNT U(38)
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/* Cortex-A715 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_A715_BHB_LOOP_COUNT U(38)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_MAKALU_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_MAKALU_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#endif /* CORTEX_MAKALU_H */
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#endif /* CORTEX_A715_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -7,23 +7,23 @@
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_makalu.h>
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#include <cortex_a715.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex Makalu must be compiled with HW_ASSISTED_COHERENCY enabled"
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#error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex Makalu supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_MAKALU_BHB_LOOP_COUNT, cortex_makalu
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wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715
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#endif /* WORKAROUND_CVE_2022_23960 */
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func check_errata_cve_2022_23960
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@ -35,44 +35,44 @@ func check_errata_cve_2022_23960
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ret
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endfunc check_errata_cve_2022_23960
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func cortex_makalu_reset_func
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func cortex_a715_reset_func
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/* Disable speculative loads */
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msr SSBS, xzr
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Cortex Makalu generic vectors are overridden to apply errata
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* The Cortex-A715 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_cortex_makalu
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adr x0, wa_cve_vbar_cortex_a715
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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isb
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ret
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endfunc cortex_makalu_reset_func
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endfunc cortex_a715_reset_func
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_makalu_core_pwr_dwn
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func cortex_a715_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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mrs x0, CORTEX_MAKALU_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_MAKALU_CPUPWRCTLR_EL1, x0
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mrs x0, CORTEX_A715_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_A715_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_makalu_core_pwr_dwn
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endfunc cortex_a715_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex Makalu. Must follow AAPCS.
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* Errata printing function for Cortex-A715. Must follow AAPCS.
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*/
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func cortex_makalu_errata_report
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func cortex_a715_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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@ -82,15 +82,15 @@ func cortex_makalu_errata_report
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata WORKAROUND_CVE_2022_23960, cortex_makalu, cve_2022_23960
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report_errata WORKAROUND_CVE_2022_23960, cortex_a715, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_makalu_errata_report
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endfunc cortex_a715_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides Cortex Makalu-specific
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* This function provides Cortex-A715 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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@ -98,16 +98,16 @@ endfunc cortex_makalu_errata_report
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_makalu_regs, "aS"
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cortex_makalu_regs: /* The ascii list of register names to be reported */
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.section .rodata.cortex_a715_regs, "aS"
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cortex_a715_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_makalu_cpu_reg_dump
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adr x6, cortex_makalu_regs
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mrs x8, CORTEX_MAKALU_CPUECTLR_EL1
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func cortex_a715_cpu_reg_dump
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adr x6, cortex_a715_regs
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mrs x8, CORTEX_A715_CPUECTLR_EL1
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ret
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endfunc cortex_makalu_cpu_reg_dump
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endfunc cortex_a715_cpu_reg_dump
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declare_cpu_ops cortex_makalu, CORTEX_MAKALU_MIDR, \
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cortex_makalu_reset_func, \
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cortex_makalu_core_pwr_dwn
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declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \
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cortex_a715_reset_func, \
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cortex_a715_core_pwr_dwn
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@ -25,7 +25,7 @@
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#include <cortex_a78.h>
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#include <cortex_a78_ae.h>
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#include <cortex_a78c.h>
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#include <cortex_makalu.h>
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#include <cortex_a715.h>
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#include <cortex_x1.h>
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#include <cortex_x2.h>
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#include <neoverse_n1.h>
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@ -406,7 +406,7 @@ struct em_cpu_list cpu_list[] = {
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#if CORTEX_A715_H_INC
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{
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.cpu_partnumber = CORTEX_MAKALU_MIDR,
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.cpu_partnumber = CORTEX_A715_MIDR,
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.cpu_errata_list = {
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[0] = {2701951, 0x00, 0x11, ERRATA_A715_2701951, \
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ERRATA_NON_ARM_INTERCONNECT},
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