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Merge "fix(zynqmp): handling of type el3 interrrupts" into integration
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commit
c0d8ee3861
3 changed files with 31 additions and 10 deletions
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@ -132,21 +132,29 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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}
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#if ZYNQMP_WDT_RESTART
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static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3];
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static zynmp_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3];
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int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
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{
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static uint32_t index;
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uint32_t i;
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/* Validate 'handler' and 'id' parameters */
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if (!handler || id >= MAX_INTR_EL3) {
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if (!handler || index >= MAX_INTR_EL3) {
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return -EINVAL;
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}
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/* Check if a handler has already been registered */
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if (type_el3_interrupt_table[id]) {
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return -EALREADY;
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for (i = 0; i < index; i++) {
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if (id == type_el3_interrupt_table[i].id) {
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return -EALREADY;
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}
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}
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type_el3_interrupt_table[id] = handler;
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type_el3_interrupt_table[index].id = id;
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type_el3_interrupt_table[index].handler = handler;
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index++;
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return 0;
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}
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@ -155,12 +163,19 @@ static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
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void *handle, void *cookie)
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{
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uint32_t intr_id;
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interrupt_type_handler_t handler;
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uint32_t i;
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interrupt_type_handler_t handler = NULL;
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intr_id = plat_ic_get_pending_interrupt_id();
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handler = type_el3_interrupt_table[intr_id];
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for (i = 0; i < MAX_INTR_EL3; i++) {
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if (intr_id == type_el3_interrupt_table[i].id) {
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handler = type_el3_interrupt_table[i].handler;
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}
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}
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if (handler != NULL) {
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handler(intr_id, flags, handle, cookie);
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return handler(intr_id, flags, handle, cookie);
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}
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return 0;
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -21,8 +22,12 @@ uint32_t zynqmp_calc_core_pos(u_register_t mpidr);
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uint32_t zynqmp_get_uart_clk(void);
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uint32_t zynqmp_get_bootmode(void);
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#if ZYNQMP_WDT_RESTART
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typedef struct zynqmp_intr_info_type_el3 {
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uint32_t id;
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interrupt_type_handler_t handler;
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} zynmp_intr_info_type_el3_t;
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/*
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* Register handler to specific GIC entrance
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* for INTR_TYPE_EL3 type of interrupt
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@ -135,7 +135,8 @@
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#define ARM_IRQ_SEC_SGI_6 14
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#define ARM_IRQ_SEC_SGI_7 15
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#define MAX_INTR_EL3 128
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/* number of interrupt handlers. increase as required */
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#define MAX_INTR_EL3 2
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/*******************************************************************************
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* UART related constants
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