Igor Podgainõi 58fadd62be fix: add support for 128-bit sysregs to EL3 crash handler ... The following changes have been made: * Add new sysreg definitions and ASM macro is_feat_sysreg128_present_asm * Add registers TTBR0_EL2 and VTTBR_EL2 to EL3 crash handler output * Use MRRS instead of MRS for registers TTBR0_EL1, TTBR0_EL2, TTBR1_EL1, VTTBR_EL2 and PAR_EL1 Change-Id: I0e20b2c35251f3afba2df794c1f8bc0c46c197ff Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>		2025-02-05 21:19:15 +01:00
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arch	fix: add support for 128-bit sysregs to EL3 crash handler	2025-02-05 21:19:15 +01:00
bl1	refactor(bl1): clean up bl2 layout calculation	2024-04-26 09:00:12 +00:00
bl2	BL2_AT_EL3: Enable pointer authentication support	2019-02-27 11:58:09 +00:00
bl2u	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
bl31	Merge "refactor(sdei): use common create_spsr() in SDEI library" into integration	2024-03-14 21:17:45 +01:00
bl32	feat(cm): test integrity of el1_ctx registers	2024-11-08 11:05:13 +00:00
common	feat(mbedtls): introduce crypto lib heap info struct	2024-12-18 14:48:24 +00:00
drivers	feat(s32g274a): split early clock initialization	2025-01-14 13:02:51 +02:00
dt-bindings	fix(dt-bindings): update STM32MP2 clock and reset bindings	2024-06-27 17:17:35 +02:00
export	feat(tbbr): add image id for backup GPT	2023-10-27 08:31:54 -05:00
lib	Merge changes from topic "us_tc_trng" into integration	2025-02-04 13:19:10 +01:00
plat	feat(handoff): common API for TPM event log handoff	2025-01-06 07:20:37 -08:00
services	fix(security): apply SMCCC_ARCH_WORKAROUND_4 to affected cpus	2025-01-30 16:45:35 -06:00
tools_share	fix(tc): add SCP_BL2 to RSE measured boot	2024-06-13 15:53:10 +02:00