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fix(security): apply SMCCC_ARCH_WORKAROUND_4 to affected cpus

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This patch implements SMCCC_ARCH_WORKAROUND_4 and
allows discovery through SMCCC_ARCH_FEATURES.
This mechanism is enabled if CVE_2024_7881 [1] is enabled
by the platform. If CVE_2024_7881 mitigation
is implemented, the discovery call returns 0,
if not -1 (SMC_ARCH_CALL_NOT_SUPPORTED).

For more information about SMCCC_ARCH_WORKAROUND_4 [2], please
refer to the SMCCC Specification reference provided below.

[1]: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-7881
[2]: https://developer.arm.com/documentation/den0028/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I1b1ffaa1f806f07472fd79d5525f81764d99bc79
This commit is contained in:
Arvind Ram Prakash 2025-01-28 17:21:17 -06:00
parent 4caef42a94
commit 8ae6b1ad6c
9 changed files with 85 additions and 8 deletions
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4
include/lib/cpus/errata.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -48,6 +48,8 @@ static inline bool errata_a75_764081_applies(void)
unsigned int check_if_affected_core(void);
#endif
int check_wa_cve_2024_7881(void);
/*
* NOTE that this structure will be different on AArch32 and AArch64. The
* uintptr_t will reflect the change and the alignment will be correct in both.

3
include/services/arm_arch_svc.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -14,6 +14,7 @@
#define SMCCC_ARCH_WORKAROUND_2 U(0x80007FFF)
#define SMCCC_ARCH_WORKAROUND_3 U(0x80003FFF)
#define SMCCC_ARCH_FEATURE_AVAILABILITY U(0x80000003)
#define SMCCC_ARCH_WORKAROUND_4 U(0x80000004)
#define SMCCC_GET_SOC_VERSION U(0)
#define SMCCC_GET_SOC_REVISION U(1)

6
lib/cpus/aarch64/cortex_x3.S
View file

@ -162,6 +162,10 @@ func cortex_x3_cpu_reg_dump
ret
endfunc cortex_x3_cpu_reg_dump
declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \
declare_cpu_ops_wa_4 cortex_x3, CORTEX_X3_MIDR, \
cortex_x3_reset_func, \
CPU_NO_EXTRA1_FUNC, \
CPU_NO_EXTRA2_FUNC, \
CPU_NO_EXTRA3_FUNC, \
check_erratum_cortex_x3_7881, \
cortex_x3_core_pwr_dwn

6
lib/cpus/aarch64/cortex_x4.S
View file

@ -160,6 +160,10 @@ func cortex_x4_cpu_reg_dump
ret
endfunc cortex_x4_cpu_reg_dump
declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \
declare_cpu_ops_wa_4 cortex_x4, CORTEX_X4_MIDR, \
cortex_x4_reset_func, \
CPU_NO_EXTRA1_FUNC, \
CPU_NO_EXTRA2_FUNC, \
CPU_NO_EXTRA3_FUNC, \
check_erratum_cortex_x4_7881, \
cortex_x4_core_pwr_dwn

6
lib/cpus/aarch64/cortex_x925.S
View file

@ -77,6 +77,10 @@ func cortex_x925_cpu_reg_dump
ret
endfunc cortex_x925_cpu_reg_dump
declare_cpu_ops cortex_x925, CORTEX_X925_MIDR, \
declare_cpu_ops_wa_4 cortex_x925, CORTEX_X925_MIDR, \
cortex_x925_reset_func, \
CPU_NO_EXTRA1_FUNC, \
CPU_NO_EXTRA2_FUNC, \
CPU_NO_EXTRA3_FUNC, \
check_erratum_cortex_x925_7881, \
cortex_x925_core_pwr_dwn

37
lib/cpus/aarch64/cpu_helpers.S
View file

@ -326,6 +326,43 @@ func check_wa_cve_2017_5715
ret
endfunc check_wa_cve_2017_5715
/*
* int check_wa_cve_2024_7881(void);
*
* This function returns:
* - ERRATA_APPLIES when firmware mitigation is required.
* - ERRATA_NOT_APPLIES when firmware mitigation is _not_ required.
* - ERRATA_MISSING when firmware mitigation would be required but
* is not compiled in.
*
* NOTE: Must be called only after cpu_ops have been initialized
* in per-CPU data.
*/
.globl check_wa_cve_2024_7881
func check_wa_cve_2024_7881
mrs x0, tpidr_el3
#if ENABLE_ASSERTIONS
cmp x0, #0
ASM_ASSERT(ne)
#endif
ldr x0, [x0, #CPU_DATA_CPU_OPS_PTR]
#if ENABLE_ASSERTIONS
cmp x0, #0
ASM_ASSERT(ne)
#endif
ldr x0, [x0, #CPU_EXTRA4_FUNC]
/*
* If the reserved function pointer is NULL, this CPU
* is unaffected by CVE-2024-7881 so bail out.
*/
cmp x0, #CPU_NO_EXTRA4_FUNC
beq 1f
br x0
1:
mov x0, #ERRATA_NOT_APPLIES
ret
endfunc check_wa_cve_2024_7881
/*
* void *wa_cve_2018_3639_get_disable_ptr(void);
*

6
lib/cpus/aarch64/neoverse_v2.S
View file

@ -153,6 +153,10 @@ func neoverse_v2_cpu_reg_dump
ret
endfunc neoverse_v2_cpu_reg_dump
declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \
declare_cpu_ops_wa_4 neoverse_v2, NEOVERSE_V2_MIDR, \
neoverse_v2_reset_func, \
CPU_NO_EXTRA1_FUNC, \
CPU_NO_EXTRA2_FUNC, \
CPU_NO_EXTRA3_FUNC, \
check_erratum_neoverse_v2_7881, \
neoverse_v2_core_pwr_dwn

6
lib/cpus/aarch64/neoverse_v3.S
View file

@ -101,6 +101,10 @@ declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \
neoverse_v3_reset_func, \
neoverse_v3_core_pwr_dwn
declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \
declare_cpu_ops_wa_4 neoverse_v3, NEOVERSE_V3_MIDR, \
neoverse_v3_reset_func, \
CPU_NO_EXTRA1_FUNC, \
CPU_NO_EXTRA2_FUNC, \
CPU_NO_EXTRA3_FUNC, \
check_erratum_neoverse_v3_7881, \
neoverse_v3_core_pwr_dwn

19
services/arm_arch_svc/arm_arch_svc_setup.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -99,6 +99,14 @@ static int32_t smccc_arch_features(u_register_t arg1)
return SMC_ARCH_CALL_SUCCESS;
#endif /* ARCH_FEATURE_AVAILABILITY */
#if WORKAROUND_CVE_2024_7881
case SMCCC_ARCH_WORKAROUND_4:
if (check_wa_cve_2024_7881() != ERRATA_APPLIES) {
return SMC_ARCH_CALL_NOT_SUPPORTED;
}
return 0;
#endif /* WORKAROUND_CVE_2024_7881 */
#endif /* __aarch64__ */
/* Fallthrough */
@ -254,6 +262,15 @@ static uintptr_t arm_arch_svc_smc_handler(uint32_t smc_fid,
*/
SMC_RET0(handle);
#endif
#if WORKAROUND_CVE_2024_7881
case SMCCC_ARCH_WORKAROUND_4:
/*
* The workaround has already been applied on affected PEs
* during cold boot. This function has no effect whether PE is
* affected or not.
*/
SMC_RET0(handle);
#endif /* WORKAROUND_CVE_2024_7881 */
#endif /* __aarch64__ */
#if ARCH_FEATURE_AVAILABILITY
/* return is 64 bit so only reply on SMC64 requests */