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fix(dt-bindings): update STM32MP2 clock and reset bindings
Fix some clocks and reset binding values. Change-Id: Ibe480aa77cd0abb63d08bbee08ad4ec9d5d2a397 Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
This commit is contained in:
Gabriel Fernandez
Yann Gautier
parent
d91d10ab39
commit
85229098ab
3 changed files with 34 additions and 31 deletions
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@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
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/*
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* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
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* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
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* Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
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* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
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*/
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#ifndef _DT_BINDINGS_STM32MP25_CLKS_H_
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@ -109,7 +109,7 @@
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/* LOW SPEED MCU CLOCK */
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#define CK_ICN_LS_MCU 88
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#define CK_BUS_STM500 89
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#define CK_BUS_STM 89
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#define CK_BUS_FMC 90
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#define CK_BUS_GPU 91
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#define CK_BUS_ETH1 92
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@ -233,7 +233,6 @@
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#define CK_BUS_DDRCFG 210
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#define CK_BUS_GICV2M 211
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#define CK_BUS_USBTC 212
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#define CK_BUS_BUSPERFM 213
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#define CK_BUS_USB3PCIEPHY 214
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#define CK_BUS_STGEN 215
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#define CK_BUS_VDEC 216
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@ -272,7 +271,7 @@
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#define CK_BUS_RISAF4 249
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#define CK_BUS_USB2OHCI 250
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#define CK_BUS_USB2EHCI 251
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#define CK_BUS_USB3DRD 252
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#define CK_BUS_USB3DR 252
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#define CK_KER_LPTIM1 253
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#define CK_KER_LPTIM2 254
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#define CK_KER_USART2 255
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@ -364,8 +363,10 @@
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#define CK_BUS_ETHSWACMCFG 341
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#define CK_BUS_ETHSWACMMSG 342
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#define HSE_DIV2_CK 343
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#define CK_KER_ETR 344
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#define CK_KER_STM 345
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#define STM32MP25_LAST_CLK 344
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#define STM32MP25_LAST_CLK 346
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#define CK_SCMI_ICN_HS_MCU 0
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#define CK_SCMI_ICN_SDMMC 1
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@ -453,8 +454,7 @@
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#define CK_SCMI_TIMG2 83
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#define CK_SCMI_BKPSRAM 84
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#define CK_SCMI_BSEC 85
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#define CK_SCMI_BUSPERFM 86
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#define CK_SCMI_ETR 87
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#define CK_SCMI_BUS_ETR 87
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#define CK_SCMI_FMC 88
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#define CK_SCMI_GPIOA 89
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#define CK_SCMI_GPIOB 90
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@ -489,6 +489,8 @@
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#define CK_SCMI_SYSDBG 119
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#define CK_SCMI_SYSATB 120
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#define CK_SCMI_TSDBG 121
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#define CK_SCMI_STM500 122
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#define CK_SCMI_BUS_STM 122
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#define CK_SCMI_KER_STM 123
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#define CK_SCMI_KER_ETR 124
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#endif /* _DT_BINDINGS_STM32MP25_CLKS_H_ */
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
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/*
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* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
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* Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
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*/
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#ifndef _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_
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@ -108,9 +108,8 @@
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#define MUX_DSIPHY 18
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#define MUX_LVDSPHY 19
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#define MUX_DTS 20
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#define MUX_CPU1 21
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#define MUX_D3PER 22
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#define MUX_NB 23
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#define MUX_D3PER 21
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#define MUX_NB 22
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#define MUXSEL_HSI 0
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#define MUXSEL_HSE 1
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@ -144,7 +143,7 @@
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#define MUX_USB3PCIEPHY_FLEX34 0x0
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#define MUX_USB3PCIEPHY_HSE 0x1
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#define MUX_DSIBLANE_FLEX28 0x0
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#define MUX_DSIBLANE_DSIPHY 0x0
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#define MUX_DSIBLANE_FLEX27 0x1
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#define MUX_DSIPHY_FLEX28 0x0
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@ -219,8 +218,8 @@
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/* define for st,drive */
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#define LSEDRV_LOWEST 0
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#define LSEDRV_MEDIUM_LOW 1
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#define LSEDRV_MEDIUM_HIGH 2
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#define LSEDRV_MEDIUM_LOW 2
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#define LSEDRV_MEDIUM_HIGH 1
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#define LSEDRV_HIGHEST 3
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#endif /* _DT_BINDINGS_CLOCK_STM32MP25_CLKSRC_H_ */
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */
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/*
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* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
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* Copyright (C) 2023-2024, STMicroelectronics - All Rights Reserved
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* Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
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*/
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@ -14,16 +14,16 @@
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#define C2_R 8288
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#define C2_HOLDBOOT_R 8608
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#define C1_HOLDBOOT_R 8609
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#define VSW_R 8703
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#define C1MS_R 8808
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#define IWDG2_KER_R 9074
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#define IWDG4_KER_R 9202
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#define C3_R 9312
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#define DDRCP_R 9856
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#define DDRCAPB_R 9888
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#define DDRPHYCAPB_R 9920
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#define DDRCFG_R 9984
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#define DDR_R 10016
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#define VSW_R 8735
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#define C1MS_R 8840
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#define IWDG2_KER_R 9106
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#define IWDG4_KER_R 9234
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#define C3_R 9344
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#define DDRCP_R 9888
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#define DDRCAPB_R 9920
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#define DDRPHYCAPB_R 9952
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#define DDRCFG_R 10016
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#define DDR_R 10048
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#define OSPI1_R 10400
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#define OSPI1DLL_R 10416
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#define OSPI2_R 10432
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@ -115,7 +115,7 @@
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#define USB2_R 16352
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#define USB2PHY1_R 16384
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#define USB2PHY2_R 16416
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#define USB3DRD_R 16448
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#define USB3DR_R 16448
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#define USB3PCIEPHY_R 16480
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#define PCIE_R 16512
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#define USBTC_R 16544
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@ -143,7 +143,6 @@
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#define CRYP2_R 17440
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#define WWDG1_R 17632
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#define WWDG2_R 17664
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#define BUSPERFM_R 17696
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#define VREF_R 17728
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#define DTS_R 17760
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#define CRC_R 17824
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@ -159,6 +158,9 @@
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#define RST_SCMI_C1_HOLDBOOT_R 2
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#define RST_SCMI_C2_HOLDBOOT_R 3
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#define RST_SCMI_FMC 4
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#define RST_SCMI_PCIE 5
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#define RST_SCMI_OSPI1 5
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#define RST_SCMI_OSPI1DLL 6
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#define RST_SCMI_OSPI2 7
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#define RST_SCMI_OSPI2DLL 8
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#endif /* _DT_BINDINGS_STM32MP25_RESET_H_ */
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