arm-trusted-firmware/include/lib/cpus/aarch64
Boyan Karatotev 3f4c1e1e7b feat(cpus): add a concise way to implement AArch64 errata
Errata implementation involves adding a lot of boilerplate to random
places with just conventions on how to do them. Copy pasting is the
usual method for doing this. The result is an error-prone and verbose
patch that is a nightmare to get through review.

Errata workarounds have a very large degree of similarity - most of them
involve setting a bit at reset. As such most of the boilerplate is not
strictly necessary. To solve this, add a collection of assembly macros
to wrap errata implementations such that only the actual mitigations
need to be written. A new erratum mitigation looks something like:

  workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769
    sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8
  workaround_reset_end cortex_a77, ERRATUM(1925769)

  check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1)

Note, that the long comment on every mitigation is missing. This is on
purpose, as this new format includes all of its contents into an easily
readable format.

The workaround wrappers add an erratum entry (24 bytes) to a per-cpu
data structure which can then be read by a standard reset function to
apply all errata automatically. This has the added benefit of collecting
all errata TF-A knows about in a central way, which was previously
missing. This can then be used at runtime with the errata ABI.

If an erratum doesn't fit this standard definition (eg. the
CVE_2022_23960), it can progressively be unwrapped to the old
convention. The only differences are that the naming format is slightly
more verbose and a call to add_erratum_entry is needed to inform the
framework about the errata.

Finally, the internal workaround names change a tiny bit, especially
CVEs.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iac644f85dcf85b8279b25e83baf1e7d08b253b16
2023-05-30 09:31:15 +01:00
..
a64fx.h feat(cpus): add a64fx cpu to tf-a 2022-07-07 07:17:25 +09:00
aem_generic.h cpus: Add casts to all definitions in CPU headers 2019-02-11 13:34:57 +00:00
cortex_a35.h Cortex-A35: Implement workaround for errata 855472 2019-04-17 13:46:43 +01:00
cortex_a53.h feat(cpu/cortex_a53): add L1PCTL macro definiton for CPUACTLR_EL1 2022-01-13 18:00:46 +08:00
cortex_a55.h Cortex-A55: workarounds for errata 1221012 2019-05-28 14:19:04 +01:00
cortex_a57.h cpus: higher performance non-cacheable load forwarding 2020-02-20 09:25:45 -08:00
cortex_a65.h Introducing support for Cortex-A65 2019-10-02 18:12:28 +02:00
cortex_a65ae.h Introducing support for Cortex-A65AE 2019-10-03 15:38:31 +02:00
cortex_a72.h feat(ti): set snoop-delayed exclusive handling on A72 cores 2023-01-12 18:42:57 -06:00
cortex_a73.h Replace deprecated __ASSEMBLY__ macro with __ASSEMBLER__ 2019-10-11 14:12:24 +02:00
cortex_a75.h Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ 2019-08-01 13:14:12 -07:00
cortex_a76.h fix(security): loop workaround for CVE-2022-23960 for Cortex-A76 2022-03-11 00:48:03 -06:00
cortex_a76ae.h fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C 2022-03-21 08:57:09 -05:00
cortex_a77.h revert(cpus): "Revert workaround for A77 erratum 1800714" 2022-10-11 09:34:05 +01:00
cortex_a78.h fix(cpus): workaround for Cortex-A78 erratum 2742426 2023-03-08 14:58:05 -06:00
cortex_a78_ae.h fix(errata): workaround for Cortex A78 AE erratum 2395408 2022-03-24 10:55:48 +00:00
cortex_a78c.h fix(cpus): workaround for Cortex-A78C erratum 1827430 2023-03-21 16:14:41 -05:00
cortex_a510.h fix(cpus): workaround for Cortex-A510 erratum 2666669 2022-10-13 16:19:50 -05:00
cortex_a710.h fix(cpus): workaround for Cortex-A710 erratum 2291219 2022-10-27 13:46:52 +01:00
cortex_blackhawk.h feat(cpus): add support for blackhawk cpu 2023-04-04 17:16:53 +02:00
cortex_chaberton.h feat(cpus): add support for chaberton cpu 2023-04-04 17:16:46 +02:00
cortex_hayes.h feat(cpu): add support for Hayes CPU 2021-09-30 19:30:39 +02:00
cortex_hunter.h fix(security): workaround for CVE-2022-23960 2022-05-11 19:05:48 +02:00
cortex_hunter_elp_arm.h feat(cpu): add library support for Hunter ELP 2022-10-07 12:44:04 +01:00
cortex_makalu.h fix(security): workaround for CVE-2022-23960 2022-05-11 19:05:48 +02:00
cortex_x1.h fix(security): workaround for CVE-2022-23960 for Cortex-X1 2022-05-11 15:24:37 +02:00
cortex_x2.h fix(errata): workaround for Cortex-X2 erratum 2371105 2022-07-21 14:26:59 -05:00
cortex_x3.h fix(cpus): workaround for Cortex-X3 erratum 2615812 2022-11-17 09:41:40 +00:00
cpu_macros.S feat(cpus): add a concise way to implement AArch64 errata 2023-05-30 09:31:15 +01:00
cpuamu.h Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ 2019-08-01 13:14:12 -07:00
denver.h lib: cpus: denver: add MIDR PN9 variant 2020-08-31 10:43:44 -07:00
dsu_def.h fix(errata): workaround for DSU-110 erratum 2313941 2022-05-11 19:05:36 +02:00
generic.h fix(tree): correct some typos 2023-05-09 15:57:12 +01:00
neoverse_e1.h Fix wrong MIDR_EL1 value for Neoverse E1 2019-03-15 15:40:27 +00:00
neoverse_n1.h fix(security): workaround for CVE-2022-23960 2022-03-10 23:57:14 -06:00
neoverse_n2.h fix(cpus): workaround for Neoverse-N2 erratum 2326639 2022-10-27 13:46:52 +01:00
neoverse_n_common.h Add support for Neoverse-N2 CPUs. 2020-11-30 19:12:56 +00:00
neoverse_poseidon.h fix(security): workaround for CVE-2022-23960 2022-05-11 19:05:48 +02:00
neoverse_v1.h fix(cpus): workaround for Neoverse V1 errata 2743233 2023-03-09 14:09:37 -06:00
neoverse_v2.h refactor(cpu): use the updated IP name for Demeter CPU 2022-10-03 15:31:40 +05:30
qemu_max.h Add support for QEMU "max" CPU 2021-04-13 12:31:40 +01:00
rainier.h lib/cpus: update MIDR value for rainier cpu 2020-10-09 10:43:13 +00:00