Commit graph

2455 commits

Author SHA1 Message Date
Manish Pandey
49c7a26419 Merge changes from topic "mb/mb-design" into integration
* changes:
  docs: remove redundant Measured Boot interface info
  docs: add Measured Boot design
2023-07-10 14:03:12 +02:00
Olivier Deprez
e318411f02 Merge "docs: add guidelines for abandoning patches" into integration 2023-07-07 12:10:48 +02:00
Manish V Badarkhe
a1c93550bc docs: remove redundant Measured Boot interface info
A separate design document for Measured Boot covers the porting
guidelines for the Measured Boot interfaces. As a result,
the Measured Boot interfaces have been removed from the porting
guide and a link to the Measured Boot design document has been
provided.

Change-Id: Ia6bd2620d830aea6aececab4af7e10a6d737f025
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-07-06 12:14:38 +01:00
Manish V Badarkhe
5038f1f90e docs: add Measured Boot design
Added design document for Measured Boot implementation in
TF-A.

Change-Id: I25b57ec555b289eb6bbf0a6aae014d7bf6d152fd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-07-06 12:14:30 +01:00
Manish V Badarkhe
8671000ff7 docs: add guidelines for abandoning patches
The code review guidelines have been updated to explain when
patches that do not receive a response to the review comments
will be abandoned.

Change-Id: I60539e16ca41245cf1b352f24557be1b3c67c367
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-07-06 11:20:28 +01:00
Jacky Bai
c190f3ed6c docs(maintainers): add maintainers for i.MX9 SoCs
Add maintainers for NXP i.MX9 SoC family.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I6dd694af56da9f4d241fda28b781254586b5f462
2023-06-30 10:24:05 +08:00
Jacky Bai
c472b7502e docs(imx9): add imx93 platform
Add i.MX9 platform introduction.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ic07ca394cff6a9e3e21b7a03f9c9080d3c1ef91a
2023-06-30 10:24:05 +08:00
Madhukar Pappireddy
e87102f32b Merge changes from topic "gr/cpu_rename" into integration
* changes:
  chore: rename hayes to a520
  chore: rename hunter to a720
  chore: rename hunter_elp to cortex-x4
2023-06-29 17:36:44 +02:00
Govindraj Raja
dea3d71e9a chore: rename hayes to a520
Rename Cortex-hayes to Cortes-A520

Change-Id: Ic574b55b1aaf11b5bf7b583e244245e7b54bdb22
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-06-29 17:20:17 +02:00
Govindraj Raja
31b3945527 chore: rename hunter to a720
Rename cortex_hunter to cortex_a720

Change-Id: Id4e0e2cd47051c2e92b3f16373ea06ef4df1d75f
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-06-29 16:20:01 +01:00
Boyan Karatotev
83a4dae1af refactor(pmu): convert FEAT_MTPMU to C and move to persistent register init
The FEAT_MTPMU feature disable runs very early after reset. This means,
it needs to be written in assembly, since the C runtime has not been
initialised yet.

However, there is no need for it to be initialised so soon. The PMU
state is only relevant after TF-A has relinquished control. The code
to do this is also very verbose and difficult to read. Delaying the
initialisation allows for it to happen with the rest of the PMU. Align
with FEAT_STATE in the process.

BREAKING CHANGE: This patch explicitly breaks the EL2 entry path. It is
currently unsupported.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2aa659d026fbdb75152469f6d19812ece3488c6f
2023-06-29 09:59:06 +01:00
Olivier Deprez
448d4d97aa Merge "docs: remove deprecated tc0 from list of supported FVPs" into integration 2023-06-28 15:44:31 +02:00
Manish V Badarkhe
acd03f4b75 docs: move common build option from Arm-specific to common file
Moved common build options from Arm-specific file to common build
file.

Change-Id: If74b6223972ae3a6c11d9f9d2fbd8d2ee008b6e5
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-06-27 12:47:28 +01:00
Manish Pandey
3995f30c55 Merge "refactor(build): merge march32/64 directives" into integration 2023-06-27 10:19:56 +02:00
Manish V Badarkhe
059b19bd44 Merge "docs: move the Juno-specific build option to Arm build option file" into integration 2023-06-23 16:01:50 +02:00
Manish V Badarkhe
e8947b27fe Merge "feat(fvp): allow configurable FVP Trusted SRAM size" into integration 2023-06-23 16:01:09 +02:00
Daniel Boulby
fa07049ee7 docs: remove deprecated tc0 from list of supported FVPs
TC0 is now a deprecated platform so remove it from the list
of supported FVPs as well as throwing an error if it is attempted
to be built.

Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: Id013fcecbe20700611463ef9eab8cb3ae09071cc
2023-06-23 11:46:06 +01:00
Govindraj Raja
d4089fb8d8 refactor(build): merge march32/64 directives
Both march32-directive and march64-directive eventually generate the
same march option that will passed to compiler.

Merge this two separate directives to a common one as march-directive.

Change-Id: I220d2b782eb3b54e13ffd5b6a581d0e6da68756a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2023-06-22 16:37:03 -05:00
Manish V Badarkhe
31df063281 docs: move the Juno-specific build option to Arm build option file
Moved the Juno-specific build option from the common build option
file to the Arm build option file.

Change-Id: I0f53203f0cfca4a3baadab2cee4339c9694cfe8b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-06-22 16:00:32 +02:00
Chris Kay
41e56f422d feat(fvp): allow configurable FVP Trusted SRAM size
In some build configurations TF-A can exceed the existing 256KB SRAM,
triggering a build failure. More recent versions of the base FVP allow
you to configure a larger Trusted SRAM of 512KB.

This change introduces the `FVP_TRUSTED_SRAM_SIZE` build option, which
allows you to explicitly specify how much of the Trusted SRAM to
utilise, e.g.:

    FVP_TRUSTED_SRAM_SIZE=384

This allows previously-failing configurations to build successfully by
utilising more than the originally-allocated 256KB of the Trusted SRAM
while maintaining compatibility with older configurations/models that
only require/have 256KB.

Change-Id: I8344d3718564cd2bd53f1e6860e2fe341ae240b0
Signed-off-by: Chris Kay <chris.kay@arm.com>
2023-06-21 14:16:11 +02:00
Stephan Gerhold
b4e49e3fe4 docs(msm8916): document new build options
Update the MSM8916 platform documentation with the new build options
introduced in the previous changes:

  - AArch32 (BL32/SP_MIN)
  - UART selection

While at it, also document the build options that allow changing the
memory addresses (PRELOADED_BL33_BASE, BL31_BASE, BL32_BASE).

Change-Id: I2370c8264982317693f69fda0b03a255f12bafe2
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2023-06-20 18:52:53 +02:00
Manish Pandey
bf1e58e737 Merge "docs: update PSCI reference" into integration 2023-06-16 10:44:39 +02:00
Lauren Wehrmeister
aa1055e300 Merge "fix(cpus): reduce generic_errata_report()'s size" into integration 2023-06-15 19:07:36 +02:00
Lauren Wehrmeister
d2e0743698 Merge changes from topic "bk/errata_refactor" into integration
* changes:
  feat(cpus): add more errata framework helpers
  docs: document the errata framework
2023-06-15 16:28:41 +02:00
Boyan Karatotev
f43e09a12e fix(cpus): reduce generic_errata_report()'s size
For a pretty implementation and straightforward code, the CVE/erratum
dispatching of the errata status reporting was done with a macro,
closely following the old code. Unfortunately, this produces a function
that was over a kilobyte in size, which unsurprisingly doesn't fit on
some platforms.

Convert the macro to a proper C function and call it once. Also hide the
errata ordering checking behind the FEATURE_DETECTION flag to further
save space. This functionality is not necessary for most builds.
Development and platform bringup builds, which should find this
functionality useful, are expected to have FEATURE_DETECTION enabled.

This reduces the function to under 600 bytes.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ibf5376a26cbae28d9dc010128452cb3c694a3f78
2023-06-15 10:14:59 +01:00
Boyan Karatotev
6a0e8e80fb docs: document the errata framework
Also add a recommended Procedure Call Standard (PCS) to use inside CPU
files and split everything into sections to make it easier to follow.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Idd876d8e598b5dfe1193aa3e7375c52f6edf5671
2023-06-15 10:14:58 +01:00
Manish V Badarkhe
032c698350 Merge "feat(ast2700): add Aspeed AST2700 platform support" into integration 2023-06-15 10:57:58 +02:00
Manish V Badarkhe
3be6b4fbe5 docs: update PSCI reference
PSCI specification reference in the documentation is updated
to point to latest specification and duplicate PSCI references are
removed.

Change-Id: I35ee365f08c557f3017af4d51f6d063a7501b27e
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-06-15 09:46:43 +01:00
Lauren Wehrmeister
0484b2cb9c Merge "docs: update Measured Boot PoC" into integration 2023-06-12 18:23:37 +02:00
Sandrine Bailleux
7ae96dcebd Merge "chore(bl): add UNALIGNED symbols for TEXT/RODATA" into integration 2023-06-12 14:43:17 +02:00
Manish V Badarkhe
7a8a97f582 Merge changes from topics "hm/latex", "hm/latexpdf" into integration
* changes:
  fix(docs): fix build errors for latexpdf
  chore: reformat sphinx configuration
2023-06-12 13:49:19 +02:00
Michal Simek
f7d445fcbb chore(bl): add UNALIGNED symbols for TEXT/RODATA
Add symbols to mark end of TEXT/RODATA before page alignment.
Similar change was done by commit 8d69a03f6a ("Various
improvements/cleanups on the linker scripts") for
RO_END/COHERENT_RAM. These symbols help to know how much free
space is in the final binary because of page alignment.

Also show all *UNALIGNED__ symbols via poetry.
For example:
poetry run memory -p zynqmp -b debug

Change-Id: I322beba37dad76be9f4e88ca7e5b3eff2df7d96e
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-06-12 12:50:08 +02:00
Harrison Mutai
443d6ea699 fix(docs): fix build errors for latexpdf
Fixes errors encountered when handling SVG graphics, unicode characters,
and deeply nested lists (i.e. in the change log) with the `latexpdf`
docs build. Adds `sphinxcontrib-svg2pdfconverter` to allow embedding SVG
images into PDF files; changes the LaTeX engine to XeLaTex to provide
wider support for unicode characters (see [1] for more details); and
increases the maximum list depth.

[1] https://www.sphinx-doc.org/en/master/usage/configuration.html#confval-latex_engine

Change-Id: I2ee265d301f6822bae7aa6dfa3a8bfcf070076d3
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-06-12 10:56:30 +01:00
Manish Pandey
f4d011b0f0 Merge changes from topic "psci-osi" into integration
* changes:
  fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
  fix(sc7280): update pwr_domain_suspend
  fix(fvp): update pwr_domain_suspend
2023-06-12 10:22:50 +02:00
Manish V Badarkhe
30ee1b065d docs: update Measured Boot PoC
Updated the Measured Boot PoC to be compliant with the current TF-A
implementation that supports multiple Measured Boot backends, which
are the RSS and Event Log.

Change-Id: I8a38a801dd75e6282d103e154966959bba2d1ec7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2023-06-12 09:08:48 +01:00
Chia-Wei Wang
85f199b774 feat(ast2700): add Aspeed AST2700 platform support
Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the documents.

Change-Id: I1796f7aae5ed2d1799e91fabb8949607959cd9b3
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2023-06-12 10:28:21 +08:00
Manish V Badarkhe
919e25e9e3 Merge "docs: add detail to assembly language guideline" into integration 2023-06-08 11:50:12 +02:00
Sandrine Bailleux
1b4d99878c Merge "fix(doc): match boot-order size to implementation" into integration 2023-06-08 08:30:40 +02:00
Manish Pandey
f6bf4d6bc8 Merge changes from topic "hm/memmap-feat" into integration
* changes:
  feat(memmap): add topological memory view
  feat(memmap): add tabular memory use data
2023-06-07 17:48:14 +02:00
Olivier Deprez
ab23061eb0 Merge changes from topic "bk/clearups" into integration
* changes:
  chore(rme): add make rule for SPD=spmd
  chore(bl1): remove redundant bl1_arch_next_el_setup
  chore(docs): remove control register setup section
  chore(pauth): remove redundant pauth_disable_el3() call
2023-06-07 10:13:17 +02:00
Sandrine Bailleux
8dadc1e2a6 chore(fconf): rename last occurences of set_fw_config_info()
set_fw_config_info() interface got renamed into set_config_info() as
part of commit f441718936 ("lib/fconf:
Update 'set_fw_config_info' function"). Rename a few left-overs of the
old name.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I119719cd7f3ba544e0c4c438e5341d35c7b5bdc2
2023-06-06 14:38:34 +02:00
Boyan Karatotev
2ce78bff8b docs: add detail to assembly language guideline
Assembly language is rarely required and when it is, there are a lot of
helpers available to reduce the amount needed. Update the guidelines to
give pointers to them.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ic484e4ba57242594c351a9185ecb625d6e5dc223
2023-06-05 13:33:41 +01:00
Harrison Mutai
29b11baf6b chore: reformat sphinx configuration
Format the configuration file to follow our coding guidelines and common
Python style conventions.

Change-Id: Ic83372287db08df0662f562f7683a02ddff0bac8
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2023-06-05 12:30:39 +01:00
Sandrine Bailleux
9b5c0fcdba Merge changes from topic "hm/memmap-feat" into integration
* changes:
  build(bl32): add symbols for memory layout
  build(bl31): add symbols for memory layout
  build(bl2): add symbols for memory layout
  build(bl1): add symbols for memory layout
  refactor: improve readability of symbol table
2023-06-01 14:36:46 +02:00
Sandrine Bailleux
0df5cf1893 docs: clarify maintainers election process
Add a new page in TF-A documentation for clarifying the process to
elect a new maintainer. This builds on top of the Trusted Firmware
process [1], with the following TF-A specific details:

 - Must have contributed to the project for at least a couple of years.
 - Must dedicate at least 2 hours a week for maintainer duties.
 - Details about the election process. In particular, setting a
   one-calendar-week deadline for other maintainers to raise
   objections.

[1] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Ibef08bbbd4d18cd7aea13e01ba570972a7ee808d
2023-06-01 13:41:09 +02:00
Sandrine Bailleux
ca4febac0c docs: consolidate code review process documentation
From the page listing the maintainers and code owners [1], add a link
to the code review guidelines page [2], which in turn has a link to
the tf.org code review process [3].

Before that patch, both pages [1] and [2] had a link to
[3]. Hopefully, this change will guide the reader better so they don't
miss out on any information.

Additionally, move some of the information from the top of page [1]
into page [2] and add extra details about the code review process used
in TF-A and how that get translated in Gerrit.

[1] https://trustedfirmware-a.readthedocs.io/en/latest/about/maintainers.html
[2] https://trustedfirmware-a.readthedocs.io/en/latest/process/code-review-guidelines.html
[3] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I56562a72443f03fff16077dadc411ef4ee78666d
2023-06-01 13:41:09 +02:00
Wing Li
d34886140c fix(psci): add optional pwr_domain_validate_suspend to plat_psci_ops_t
This patch adds a new optional member `pwr_domain_validate_suspend` to
the `plat_psci_ops_t` structure that allows a platform to optionally
perform platform specific validations in OS-initiated mode. This is
conditionally compiled into the build depending on the value of the
`PSCI_OS_INIT_MODE` build option.

In https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/17682,
the return type of the `pwr_domain_suspend` handler was updated from
`void` to `int` to allow a platform to optionally perform platform
specific validations in OS-initiated mode. However, when an error code
other than `PSCI_E_SUCCESS` is returned, the current exit path does not
undo the operations in `psci_suspend_to_pwrdown_start`, and as a result,
the system ends up in an unexpected state.

The fix in this patch prevents the need to undo the operations in
`psci_suspend_to_pwrdown_start`, by allowing the platform to first
perform any necessary platform specific validations before the PSCI
generic code proceeds to the point of no return where the CPU_SUSPEND
request is expected to complete successfully.

Change-Id: I05d92c7ea3f5364da09af630d44d78252185db20
Signed-off-by: Wing Li <wingers@google.com>
2023-05-31 23:54:19 -07:00
Madhukar Pappireddy
3f52d599f4 Merge "docs: fix syntax error in note" into integration 2023-05-30 15:08:09 +02:00
Soby Mathew
b709f12db3 Merge "feat(rme): save PAuth context when RME is enabled" into integration 2023-05-24 14:23:38 +02:00
Shruti Gupta
13cc1aa70a feat(rme): save PAuth context when RME is enabled
This patch enables CTX_INCLUDE_PAUTH_REGS for RME builds.
The RMM-EL3 specification is also updated to reflect the changes
and also version of the same is bumped from 0.1 to 0.2.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I2e96a592d2b75abaee24294240c1727c5ceba420
2023-05-24 10:56:40 +01:00