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feat(ast2700): add Aspeed AST2700 platform support

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Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the documents.

Change-Id: I1796f7aae5ed2d1799e91fabb8949607959cd9b3
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
This commit is contained in:
Chia-Wei Wang 2022-11-02 17:50:21 +08:00
parent 9b5c0fcdba
commit 85f199b774
12 changed files with 445 additions and 0 deletions
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7
changelog.yaml
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@ -244,6 +244,13 @@ subsections:
- title: Corstone-1000
scope: corstone-1000
- title: Aspeed
scope: aspeed
subsections:
- title: AST2700
scope: ast2700
- title: Broadcom
scope: brcm

11
docs/about/maintainers.rst
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@ -527,6 +527,15 @@ Arm Total Compute platform port
:|G|: `rupsin01`_
:|F|: plat/arm/board/tc
Aspeed platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
:|G|: `ChiaweiW`_
:|M|: Neal Liu <neal_liu@aspeedtech.com>
:|G|: `Neal-liu`_
:|F|: docs/plat/ast2700.rst
:|F|: plat/aspeed/
HiSilicon HiKey and HiKey960 platform ports
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Haojian Zhuang <haojian.zhuang@linaro.org>
@ -983,3 +992,5 @@ Conventional Changelog Extensions
.. _bytefire: https://github.com/bytefire
.. _rupsin01: https://github.com/rupsin01
.. _jimmy-brisson: https://github.com/theotherjimmy
.. _ChiaweiW: https://github.com/chiaweiw
.. _Neal-liu: https://github.com/neal-liu

17
docs/plat/ast2700.rst Normal file
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@ -0,0 +1,17 @@
Aspeed AST2700
==============
Aspeed AST2700 is a 64-bit ARM SoC with 4-cores Cortex-A35 integrated.
Each core operates at 1.6GHz.
Boot Flow
---------
BootRom --> BL1/BL2 --> TF-A BL31 --> BL32 (optional) --> BL33 --> Linux Kernel
How to build
------------
.. code:: shell
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=ast2700

1
docs/plat/index.rst
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@ -8,6 +8,7 @@ Platform Ports
allwinner
arm/index
ast2700
meson-axg
meson-gxbb
meson-gxl

21
plat/aspeed/ast2700/include/plat_macros.S Normal file
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@ -0,0 +1,21 @@
/*
* Copyright (c) 2023, Aspeed Technology Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLAT_MACROS_S
#define PLAT_MACROS_S
/* ---------------------------------------------
* The below required platform porting macro
* prints out relevant platform registers
* whenever an unhandled exception is taken in
* BL31.
* Clobbers: x0 - x10, x16, x17, sp
* ---------------------------------------------
*/
.macro plat_crash_print_regs
.endm
#endif /* PLAT_MACROS_S */

58
plat/aspeed/ast2700/include/platform_def.h Normal file
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@ -0,0 +1,58 @@
/*
* Copyright (c) 2023, Aspeed Technology Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
#include <arch.h>
#include <plat/common/common_def.h>
#include <platform_reg.h>
#define PLATFORM_STACK_SIZE UL(0x1000)
/* cpu topology */
#define PLATFORM_SYSTEM_COUNT U(1)
#define PLATFORM_CLUSTER_COUNT U(1)
#define PLATFORM_CORE_PRIMARY U(0)
#define PLATFORM_CORE_COUNT_PER_CLUSTER U(4)
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_CORE_COUNT_PER_CLUSTER)
/* arch timer */
#define PLAT_SYSCNT_CLKIN_HZ U(1600000000)
/* power domain */
#define PLAT_MAX_PWR_LVL U(1)
#define PLAT_NUM_PWR_DOMAINS U(5)
#define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE U(2)
/* cache line size */
#define CACHE_WRITEBACK_SHIFT U(6)
#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
/* translation tables */
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 36)
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40)
#define MAX_XLAT_TABLES U(8)
#define MAX_MMAP_REGIONS U(32)
/* BL31 region */
#define BL31_BASE ULL(0x400000000)
#define BL31_SIZE ULL(0x400000)
#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
/* BL32 region */
#define BL32_BASE BL31_LIMIT
#define BL32_SIZE ULL(0x400000)
#define BL32_LIMIT (BL32_BASE + BL32_SIZE)
/* console */
#define CONSOLE_UART_BASE UART12_BASE
#define CONSOLE_UART_CLKIN_HZ U(1846153)
#define CONSOLE_UART_BAUDRATE U(115200)
#endif /* PLATFORM_DEF_H */

28
plat/aspeed/ast2700/include/platform_reg.h Normal file
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@ -0,0 +1,28 @@
/*
* Copyright (c) 2023, Aspeed Technology Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_REG_H
#define PLATFORM_REG_H
/* GIC */
#define GICD_BASE U(0x12200000)
#define GICD_SIZE U(0x10000)
#define GICR_BASE U(0x12280000)
#define GICR_SIZE U(0x100000)
/* UART */
#define UART_BASE U(0x14c33000)
#define UART12_BASE (UART_BASE + 0xb00)
/* CPU-die SCU */
#define SCU_CPU_BASE U(0x12c02000)
#define SCU_CPU_SMP_READY (SCU_CPU_BASE + 0x780)
#define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788)
#define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790)
#define SCU_CPU_SMP_EP3 (SCU_CPU_BASE + 0x798)
#define SCU_CPU_SMP_POLLINSN (SCU_CPU_BASE + 0x7a0)
#endif /* PLATFORM_REG_H */

100
plat/aspeed/ast2700/plat_bl31_setup.c Normal file
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@ -0,0 +1,100 @@
/*
* Copyright (c) 2023, Aspeed Technology Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <common/debug.h>
#include <common/desc_image_load.h>
#include <drivers/arm/gicv3.h>
#include <drivers/console.h>
#include <drivers/ti/uart/uart_16550.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <platform_def.h>
static console_t console;
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
static unsigned int plat_mpidr_to_core_pos(u_register_t mpidr)
{
/* to workaround the return type mismatch */
return plat_core_pos_by_mpidr(mpidr);
}
static const gicv3_driver_data_t plat_gic_data = {
.gicd_base = GICD_BASE,
.gicr_base = GICR_BASE,
.rdistif_num = PLATFORM_CORE_COUNT,
.rdistif_base_addrs = rdistif_base_addrs,
.mpidr_to_core_pos = plat_mpidr_to_core_pos,
};
static const mmap_region_t plat_mmap[] = {
MAP_REGION_FLAT(GICD_BASE, GICD_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(GICR_BASE, GICR_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(UART_BASE, PAGE_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(SCU_CPU_BASE, PAGE_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
{ 0 }
};
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
console_16550_register(CONSOLE_UART_BASE, CONSOLE_UART_CLKIN_HZ,
CONSOLE_UART_BAUDRATE, &console);
console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
}
void bl31_plat_arch_setup(void)
{
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE);
mmap_add_region(BL_CODE_END, BL_CODE_END,
BL_END - BL_CODE_END,
MT_RW_DATA | MT_SECURE);
mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE,
MT_MEMORY | MT_RW);
mmap_add(plat_mmap);
init_xlat_tables();
enable_mmu_el3(0);
}
void bl31_platform_setup(void)
{
gicv3_driver_init(&plat_gic_data);
gicv3_distif_init();
gicv3_rdistif_init(plat_my_core_pos());
gicv3_cpuif_enable(plat_my_core_pos());
}
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
entry_point_info_t *ep_info;
ep_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
if (!ep_info->pc) {
return NULL;
}
return ep_info;
}

64
plat/aspeed/ast2700/plat_helpers.S Normal file
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@ -0,0 +1,64 @@
/*
* Copyright (c) 2023, Aspeed Technology Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <asm_macros.S>
#include <assert_macros.S>
#include <arch.h>
#include <cortex_a35.h>
#include <platform_def.h>
.globl plat_is_my_cpu_primary
.globl plat_my_core_pos
.globl plat_secondary_cold_boot_setup
.globl plat_get_syscnt_freq2
.globl plat_crash_console_init
.globl plat_crash_console_putc
.globl plat_crash_console_flush
/* unsigned int plat_is_my_cpu_primary(void); */
func plat_is_my_cpu_primary
mrs x0, mpidr_el1
and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
cmp x0, #PLATFORM_CORE_PRIMARY
cset w0, eq
ret
endfunc plat_is_my_cpu_primary
/* unsigned int plat_my_core_pos(void); */
func plat_my_core_pos
mrs x0, mpidr_el1
mov x2, #PLATFORM_CORE_COUNT_PER_CLUSTER
and x1, x0, #MPIDR_CPU_MASK
and x0, x0, #MPIDR_CLUSTER_MASK
madd x0, x0, x2, x1
ret
endfunc plat_my_core_pos
/* unsigned int plat_get_syscnt_freq2(void); */
func plat_get_syscnt_freq2
mov_imm w0, PLAT_SYSCNT_CLKIN_HZ
ret
endfunc plat_get_syscnt_freq2
/* int plat_crash_console_init(void); */
func plat_crash_console_init
mov_imm x0, CONSOLE_UART_BASE
mov_imm x1, CONSOLE_UART_CLKIN_HZ
mov_imm x2, CONSOLE_UART_BAUDRATE
b console_16550_core_init
endfunc plat_crash_console_init
/* int plat_crash_console_putc(int); */
func plat_crash_console_putc
mov_imm x1, CONSOLE_UART_BASE
b console_16550_core_putc
endfunc plat_crash_console_putc
/* void plat_crash_console_flush(void); */
func plat_crash_console_flush
mov_imm x0, CONSOLE_UART_BASE
b console_16550_core_flush
endfunc plat_crash_console_flush

63
plat/aspeed/ast2700/plat_pm.c Normal file
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@ -0,0 +1,63 @@
/*
* Copyright (c) 2023, Aspeed Technology Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <common/debug.h>
#include <drivers/arm/gicv3.h>
#include <drivers/console.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <plat/common/platform.h>
static uintptr_t sec_ep;
static int plat_pwr_domain_on(u_register_t mpidr)
{
unsigned int cpu = plat_core_pos_by_mpidr(mpidr);
uintptr_t ep_reg;
switch (cpu) {
case 1U:
ep_reg = SCU_CPU_SMP_EP1;
break;
case 2U:
ep_reg = SCU_CPU_SMP_EP2;
break;
case 3U:
ep_reg = SCU_CPU_SMP_EP3;
break;
default:
return PSCI_E_INVALID_PARAMS;
}
mmio_write_64(ep_reg, sec_ep);
dsbsy();
sev();
return PSCI_E_SUCCESS;
}
static void plat_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
gicv3_rdistif_init(plat_my_core_pos());
gicv3_cpuif_enable(plat_my_core_pos());
}
static const plat_psci_ops_t plat_psci_ops = {
.pwr_domain_on = plat_pwr_domain_on,
.pwr_domain_on_finish = plat_pwr_domain_on_finish,
};
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
const plat_psci_ops_t **psci_ops)
{
sec_ep = sec_entrypoint;
*psci_ops = &plat_psci_ops;
return 0;
}

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plat/aspeed/ast2700/plat_topology.c Normal file
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@ -0,0 +1,43 @@
/*
* Copyright (c) 2023, Aspeed Technology Inc.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <lib/psci/psci.h>
#include <platform_def.h>
static const unsigned char ast2700_power_domain_tree_desc[] = {
PLATFORM_SYSTEM_COUNT,
PLATFORM_CORE_COUNT_PER_CLUSTER,
};
const unsigned char *plat_get_power_domain_tree_desc(void)
{
return ast2700_power_domain_tree_desc;
}
unsigned int plat_core_pos_by_mpidr(u_register_t mpidr)
{
unsigned int cluster_id, cpu_id;
mpidr &= MPIDR_AFFINITY_MASK;
if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) {
return -1;
}
cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
return -1;
}
if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER) {
return -1;
}
return (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER) + cpu_id;
}

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plat/aspeed/ast2700/platform.mk Normal file
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@ -0,0 +1,32 @@
#
# Copyright (c) 2023, Aspeed Technology Inc.
#
# SPDX-License-Identifier: BSD-3-Clause
#
include drivers/arm/gic/v3/gicv3.mk
include lib/xlat_tables_v2/xlat_tables.mk
PLAT_AST2700 := plat/aspeed/ast2700
PLAT_INCLUDES := \
-I${PLAT_AST2700}/include
BL31_SOURCES += \
common/desc_image_load.c \
lib/cpus/aarch64/cortex_a35.S \
plat/common/plat_gicv3.c \
plat/common/plat_psci_common.c \
drivers/ti/uart/aarch64/16550_console.S \
${PLAT_AST2700}/plat_helpers.S \
${PLAT_AST2700}/plat_topology.c \
${PLAT_AST2700}/plat_bl31_setup.c \
${PLAT_AST2700}/plat_pm.c \
${GICV3_SOURCES} \
${XLAT_TABLES_LIB_SRCS}
PROGRAMMABLE_RESET_ADDRESS := 1
COLD_BOOT_SINGLE_CPU := 1
ENABLE_SVE_FOR_NS := 0