Commit graph

2632 commits

Author SHA1 Message Date
Hugues Kamba-Mpiana
deb7210d16 docs(maintainers): update Corstone-1000 maintainers
* Add new maintainers: Hugues Kamba Mpiana
* Remove maintainers: Xueliang Zhong
* Update contact information for existing maintainers

Change-Id: Ie4b7e7a1a179e3bf6f8d8e6c8e7ff0ad788e9f8f
Signed-off-by: Hugues Kamba-Mpiana <hugues.kambampiana@arm.com>
2024-08-15 08:45:44 +01:00
Charlie Bareham
4dcbba98ce feat: add option to input attr as string of flag names
Change-Id: I56f0364ef43c9d415a335474e15b68e79db37f5d
Signed-off-by: Charlie Bareham <charlie.bareham@arm.com>
2024-08-02 12:14:53 +00:00
Charlie Bareham
792e8e896f feat: add option to input text instead of tag id number
Change-Id: I6d1b1a20d1cd5b073d7d614da102b9e6bd8ea522
Signed-off-by: Charlie Bareham <charlie.bareham@arm.com>
2024-08-02 12:14:53 +00:00
Charlie Bareham
311209934e feat: add creating transfer lists from yaml files
This commit adds a command create-from-yaml to tlc, which
creates a transfer list from a yaml file. It also changes
the files structure of the fixtures in the unit tests so
they are in a directory called trusted-firmware-a. This
is necessary because blob file paths in the yaml file are
relative to the root of TF-A.

The blob files are not verified by TLC, so it can be used
to load arbitrary binary information into the transfer
list. The authenticity of the transfer list must be
ensured by the loader.

Change-Id: Idf704ce5d9b7e28b31f471ac337e4aef33d0ad8a
Signed-off-by: Charlie Bareham <charlie.bareham@arm.com>
2024-08-02 12:14:53 +00:00
Harrison Mutai
6ac31f3e76 feat(tlc): add host tool for static TL generation
Transfer List Compiler is a command line tool that enables the static
generation of TL's compliant with version 0.9 of the firmware handoff
specification. The intent of this tool is to support information passing
via the firmware handoff framework to bootloaders that run without
preceding images (i.e. `RESET_TO_BL31`).

It currently allows for TL's to be statically generated from blobs of
data, and modified by removing/adding TE's. Future work will provide
support for TL generation from configuration file.

Change-Id: Iff670842e34c9ad18eac935248ee2aece43dc533
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Co-authored-by: Charlie Bareham <charlie.bareham@arm.com>
2024-07-30 10:25:57 +00:00
Manish V Badarkhe
93b7b752e9 Merge "build(amu): restrict counters (RAZ)" into integration 2024-07-29 18:55:03 +02:00
Manish Pandey
e7c060d559 Merge "feat(fgt2): add support for FEAT_FGT2" into integration 2024-07-24 17:26:21 +02:00
Manish Pandey
c5b8de86c8 Merge "feat(debugv8p9): add support for FEAT_Debugv8p9" into integration 2024-07-22 18:07:11 +02:00
Arvind Ram Prakash
33e6aaacf1 feat(fgt2): add support for FEAT_FGT2
This patch disables trapping to EL3 when the FEAT_FGT2
specific trap registers are accessed by setting the
SCR_EL3.FGTEn2 bit

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I6d2b614affb9067b2bc3d7bf0ae7d169d031592a
2024-07-18 13:49:43 -05:00
Arvind Ram Prakash
83271d5a5a feat(debugv8p9): add support for FEAT_Debugv8p9
This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3613af1dd8cb8c0d3c33dc959f170846c0b9695a
2024-07-18 13:49:43 -05:00
Yidi Lin
65ada75717 fix(docs): fix CPU type for mt8195
MT8195 features four Cortex-A78 cores not Cortex-A76.

Change-Id: I62c60373e7a3e570bcadaeaf065ca0f7473cb838
Signed-off-by: Yidi Lin <yidilin@chromium.org>
2024-07-17 11:47:39 +08:00
Manish V Badarkhe
0dc0fda716 Merge changes from topic "stm32mp2_doc_update" into integration
* changes:
  feat(docs): add STM32MP2 docs links
  docs(stm32mp2): correct STM32MP2 frequencies
2024-07-03 15:36:54 +02:00
Manish Pandey
8d6fc86c35 Merge "refactor(docs): update RSE docs to match the example CCA token" into integration 2024-07-03 14:43:27 +02:00
Yann Gautier
21b6260ec8 feat(docs): add STM32MP2 docs links
Add links to official STMicroelectronics documentation (STM32MP2
series presentation and wiki).

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I2fca0da56bc6064c222df34493921dff3e119a22
2024-07-03 13:48:20 +02:00
Nicolas Le Bayon
7b7d23cd77 docs(stm32mp2): correct STM32MP2 frequencies
STM32MP25xA & STM32MP25xC versions run at 1.2GHz.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I75aea682c8e3fa89e7ac1347bb7f9d02f2086222
2024-07-03 13:48:20 +02:00
Madhukar Pappireddy
c4d9fbec5e Merge changes from topic "add_s32cc_clk_skeleton" into integration
* changes:
  feat(s32g274a): use s32cc clock driver
  feat(nxp-drivers): add clock skeleton for s32cc
2024-07-01 15:29:52 +02:00
Ghennadi Procopciuc
3a580e9e47 feat(nxp-drivers): add clock skeleton for s32cc
The S32CC is an umbrella for S32G2, S32G3 and S32R45 SoCs; therefore,
this clock driver will be used for all of these families.

Change-Id: Iede5371b212b67cf494a033c62fbfdcbe9b1a879
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
2024-06-28 08:33:39 +03:00
Govindraj Raja
e28ea93064 docs(fvp): update FVP versions used
Patch series:
https://review.trustedfirmware.org/q/hashtag:%22fvp_migration_11_26%22+(status:open%20OR%20status:merged)

Migrated FVP's to use version 11.26.11 and 11.24.24, also removed
some model testing that are now no more available with newer model
configuration.

Change-Id: Ib93a7148270e2b6fb356a631dcc36061c7c8341c
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2024-06-27 09:33:03 -05:00
Joanna Farley
6f05b8d45e Merge "feat(versal2): add support for AMD Versal Gen 2 platform" into integration 2024-06-18 12:27:27 +02:00
Manish V Badarkhe
08fc380ab3 Merge changes from topic "st-nand-backup-fwu" into integration
* changes:
  refactor(st): rename plat_set_image_source
  feat(st): add FWU with boot from NAND
  feat(st): manage backup partitions for NAND devices
  feat(bl): add plat handler for image loading
  refactor(bl)!: remove unused plat_try_next_boot_source
2024-06-17 20:05:05 +02:00
Thomas Fossati
6dfeb60a37 refactor(docs): update RSE docs to match the example CCA token
The RSE documentation includes binary and JSON dumps of the CCA platform
token.  This change updates those to match the example CCA platform
token from [1], which is also the one returned by the TC and QEMU
platforms.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/28493

Change-Id: I21048e7f995eb24212cf62fb2128b576bc11ecff
Signed-off-by: Thomas Fossati <thomas.fossati@linaro.org>
2024-06-17 16:29:04 +02:00
Chris Kay
7c4e1eea61 build: unify verbosity handling
This change introduces a few helper variables for dealing with verbose
and silent build modes: `silent`, `verbose`, `q` and `s`.

The `silent` and `verbose` variables are boolean values determining
whether the build system has been configured to run silently or
verbosely respectively (i.e. with `--silent` or `V=1`).

These two modes cannot be used together - if `silent` is truthy then
`verbose` is always falsy. As such:

    make --silent V=1

... results in a silent build.

In addition to these boolean variables, we also introduce two new
variables - `s` and `q` - for use in rule recipes to conditionally
suppress the output of commands.

When building silently, `s` expands to a value which disables the
command that follows, and `q` expands to a value which supppresses
echoing of the command:

    $(s)echo 'This command is neither echoed nor executed'
    $(q)echo 'This command is executed but not echoed'

When building verbosely, `s` expands to a value which disables the
command that follows, and `q` expands to nothing:

    $(s)echo 'This command is neither echoed nor executed'
    $(q)echo 'This command is executed and echoed'

In all other cases, both `s` and `q` expand to a value which suppresses
echoing of the command that follows:

    $(s)echo 'This command is executed but not echoed'
    $(q)echo 'This command is executed but not echoed'

The `s` variable is predominantly useful for `echo` commands, where you
always want to suppress echoing of the command itself, whilst `q` is
more useful for all other commands.

Change-Id: I8d8ff6ed714d3cb401946c52955887ed7dca602b
Signed-off-by: Chris Kay <chris.kay@arm.com>
2024-06-14 15:54:48 +00:00
Manish Pandey
887e69ee73 Merge "docs: update Cortex-A32 FVP model version" into integration 2024-06-14 16:37:50 +02:00
Olivier Deprez
685d5ee143 docs: update Cortex-A32 FVP model version
Change [1] migrated Cortex-A32 FVP model to the default version used in
the TF-A CI.

[1] https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/29297

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I038087af957d3ee2b289944b4af1a8cffb1ec5ff
2024-06-13 15:56:03 +02:00
Andre Przywara
c4067a9df6 fix(docs): replace "ARM-TF" with "TF-A" in diagrams
Two diagrams in the documentation contained the string "ARM TF", which
is probably a remainder of the older "ARM Trusted Firmware" name.
Replace that with "TF-A", which is now the more widely known name for
Trusted Firmware.
This was done with an image editing program, by just moving the letters
around, as I didn't find any source for that image.

Change-Id: I1fa18341b3aa8fc8c4ecc8988bf4de66e473caa7
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2024-06-13 15:55:42 +02:00
Yann Gautier
a03dafe516 feat(bl): add plat handler for image loading
In case of load error, platform may need to try another instance, either
from another storage, or from the same storage in case of PSA FWU. On
MTD devices such as NAND, it is required to define backup partitions.
A new function plat_setup_try_img_ops() should be called by platform
code to register handlers (plat_try_images_ops) to manage loading
other images.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Ideaecaf296c0037a26fb4e6680f33e507111378a
2024-06-13 11:30:29 +02:00
Yann Gautier
2c303e393b refactor(bl)!: remove unused plat_try_next_boot_source
The plat_try_next_boot_source() API is not used by any upstream platform
and not used by platforms that asked for this API. It is then removed.
It will be replaced with a more generic interface in next patch.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I298c7acace8c5efb3c66422d8d9280ecd08e5ade
2024-06-13 10:48:02 +02:00
Amit Nagal
c97857dba2 feat(versal2): add support for AMD Versal Gen 2 platform
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM
firmware which loads TF-A(bl31) to memory, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.

Change-Id: I5065b1b7ec4ee58e77dc4096747758480c84009c
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-06-10 08:09:49 +02:00
shengfei Xu
9fd9f1d024 feat(rockchip): add RK3566/RK3568 Socs support
RK3566/RK3568 is a Quad-core soc and Cortex-a55 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4. suspend/resume system
5. reset system

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I8b98a4d07664de26bd6078f63664cbc3d9c1c68c
2024-06-07 11:59:46 +02:00
Soby Mathew
20307efa5e Merge "docs(gpt): update GPT library documentation" into integration 2024-06-03 15:26:05 +02:00
AlexeiFedorov
c944952bc3 docs(gpt): update GPT library documentation
This patch updates GPT library design documentation
with the changes introduced by patches which add
support for large GPT mappings and configuration of
memory size protected by bitlock.

Change-Id: I1f97fa8f003deb07a5f32b7237c1927581a788c8
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
2024-06-03 12:13:06 +01:00
Manish V Badarkhe
a13449da37 Merge "feat(stm32mp15): remove OP-TEE shared mem" into integration 2024-06-03 09:50:20 +02:00
Soby Mathew
261edb6a0f Merge changes I710d1780,Ia9a59bde into integration
* changes:
  feat(gpt): configure memory size protected by bitlock
  feat(gpt): add support for large GPT mappings
2024-05-28 12:26:37 +02:00
Yann Gautier
8dd2a64a12 feat(stm32mp15): remove OP-TEE shared mem
The flag STM32MP15_OPTEE_RSV_SHM was disabled and mark deprecated.
Remove the corresponding code.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I948af3e1de4b89815c967a63abe64f285c405ecc
2024-05-23 17:44:16 +02:00
Manish Pandey
f2735ebccf Merge "docs(changelog): changelog for v2.11 release" into integration 2024-05-23 13:51:22 +02:00
Manish V Badarkhe
669e2b159a docs(changelog): changelog for v2.11 release
Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.11.0

Change-Id: I34c7b342549781057da1b18116500f110bc3f5ad
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Juan Pablo Conde <JuanPablo.Conde@arm.com>
2024-05-22 19:19:54 -05:00
Manish Pandey
6370f2cbbe Merge changes from topic "hm/rt-instr" into integration
* changes:
  docs(juno): update PSCI instrumentation data
  docs(n1sdp): update N1SDP PSCI instrumentation data
2024-05-22 17:00:03 +02:00
Manish V Badarkhe
b5ead359f3 docs: move DPE option to experimental section
Since DPE support is experimental, move the build option for
the DPE to the experimental section.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I2e18947d37c52a0151b5ac656098dbae51254956
2024-05-22 14:13:50 +01:00
AlexeiFedorov
d766084fc4 feat(gpt): configure memory size protected by bitlock
This patch adds support in GPT library for configuration
of the memory block size protected by one bit of 'bitlock'
structure. Build option 'RME_GPT_BITLOCK_BLOCK' defines the
number of 512MB blocks covered by each bit. This numeric
parameter must be a power of 2 and can take the values from
0 to 512. Setting this value to 0 chooses a single spinlock
for all GPT L1 table entries. The default value is set to 1
which corresponds to 512MB per bit.

Change-Id: I710d178072894a3ef40daebea701f74d19e8a3d7
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
2024-05-22 11:41:00 +01:00
Harrison Mutai
932d6cdb25 docs(juno): update PSCI instrumentation data
Add the latest instrumentation data as of v2.11-rc0, remove data for
v2.9.

Change-Id: I8c055278d732220a9be88978ed63d27e453b7f2f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2024-05-21 13:25:16 +00:00
Harrison Mutai
e9c335fbda docs(n1sdp): update N1SDP PSCI instrumentation data
Add data for v2.11 release and remove data from v2.9.

Change-Id: Ic960cece6f27993cefebf483c768967bd6f2cad1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2024-05-21 13:25:16 +00:00
Bipin Ravi
3ab6ae4ef4 docs(maintainers): update the maintainer list for LTS
This patch updates the maintainer list for LTS.

Change-Id: I7942288cd79dd163bebd3397bf908bf29906d59e
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
2024-05-16 16:17:35 -05:00
Madhukar Pappireddy
b131a12377 docs(maintainers): add code owners for runtime services module
This patch adds code owners responsible for maintaining source files
related to runtime services functionality in TF-A.

Change-Id: I24fbbfd017f90a4fae2ffbb94c8eb81d0d837f8e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-05-15 13:56:04 -05:00
Madhukar Pappireddy
017566560e docs(maintainers): add missing header files
Few header files are added to the lists tracking code owners of
various modules in TF-A project.

Also remove drivers/nuvoton directory, which does not exist, from the list
of files maintained by the corresponding owners.

Change-Id: Iad7ce5b1430965237004c9e76e972a3469d20c9d
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-05-15 13:56:04 -05:00
Madhukar Pappireddy
5ecb6bb0bf docs(maintainers): add code owners for context management module
This patch adds code owners responsible for maintaining context
management source files in TF-A.

Change-Id: Idc679a907b8380e81d5fbb129fcb74cea5983c0e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-05-15 13:56:04 -05:00
Madhukar Pappireddy
4d16bc70bf docs(maintainers): add code owners for runtime exceptions module
This patch adds code owners responsible for maintaining runtime
exceptions and interrupt management modules in TF-A.

Change-Id: Idb131a2af143097e4d05a285e08ef12cd5d3db2a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-05-15 13:56:04 -05:00
Madhukar Pappireddy
a45f75a6a7 docs(maintainers): add missing files related to SPMD
Few header files are added to the list maintained by SPMD code owners.
Also, added myself as one of the code owners for SPMD module in TF-A.

Change-Id: Ic017cb98013d349702c35837463586d4aae65543
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-05-15 13:56:04 -05:00
Madhukar Pappireddy
46fc25019f docs(maintainers): update missing files related to EL3 SPMC
Few header files are added to the list maintained by EL3 SPMC
code owner.

Also added missing copyright license footer message.

Change-Id: I72afe4c4e1280ef64610a5efe6d1b0e2c9727bb0
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2024-05-15 13:55:21 -05:00
Olivier Deprez
ed3525e604 docs: remove reference to phabricator pages
Phabricator wiki is deprecated, remove TF-A links to this website.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I1255a1513524504636b9c914f9dacf3c54063196
2024-05-15 14:27:45 +02:00
AlexeiFedorov
ec0088bbab feat(gpt): add support for large GPT mappings
This patch adds support for large GPT mappings using
Contiguous descriptors. The maximum size of supported
contiguous block in MB is defined in RME_GPT_MAX_BLOCK
build parameter and takes values 0, 2, 32 and 512 and
by default set to 2 in make_helpers/defaults.mk.
Setting RME_GPT_MAX_BLOCK value to 0 disables use of
Contiguous descriptors.
Function gpt_tlbi_by_pa_ll() and its declaration
are removed from lib/aarch64/misc_helpers.S and
include/arch/aarch64/arch_helpers.h, because the
GPT library now uses tlbirpalos_xxx() functions.

Change-Id: Ia9a59bde1741c5666b4ca1de9324e6dfd6f734eb
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
2024-05-14 10:36:42 +02:00