From the get rate callback perspective, all types of clock muxes should
return the frequency of the selected source, regardless of whether it is
an MC_CGM or PLL mux.
Change-Id: I24ae821013b0844e4d62793fde12b53b043a9776
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The get rate callback is needed for s32cc_pll_out_div to get the A53
cores and DDR rate.
Change-Id: Ife7860c9941e819b612d7948dac9843bdf0c31c4
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The get rate callback is needed for s32cc_fixed_div to allow the
frequency compilation for modules attached to a fixed divider like
LINFLEXD_CLK.
Change-Id: Ibc3e52f7f1127bba0dd793be0a26bdff15260824
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add the option to obtain the rate of an s32cc_dfs_div object. As in the
case of the PLL, the output divider of a DFS will return its targeted
frequency if the module is disabled and calculate the rate based on the
settings found in its registers if the module is turned on.
Change-Id: Id6db92dbdf03f8119875476ad8f7aa268ff6ea93
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add the option to obtain the rate of an s32cc_dfs object. The DFS rate
depends on the module to which it's connected. Therefore, it will always
return the rate of its parent.
Change-Id: Ie3becd36721f541d0fab11b2fb57aacd66d48220
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add the option to obtain the rate of an s32cc_pll object. The rate of
the PLL can be obtained regardless of its hardware state. The targeted
frequency is returned in case the PLL is off. Otherwise, the frequency
is determined based on settings found in its registers.
Change-Id: Id200d0eff149109a724eee69b063bf750d5cba2e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add the option to obtain the rate of an s32cc_clk object. s32cc_clk are
usually links to either another s32cc_clk or a different clock module.
Therefore, this function routes the request.
Change-Id: I0c1174cb861d2062882319e46cb6ca97bad70aab
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Replace the dummy implementation of clk_ops.get_rate with a basic
version that only handles the oscillator objects. Subsequent commits
will add more objects to this list.
Change-Id: I8c1bbbfa6b116fdcf5a1f1353bdb52b474bac831
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
* changes:
perf(psci): pass my_core_pos around instead of calling it repeatedly
refactor(psci): move timestamp collection to psci_pwrdown_cpu
refactor(psci): factor common code out of the standby finisher
refactor(psci): don't use PSCI_INVALID_PWR_LVL to signal OFF state
docs(psci): drop outdated cache maintenance comment
The build macro no longer coverts variable names to uppercase.
We need to convert it to uppercase to pass it on.
Change-Id: If808fc77bce71d575e2d43ff83c4d9bcdcc52326
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>
FEAT_MOPS, mandatory from Arm v8.8, is typically managed in EL2.
However, in configurations where NS_EL2 is not enabled,
EL3 must set the HCRX_EL2.MSCEn bit to 1 to enable the feature.
This patch ensures FEAT_MOPS is enabled by setting HCRX_EL2.MSCEn to 1.
Change-Id: Ic4960e0cc14a44279156b79ded50de475b3b21c5
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
* changes:
feat(s32g274a): split early clock initialization
feat(s32g274a): enable MMU for BL31 stage
feat(s32g274a): dynamically map GIC regions
feat(s32g274a): enable MMU for BL2 stage
feat(s32g274a): dynamically map siul2 and fip img
feat(s32g274a): map each image before its loading
feat(nxp-clk): dynamic map of the clock modules
feat(s32g274a): increase the number of MMU regions
feat(s32g274a): add console mapping
For a couple of releases now we have officially withdrawn support for
building TF-A on Windows using the native environment, relying instead
on POSIX emulation layers like MSYS2, Mingw64, Cygwin or WSL.
This change removes the remainder of the OS compatibility layer
entirely, and migrates the build system over to explicitly relying on a
POSIX environment.
Change-Id: I8fb60d998162422e958009afd17eab826e3bc39b
Signed-off-by: Chris Kay <chris.kay@arm.com>
Initializing all early clocks before the MMU is enabled can impact boot
time. Therefore, splitting the setup into A53 clocks and peripheral
clocks can be beneficial, with the peripheral clocks configured after
fully initializing the MMU.
Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Enable the MMU and add two entries to map the BL31 code and data
regions. Additional mappings will be added dynamically, enhancing
flexibility and modularity during the porting process.
Change-Id: I333c34c58274a115f62f54730bba5b71165e3e36
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Dynamically add entries for the GIC distributor and all its
redistributors for the cases when the platform is booted using enabled
MMU.
Change-Id: Ia810ec2329993057173e8fc25620a3df59b1e55d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Enable the MMU and add two entries to map the BL2 code and data regions.
Additional mappings will be added dynamically, enhancing flexibility and
modularity during the porting process.
Change-Id: I107abf944dfdce9dcff47b08272a5001484de8a9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Dynamically map the remaining regions part of the BL2 stages using
dynamic regions.
Change-Id: Ia81666920b941218ddaa7d3244dfa5212525c75d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The regions used by the stages loaded by BL2 must be mapped before they
can be used.
Change-Id: Ia70f8c5f35d7930e2b20f1a26be0ad2cdfea2b1a
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Add all clock modules as entries in MMU using dynamic regions.
Change-Id: I56f724ced4bd024554c7b38afd14ea420de80cc6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Increase the maximum number of regions allocated by the translation
table library to accommodate the entries added in the next commits.
Change-Id: Ib0dd2d0dbc9b4a574367141a7c96d76dd08e2c7f
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
On some platforms plat_my_core_pos is a nontrivial function that takes a
bit of time and the compiler really doesn't like to inline. In the PSCI
library, at least, we have no need to keep repeatedly calling it and we
can instead pass it around as an argument. This saves on a lot of
redundant calls, speeding the library up a bit.
Change-Id: I137f69bea80d7cac90d7a20ffe98e1ba8d77246f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
psci_pwrdown_cpu has two callers, both of which save timestamps meant to
measure how much time the cache maintenance operations take. Move the
timestamp collection inside to save on a bit of code duplication.
Change-Id: Ia2e7168faf7773d99b696cbdb6c98db7b58e31cf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
psci_suspend_to_standby_finisher and psci_cpu_suspend_finish do mostly
the same stuff, besides the system management associated with their
respective wakeup paths. So bring the wake from standby path in line
with the wake from reset path - caller acquires locks and manages
context. This way both behave in vaguely the same way. We can also bring
their names in line so it's more apparent how they are different.
This is in preparation for cores waking from sleep, coming in another
patch. No functional change is expected.
Change-Id: I0e569d12f65d231606080faa0149d22efddc386d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
The target_pwrlvl field in the psci cpu data struct only stores the
highest power domain that a CPU_SUSPEND call affected, and is used to
resume those same domains on warm reset. If the cpu is otherwise OFF
(never turned on or CPU_OFF), then this needs to be the highest power
level because we don't know the highest level that will be off.
So skip the invalidation and always keep the field to the maximum value.
During suspend the field will be lowered to the appropriate value and
then put back after wakeup.
Also, do that in the suspend to standby path as well as it will have
been written before the sleep and it might end up incorrect.
Change-Id: I614272ec387e1d83023c94700780a0f538a9a6b6
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
The comment was written when cache maintenance had to be considered when
calling this function. But that argument was dropped a while back and
this comment no longer makes any sense.
Change-Id: Ib68293f23cc3edca3010164dfe8866956b8e1a63
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Patch fc7dca72ba656e5f147487b20f9f0fb6eb39e116 changed the owning
security states of the TRBE and SPE buffers to NS. The thinking was that
this would assist SMCCC feature availability to more easily determine
if the feature is enabled or disabled. However, that only changed bit 0
while the SMCCC feature only looks at bit 1 so this change is redundant.
It was also meant to tighten security but that was done by
73d98e3759 instead.
Annoyingly, FEAT_TRBE has TRBIDR_EL1 which reports that programming is
allowed when the current security state owns the buffer even when the
MDCR_EL3 setting disallows this in practice.
So revert the functional aspect of the patch as it causes linux panics
with ERRATA_A520_2938996. Keep the defines as they are used elsewhere.
Change-Id: I39463d585df89aee44d1996137616da85d678f41
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
* changes:
feat(el3_spmc): ffa error handling in direct msg
feat(ff-a): support FFA_MSG_SEND_DIRECT_REQ2/RESP2
feat(ff-a): add FFA_MEM_PERM_GET/SET_SMC64
feat(el3-spmc): support Hob list to boot S-EL0 SP
feat(synquacer): add support Hob creation
fix(fvp): exclude extend memory map TZC regions
feat(fvp): add StandaloneMm manifest in fvp
feat(spm): use xfer list with Hob list in SPM_MM
When an FFA_ERROR happens while handling a direct message
from normal world, return to normal world with
FFA_ERROR. Otherwise, the system would re-enter the secure partition
with FFA_ERROR.
Change-Id: I3d9a68a41b4815c1a8e10354cfcf68fec9f4b800
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
StandaloneMm which is S-EL0 partition uses
FFA_MSG_SEND_DIRECT_REQ2/RESP2 to handle multiple services.
For this, add support for FFA_MSG_SEND_DIRECT_REQ2/RESP2 in el3_spmc
restrictly up to use 8 registers.
although FF-A v1.2 defines FFA_MSG_SEND_DIRECT_REQ2/RESP2
with ability to pass/return up to 18 registers.
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: I8ab1c332d269d9d131330bb2debd10d75bdba1ee
If MTKLIB_PATH is provided, the build will use the library provided by
MTKLIB_PATH. Otherwise, it will use stub implementation.
Change-Id: I218e724231c8bbc6cc851a240c6bbc4f6f49f154
Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com>
* changes:
feat(qemu): hand off TPM event log via TL
feat(handoff): common API for TPM event log handoff
feat(handoff): transfer entry ID for TPM event log
fix(qemu): fix register convention in BL31 for qemu
fix(handoff): fix register convention in opteed
Commit 71c4443886ff ("fix(lib/rmm_el3_ifc): add console name to checksum
calculation") on TF-RMM updated the checksum calcualtion of the RMM
manifest to include the console names.
Include console names in the QEMU manifest to remain compatible with
RMM, just like commit aa99881d30 ("fix(rme): add console name to
checksum calculation") did for FVP.
Checksum calculation is done by adding together 64-bit values. Add a
helper that does this.
Change-Id: Ica6cab628160593830270bef1acdeb475d1c0c36
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
* changes:
feat(smccc): implement SMCCC_ARCH_FEATURE_AVAILABILITY
refactor(cm): clean up per-world context
refactor(cm): change owning security state when a feature is disabled
Implement stub functions for the EMI driver to ensure that the build
can pass when a prebuilt library is not available.
Change-Id: I296945a3df6766a3a133cd385a1e5038ca979403
Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com>
