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feat(nxp-clk): add get_rate for s32cc_pll_out_div
The get rate callback is needed for s32cc_pll_out_div to get the A53 cores and DDR rate. Change-Id: Ife7860c9941e819b612d7948dac9843bdf0c31c4 Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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1 changed files with 54 additions and 0 deletions
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@ -1341,6 +1341,57 @@ static int set_pll_div_freq(const struct s32cc_clk_obj *module, unsigned long ra
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return 0;
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}
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static int get_pll_div_freq(const struct s32cc_clk_obj *module,
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const struct s32cc_clk_drv *drv,
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unsigned long *rate, unsigned int depth)
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{
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const struct s32cc_pll_out_div *pdiv = s32cc_obj2plldiv(module);
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const struct s32cc_pll *pll;
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unsigned int ldepth = depth;
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uintptr_t pll_addr = 0UL;
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unsigned long pfreq;
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uint32_t pllodiv;
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uint32_t dc;
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int ret;
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ret = update_stack_depth(&ldepth);
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if (ret != 0) {
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return ret;
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}
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pll = get_div_pll(pdiv);
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if (pll == NULL) {
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ERROR("The parent of the PLL DIV is invalid\n");
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return -EINVAL;
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}
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ret = get_base_addr(pll->instance, drv, &pll_addr);
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if (ret != 0) {
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ERROR("Failed to detect PLL instance\n");
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return -EINVAL;
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}
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ret = get_module_rate(pdiv->parent, drv, &pfreq, ldepth);
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if (ret != 0) {
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ERROR("Failed to get the frequency of PLL %" PRIxPTR "\n",
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pll_addr);
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return ret;
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}
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pllodiv = mmio_read_32(PLLDIG_PLLODIV(pll_addr, pdiv->index));
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/* Disabled module */
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if ((pllodiv & PLLDIG_PLLODIV_DE) == 0U) {
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*rate = pdiv->freq;
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return 0;
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}
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dc = PLLDIG_PLLODIV_DIV(pllodiv);
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*rate = (pfreq * FP_PRECISION) / (dc + 1U) / FP_PRECISION;
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return 0;
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}
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static int set_fixed_div_freq(const struct s32cc_clk_obj *module, unsigned long rate,
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unsigned long *orate, unsigned int *depth)
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{
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@ -1584,6 +1635,9 @@ static int get_module_rate(const struct s32cc_clk_obj *module,
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case s32cc_fixed_div_t:
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ret = get_fixed_div_freq(module, drv, rate, ldepth);
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break;
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case s32cc_pll_out_div_t:
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ret = get_pll_div_freq(module, drv, rate, ldepth);
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break;
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default:
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ret = -EINVAL;
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break;
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