For peripheral where both status and secure-status are set to okay,
the function fdt_get_status() returns the same status (DT_SHARED) if
secure-status property is omitted. This secure-status property can then
be removed in boards DT files for iwdg nodes.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9f9360842d4d41288db0cf1b92063f347c72d137
The RCC security is managed with a dedicated compatible:
"st,stm32mp1-rcc-secure" [1].
Remove useless secure-status property in boards rcc nodes.
[1] 812daf916c ("feat(st): update the security based on new compatible")
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iff31044ade78dd9c432120dce65375fe2b0d36d6
This should replace the stm32mp157a-avenger96.dts with the new device
tree files split into the STM32MP15 DHCOR SoM definition and the
Avenger96 baseboard like it's done in Linux and U-Boot.
Differences to stm32mp157a-avenger96.dts:
- Enable sdmmc2 for booting from eMMC
- improved clock settings like in U-Boot commit b6055945
"ARM: dts: stm32: Adjust PLL4 settings on AV96 again"
- improved DDR settings for DHSOMs like in U-Boot commit 92ca0f74
"ARM: dts: stm32: Synchronize DDR setttings on DH SoMs"
TF-A with this new dts(i) files on this board was fully tested with
the latest OP-TEE developer setup.
Change-Id: I85ce8eca7747965af3555fc19fd7b192dc3e5740
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Align with STM32MP15 file, use the macro STM32MP_DDR_S_SIZE, instead of
an hard-coded value.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ib31bed1ffe89ff221fab1884a2db729ce1e21846
Instead of adding all peripheral nodes in SoC DT files, and then
removing them with BL2 overlay file, just remove them from SoC files.
And remove peripherals that are not used in TF-A on STM32MP13.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I0c408d29b55cb94644c92539460fc62485781223
On STM32MP13, the max frequency for IOs is 130MHz, update the SDMMC
max-frequency property with this value. This is an alignment with
Linux DT file.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: If4b364f53f87d4b5d276a976af486a3bf083f49b
Update the pinctrl nodes for sdmmc instances in stm32mp13-pinctrl.dtsi
file to align with Linux. The boards DT files then need to be updated
accordingly.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4e1f3cf78794bfb7bbe53cfc7e88623c7e79855d
The ETZPC is always secure, and the driver does no more rely on
secure-status (and status) DT property. Remove them from the SoC
DT file.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I5f1d3534679553d79e6866396cd70e21a595ef6a
The #address-cells and #size-cells properties affect the size of reg
properties in *child* nodes only, they have no effect on the current
node.
The /memory node has no children, hence there is no need to specify
those properties. dt-validate complains about this:
==========
morello-soc.dtb: /: memory@80000000: '#address-cells', '#size-cells' do
not match any of the regexes: 'pinctrl-[0-9]+'
From schema: dt-schema.git/dtschema/schemas/memory.yaml
==========
Remove the unneeded properties.
Change-Id: I35058a00fa9bfa1007f31a4c21898dd45c586aa8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The official GICv3 DT bindings require only a limited number of
compatible string, and disavowes the naming of an implementation.
Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: interrupt-controller@2c010000: compatible: 'oneOf' conditional failed, one must be fixed:
['arm,gic-600', 'arm,gic-v3'] is too long
'arm,gic-600' is not one of ['qcom,msm8996-gic-v3']
'arm,gic-v3' was expected
From schema: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
============
Drop the redundant (because runtime detectable) and undocumented
implementation version, and just use the standard compatible string.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I05b207df271d6aa5bf3f2163f99ac0c594204c75
The various official DT bindings only allow certain node name patterns.
Linux' "make dtbs_check" reports:
===========
.../morello-soc.dt.yaml: sram@45200000: 'scp-shmem@0', 'scp-shmem@80' do not match any of the regexes: '^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$', 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/sram/sram.yaml
.../morello-soc.dt.yaml: uart@2a400000: $nodename:0: 'uart@2a400000' does not match '^serial(@.*)?$'
From schema: Documentation/devicetree/bindings/serial/pl011.yaml
.../morello-soc.dt.yaml: interrupt-controller@2c010000: 'its@30040000', 'its@30060000', 'its@30080000', 'its@300a0000' do not match any of the regexes: '^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$', '^gic-its@', '^interrupt-controller@[0-9a-f]+$', 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
===========
Rename the node names to improve bindings compliance.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ieff576512853eb2bf932c7a2b338c91e0c116b87
The official Arm MHU DT binding suggests to group the shmem (and mboxes)
values to signify the number of mailboxes supported.
Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: scmi: shmem:0: [17, 18] is too long
From schema: dt-schema.git/dtschema/schemas/mbox/mbox-consumer.yaml
============
Add angle brackets at the right location to mark the boundaries between
the two mailbox instances used.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: If585c98b5e8e55cd5c0b1261e03ce4b91a4c0413
The official Arm Komeda DPU DT binding only mentions the "arm,mali-d71"
string as a possible compatible string. The D32 version is just a
variant of the D71, and the revision can and will be auto-detected at
runtime.
Add the usual fallback compatible string scheme to contain a documented
compatible string.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ic1eade122b030dc983944b161eec175facf75357
The official SMMUv3 DT bindings require a certain order of the
interrupts, Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: iommu@2ce00000: interrupt-names: 'oneOf' conditional failed, one must be fixed:
['eventq', 'cmdq-sync', 'gerror'] is too long
'combined' was expected
'gerror' was expected
'priq' was expected
'cmdq-sync' was expected
From schema: Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
============
Swap the order of the interrupts to improve bindings compliance.
Actually in this case the binding needs to be extended, since PRI is not
implemented in the SMMU in this case, so the PRI IRQ should be optional,
but we still want to describe the CMDQ sync IRQ. A patch for the binding
is pending.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I3978f1c087136cd4c2e8f7fd4d1bba5b95f72726
The official SMMUv3 DT bindings require a certain order of the
interrupts, Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: iommu@4f400000: interrupt-names: 'oneOf' conditional failed, one must be fixed:
['eventq', 'priq', 'cmdq-sync', 'gerror'] is too long
'combined' was expected
'gerror' was expected
'priq' was expected
'cmdq-sync' was expected
From schema: Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
============
Swap the order of the interrupt-names and their corresponding interrupts
values to improve bindings compliance.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I2110b8509593a4f1aadff11bd518ec4a0f3f5d3c
The core root node DT bindings require every DT to have a "model"
property. Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: /: 'model' is a required property
From schema: dt-schema.git/dtschema/schemas/root-node.yaml
============
Add a model name to both the SoC and FVP files to improve bindings
compliance.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I64923edb947f8939dfa24c13a37996b1ba34ea54
This is an SoM in SODIMM-200 format on an evaluation board called
"DHCOM Premium Developer Kit #2" (DHCOM PDK2 for short). The SoM features an
STM32MP157C SoC with 1 GB DDR3, 8 GB eMMC, microSD and 2 MB SPI flash.
The baseboard has multiple UART, USB, SPI, and I2C ports/headers and several
other interfaces that are not important for TF-A.
These dts(i) files are based on DHCOM dt's from Linux 5.16 and U-Boot 2022.01.
The DRAM calibration values are taken from U-Boot 2022.01 and are optimized for
industrial temperature range above 85° C.
TF-A on this board was fully tested with the latest OP-TEE developer setup.
Change-Id: I696c01742954d761fbad312cd1059e3ab01fa93c
Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
On STM32MP15, there is currently an OP-TEE shared memory area at the end
of the DDR. But this area will in term be removed. To allow a smooth
transition, a new flag is added (STM32MP15_OPTEE_RSV_SHM). It reflects
the OP-TEE flag: CFG_CORE_RESERVED_SHM. The flag is enabled by default
(no behavior change). It will be set to 0 when OP-TEE is aligned, and
then later be removed.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I91146cd8a26a24be22143c212362294c1e880264
Due to commit updating kernel yaml file [1], we need to align TF-A DT
files to what is done in kernel.
[1] c09acbc499e8 ("dt-bindings: pinctrl: use pinctrl.yaml")
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Id717162e42d3959339d6c01883e87a9d4399f5d9
With recent changes, TF-A now panics on MC-1, Avenger96 and Odyssey:
NOTICE: CPU: STM32MP157C?? Rev.B
NOTICE: Model: Linux Automation MC-1 board
ERROR: regul ldo3: max value 750 is invalid
PANIC at PC : 0x2ffeebb7
as the driver takes great offense at the content of the device
tree. The parts in question were copy-pasted from ST DTs, but
those ST DTs were fixed by commit 67d95409ba
("refactor(stm32mp1-fdts): update regulator description").
Fix the breakage by transplanting the same changes into all
remaining STM32MP1 DTs.
Change was boot-tested on MC-1, but only build tested for the
other two.
Fixes: bba9fdee58 ("feat(stm32mp1): add regulator framework compilation")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Change-Id: I143d0091625f62c313b3b71449c9ad99583d01c8
On STM32MP13, OP-TEE will be loaded at the beginning of the secure
memory, and will be responsible for its shared memory.
The memory allocated to OP-TEE is then 32MB, and the shared memory
does no more appear in the STM32MP13 fw-config DT file.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4e9238ddb4d82079b9ddf8fc8f6916b5b989d263
Remove the nvmem_layout node with compatible "st,stm32-nvmem-layout"
no more used in TF-A code to simplify the device tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I3748b20b7d3c60ee64ead15541fac1fd12656600
According to the DT spec, stdout-path must either start with the full
path to a node, or with an alias.
"soc_uart0" is neither of them, and consequently the Linux kernel
complains that it cannot find the root console device when just given
"earlycon" on the kernel command line:
===========
[ 0.000000] OF: fdt: earlycon: stdout-path soc_uart0 not found
===========
Use the already defined "serial0" alias to fix this and make "earlycon"
work in Linux.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie0ddb1909160c930af3831246f0140363bc0b5db
Add dedicated device tree files for STM32MP13.
Add new DDR compatible for STM32MP13x.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Ib1bb9ad8cb2ab9f5f81549635d6604093aeb99d3
To be able to load images with FIP and FCONF on STM32MP13,
the st-io_policies has to be filled.
It is a copy of the node in stm32mp15_bl2.dtsi .
Change-Id: Ia15f50d1179e9b8aefe621dc5e0070ea845d6aac
Signed-off-by: Yann Gautier <yann.gautier@st.com>
STM32MP13 is a single Cortex-A7 CPU, without co-processor.
As for STM32MP15x SoC family, STM32MP15x SoCs come with different
features, depending on SoC version. Each peripheral node is created.
Some are left empty for the moment , and will be filled later on.
Change-Id: I0166bb70dfa7f717e89e89883b059a5b873c4ef7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
* changes:
fix(sptool): add leading zeroes in UUID conversion
feat(tc): enable SMMU for DPU
feat(tc): add reserved memory region for Gralloc
feat(tc): enable GPU
fix(tc): remove the bootargs node
The SMMU needs to be enabled to support 8GB RAM
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ie81f2fc59886c52e9d6ed799ea73f49eb7a7c307
Gralloc for Android S uses dmabuf, we need to add reserved memory area
for these allocations
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: If869ac930fadc374ec435cae3847ba374584275b
Add DTS node for GPU to support hardware rendering in Android
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: I2cf2badf5b15e59a910f6cf7d3d30fdfaf4fe9ce
We need to keep the kernel command line in Yocto, otherwise we
can't support AVB.
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ic291eb13620b307f10354c2c2797c6fc9b053e83
Set non-secure property on platform secure OTP nodes that non-secure
world is allowed to access through secure world services.
These are the SoC MAC address and the ST boards board_id OTPs.
Most of these were already done but it was missing for ED1 board.
Change-Id: Idfa6322d9d5c35285706d0b2d32ae09af38684a7
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
A new nvmem_layout node includes nvmem platform-dependent layout
information, such as OTP NVMEM cell lists (phandle, name).
This list allows easy access to OTP offsets defined in BSEC node,
where more OTP definitions with offsets in bytes and length have
been added (replace hard-coded values).
Each board may redefine this list, especially for board_id info.
Change-Id: I910ae671b3bf3320ee6500fecc9ec335ae67bbda
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
If a board declares an mmc1 alias in its DT and is compiled without flags
STM32MP_EMMC or STM32MP_SDMMC, the DT will fail to build.
Add /delete-property/ mmc1; to correct this.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I1938ff99dc3d883f9174ee886f9ffa195ec60373
Total Compute has ETE and TRBE tracing components and they have
to be enabled to capture the execution trace of the processor.
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I3c86c11be2c655a61ecefa3eb2e4e3951577a113
The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when built-in calibration is executed.
The calibration parameters were provided in the device tree by the
optional node "st,phy-cal", activated in ddr helper file by the
compilation flag DDR_PHY_CAL_SKIP and filled with values generated
by CubeMX.
This patch
- updates the binding file to remove "st,phy-cal" support
- updates the device trees and remove the associated defines
- simplifies the STM32MP1 DDR driver and remove the support of
the optional "st,phy-cal"
After this patch the built-in calibration is always executed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I3fc445520c259f7f05730aefc25e64b328bf7159
Update regulator description to match with pmic driver updates.
vref_ddr does not support over-current protection.
vtt_ddr is set to sink source mode.
Change-Id: I725f35b091ca8c230994c2b5f81693ebc97bf4aa
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Add 'firmware' node in morello-soc.dts to expose SCMI
support to the kernel. The SCMI protocols supported at
the moment are SCMI Base, Clock and Perf (DVFS).
The current mailbox memory region in MHU SRAM has an issue
with any access not aligned to a 4-byte boundary. So, the SCMI
mailbox memory region has been relocated to AP non-trusted
RAM to get around the problem.
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Change-Id: Ibcbce8823b751a0fc3be7e9bc3588c1dc47ae024
Morello Specification specifies the system
reference clock frequency as 50MHz so the frequency
has been changed from 100MHz to 50MHz.
Change-Id: I25577b04aa54ed82b7e9df69ac8e40ac54a9b111
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* changes:
feat(arm_fpga): write UART baud base clock frequency into DTB
feat(arm_fpga): query PL011 to learn system frequency
refactor(arm_fpga): move command line code into separate function
fix(fdt): avoid output on missing DT property
feat(arm_fpga): add ITS autodetection
feat(arm_fpga): determine GICR base by probing
feat(gicv3): introduce GIC component identification
feat(libfdt): also allow changing base address
fix(arm_fpga): avoid re-linking from executable ELF file
Add 2021 year in the file header Copyright line.
Change-Id: I09f7bef1f746c429ff308286169354e58648a1cd
Signed-off-by: Yann Gautier <yann.gautier@st.com>
About a year ago there was a change in the underlying Arm platform design
framework, which lead to a reorganisation of the interrupt map (to make
room for multi-chip designs).
This lead to the PL011 debug UART interrupt to move from SPI 115 to SPI
415. Unfortunately there is not a good or easy way to auto-detect this
change: Flooding the TX FIFO and checking GICD_ISPENDR registers might
be possible, but sounds a bit over the top for BL31.
So we would need to break one group of images: newer ones, as we do right
now, or older ones.
By now every interesting FPGA image seems to use the newer IRQ, so in
the interest of having a smooth experience for most users, lets switch
to this IRQ.
When people are interested in older images, they can either change the
number back in the .dts file, or provide a patched DTB on the FPGA
command line.
Change-Id: I3c7e7b711f5142813bd94eecde3095a4fc555bb3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The Arm FPGAs run in mostly one clock domain, which is used for the CPU
cores, the generic timer, and also the UART baudrate base clock. This
single clock can have different rates, to compensate for different IP
complexity. So far most images used 10 MHz, but different rates start to
appear.
To avoid patching both the arch timer frequency and UART baud base fixed
clock in the DTB manually, we would like to set the clock rate
automatically. Fortunately the SCP firmware has the actual clock rate
hard coded, and already programs the PL011 UART baud divider register
with the correct value to achieve a 38400 bps baudrate.
So read the two PL011 baudrate divider values and re-calculate the
original base clock from there, to use as the arch timer frequency. If
the arch timer DT node contains a clock-frequency property, we use that
instead, to support overriding and disabling this autodetection.
Change-Id: I9857fbb418deb4644aeb2816f1102796f9bfd3bb
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
