mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-13 08:04:27 +00:00
feat(stm32mp15-fdts): add Avenger96 board with STM32MP157A DHCOR SoM
This should replace the stm32mp157a-avenger96.dts with the new device tree files split into the STM32MP15 DHCOR SoM definition and the Avenger96 baseboard like it's done in Linux and U-Boot. Differences to stm32mp157a-avenger96.dts: - Enable sdmmc2 for booting from eMMC - improved clock settings like in U-Boot commit b6055945 "ARM: dts: stm32: Adjust PLL4 settings on AV96 again" - improved DDR settings for DHSOMs like in U-Boot commit 92ca0f74 "ARM: dts: stm32: Synchronize DDR setttings on DH SoMs" TF-A with this new dts(i) files on this board was fully tested with the latest OP-TEE developer setup. Change-Id: I85ce8eca7747965af3555fc19fd7b192dc3e5740 Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
This commit is contained in:
Johann Neuhauser
Madhukar Pappireddy
parent
0c0bab0cb4
commit
51e223058f
6 changed files with 474 additions and 0 deletions
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@ -120,6 +120,21 @@
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};
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};
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sdmmc1_dir_pins_b: sdmmc1-dir-1 {
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pins1 {
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pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
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<STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */
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<STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
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slew-rate = <1>;
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drive-push-pull;
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bias-pull-up;
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};
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pins2{
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pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
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bias-pull-up;
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};
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};
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sdmmc2_b4_pins_a: sdmmc2-b4-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
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@ -182,6 +197,18 @@
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};
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};
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sdmmc2_d47_pins_c: sdmmc2-d47-2 {
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pins {
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pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
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<STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
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<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
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<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
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slew-rate = <1>;
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drive-push-pull;
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bias-pull-up;
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};
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};
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sdmmc2_d47_pins_d: sdmmc2-d47-3 {
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pins {
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pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
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7
fdts/stm32mp157a-dhcor-avenger96-fw-config.dts
Normal file
7
fdts/stm32mp157a-dhcor-avenger96-fw-config.dts
Normal file
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@ -0,0 +1,7 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (c) 2020-2021, STMicroelectronics - All Rights Reserved
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*/
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#define DDR_SIZE 0x40000000 /* 1GB */
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#include "stm32mp15-fw-config.dtsi"
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24
fdts/stm32mp157a-dhcor-avenger96.dts
Normal file
24
fdts/stm32mp157a-dhcor-avenger96.dts
Normal file
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@ -0,0 +1,24 @@
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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* Copyright (C) 2020 Marek Vasut <marex@denx.de>
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* Copyright (C) 2022 DH electronics GmbH
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*
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* DHCOR STM32MP1 variant:
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* DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG
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* DHCOR PCB number: 586-100 or newer
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* Avenger96 PCB number: 588-200 or newer
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*/
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/dts-v1/;
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#include "stm32mp157.dtsi"
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#include "stm32mp15xx-dhcor-som.dtsi"
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#include "stm32mp15xx-dhcor-avenger96.dtsi"
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/ {
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model = "Arrow Electronics STM32MP157A Avenger96 board";
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compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som",
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"st,stm32mp157";
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};
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100
fdts/stm32mp15xx-dhcor-avenger96.dtsi
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100
fdts/stm32mp15xx-dhcor-avenger96.dtsi
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@ -0,0 +1,100 @@
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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* Copyright (C) 2020 Marek Vasut <marex@denx.de>
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* Copyright (C) 2022 DH electronics GmbH
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*/
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/* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */
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#include "stm32mp15xx-dhcor-io1v8.dtsi"
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/ {
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aliases {
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serial0 = &uart4;
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serial1 = &uart7;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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sd_switch: regulator-sd_switch {
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compatible = "regulator-gpio";
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regulator-name = "sd_switch";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <2900000>;
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regulator-type = "voltage";
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regulator-always-on;
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gpios = <&gpioi 5 0>;
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gpios-states = <0>;
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states = <1800000 0x1>,
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<2900000 0x0>;
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};
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};
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&sdmmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
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disable-wp;
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st,sig-dir;
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st,neg-edge;
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st,use-ckin;
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bus-width = <4>;
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vmmc-supply = <&vdd_sd>;
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vqmmc-supply = <&sd_switch>;
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status = "okay";
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};
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&sdmmc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
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bus-width = <8>;
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mmc-ddr-1_8v;
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no-sd;
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no-sdio;
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non-removable;
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st,neg-edge;
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vmmc-supply = <&v3v3>;
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vqmmc-supply = <&vdd_io>;
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status = "okay";
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};
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&uart4 {
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/* On Low speed expansion header */
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label = "LS-UART1";
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pinctrl-names = "default";
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pinctrl-0 = <&uart4_pins_b>;
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status = "okay";
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};
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&uart7 {
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/* On Low speed expansion header */
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label = "LS-UART0";
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pinctrl-names = "default";
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pinctrl-0 = <&uart7_pins_a>;
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uart-has-rtscts;
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status = "okay";
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};
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&usbotg_hs {
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pinctrl-0 = <&usbotg_hs_pins_a>;
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pinctrl-names = "default";
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phy-names = "usb2-phy";
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phys = <&usbphyc_port1 0>;
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status = "okay";
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vbus-supply = <&vbus_otg>;
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};
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&usbphyc {
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status = "okay";
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};
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&usbphyc_port0 {
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phy-supply = <&vdd_usb>;
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};
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&usbphyc_port1 {
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phy-supply = <&vdd_usb>;
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};
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28
fdts/stm32mp15xx-dhcor-io1v8.dtsi
Normal file
28
fdts/stm32mp15xx-dhcor-io1v8.dtsi
Normal file
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@ -0,0 +1,28 @@
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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/*
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* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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* Copyright (C) 2020 Marek Vasut <marex@denx.de>
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*/
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/ {
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/* Enpirion EP3A8LQI U2 on the DHCOR */
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vdd_io: regulator-buck-io {
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compatible = "regulator-fixed";
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regulator-name = "buck-io";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vdd>;
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};
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};
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&vdd {
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <2900000>;
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};
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&pwr_regulators {
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vdd-supply = <&vdd_io>;
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};
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288
fdts/stm32mp15xx-dhcor-som.dtsi
Normal file
288
fdts/stm32mp15xx-dhcor-som.dtsi
Normal file
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@ -0,0 +1,288 @@
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (C) Linaro Ltd 2019 - All Rights Reserved
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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* Copyright (C) 2020 Marek Vasut <marex@denx.de>
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* Copyright (C) 2022 DH electronics GmbH
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*/
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#include "stm32mp15-pinctrl.dtsi"
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#include "stm32mp15xxaa-pinctrl.dtsi"
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
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/ {
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memory@c0000000 {
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device_type = "memory";
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reg = <0xc0000000 0x40000000>;
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};
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};
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&cpu0 {
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cpu-supply = <&vddcore>;
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};
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&cpu1 {
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cpu-supply = <&vddcore>;
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};
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&hash1 {
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status = "okay";
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_pins_a>;
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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status = "okay";
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pmic: stpmic@33 {
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compatible = "st,stpmic1";
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reg = <0x33>;
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interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "okay";
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regulators {
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compatible = "st,stpmic1-regulators";
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ldo1-supply = <&v3v3>;
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ldo2-supply = <&v3v3>;
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ldo3-supply = <&vdd_ddr>;
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ldo5-supply = <&v3v3>;
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ldo6-supply = <&v3v3>;
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pwr_sw1-supply = <&bst_out>;
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pwr_sw2-supply = <&bst_out>;
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vddcore: buck1 {
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regulator-name = "vddcore";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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vdd_ddr: buck2 {
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regulator-name = "vdd_ddr";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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vdd: buck3 {
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regulator-name = "vdd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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v3v3: buck4 {
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regulator-name = "v3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-over-current-protection;
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regulator-initial-mode = <0>;
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};
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vdda: ldo1 {
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regulator-name = "vdda";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <2900000>;
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};
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v2v8: ldo2 {
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regulator-name = "v2v8";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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};
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vtt_ddr: ldo3 {
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regulator-name = "vtt_ddr";
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regulator-always-on;
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regulator-over-current-protection;
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st,regulator-sink-source;
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};
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vdd_usb: ldo4 {
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regulator-name = "vdd_usb";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vdd_sd: ldo5 {
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regulator-name = "vdd_sd";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <2900000>;
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regulator-boot-on;
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};
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v1v8: ldo6 {
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regulator-name = "v1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-enable-ramp-delay = <300000>;
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};
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vref_ddr: vref_ddr {
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regulator-name = "vref_ddr";
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regulator-always-on;
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};
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bst_out: boost {
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regulator-name = "bst_out";
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};
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vbus_otg: pwr_sw1 {
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regulator-name = "vbus_otg";
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regulator-active-discharge = <1>;
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};
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vbus_sw: pwr_sw2 {
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regulator-name = "vbus_sw";
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regulator-active-discharge = <1>;
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};
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};
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};
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};
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&iwdg2 {
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timeout-sec = <32>;
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status = "okay";
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secure-status = "okay";
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};
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&pwr_regulators {
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vdd-supply = <&vdd>;
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vdd_3v3_usbfs-supply = <&vdd_usb>;
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};
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&qspi {
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pinctrl-names = "default";
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pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
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reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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flash0: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <50000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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&rcc {
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secure-status = "disabled";
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_MCU_PLL3P
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CLK_PLL12_HSE
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CLK_PLL3_HSE
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CLK_PLL4_HSE
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CLK_RTC_LSE
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CLK_MCO1_DISABLED
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CLK_MCO2_DISABLED
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>;
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st,clkdiv = <
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1 /*MPU*/
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0 /*AXI*/
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0 /*MCU*/
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1 /*APB1*/
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1 /*APB2*/
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1 /*APB3*/
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1 /*APB4*/
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2 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
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0 /*MCO2*/
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>;
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st,pkcs = <
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CLK_CKPER_HSE
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CLK_FMC_ACLK
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CLK_QSPI_ACLK
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CLK_ETH_DISABLED
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CLK_SDMMC12_PLL4P
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CLK_DSI_DSIPLL
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CLK_STGEN_HSE
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CLK_USBPHY_HSE
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CLK_SPI2S1_PLL3Q
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CLK_SPI2S23_PLL3Q
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CLK_SPI45_HSI
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CLK_SPI6_HSI
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CLK_I2C46_HSI
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CLK_SDMMC3_PLL4P
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CLK_USBO_USBPHY
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CLK_ADC_CKPER
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CLK_CEC_LSE
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CLK_I2C12_HSI
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CLK_I2C35_HSI
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CLK_UART1_HSI
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CLK_UART24_HSI
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CLK_UART35_HSI
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CLK_UART6_HSI
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CLK_UART78_HSI
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CLK_SPDIF_PLL4P
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CLK_FDCAN_PLL4R
|
||||
CLK_SAI1_PLL3Q
|
||||
CLK_SAI2_PLL3Q
|
||||
CLK_SAI3_PLL3Q
|
||||
CLK_SAI4_PLL3Q
|
||||
CLK_RNG1_LSI
|
||||
CLK_RNG2_LSI
|
||||
CLK_LPTIM1_PCLK1
|
||||
CLK_LPTIM23_PCLK3
|
||||
CLK_LPTIM45_LSE
|
||||
>;
|
||||
|
||||
/* VCO = 1300.0 MHz => P = 650 (CPU) */
|
||||
pll1: st,pll@0 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <0>;
|
||||
cfg = <2 80 0 0 0 PQR(1,0,0)>;
|
||||
frac = <0x800>;
|
||||
};
|
||||
|
||||
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
|
||||
pll2: st,pll@1 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <1>;
|
||||
cfg = <2 65 1 0 0 PQR(1,1,1)>;
|
||||
frac = <0x1400>;
|
||||
};
|
||||
|
||||
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
|
||||
pll3: st,pll@2 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <2>;
|
||||
cfg = <1 33 1 16 36 PQR(1,1,1)>;
|
||||
frac = <0x1a04>;
|
||||
};
|
||||
|
||||
/* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
|
||||
pll4: st,pll@3 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <3>;
|
||||
cfg = <3 98 5 7 5 PQR(1,1,1)>;
|
||||
};
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue