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feat(stm32mp15-fdts): add support for STM32MP157C based DHCOM SoM on PDK2 board
This is an SoM in SODIMM-200 format on an evaluation board called "DHCOM Premium Developer Kit #2" (DHCOM PDK2 for short). The SoM features an STM32MP157C SoC with 1 GB DDR3, 8 GB eMMC, microSD and 2 MB SPI flash. The baseboard has multiple UART, USB, SPI, and I2C ports/headers and several other interfaces that are not important for TF-A. These dts(i) files are based on DHCOM dt's from Linux 5.16 and U-Boot 2022.01. The DRAM calibration values are taken from U-Boot 2022.01 and are optimized for industrial temperature range above 85° C. TF-A on this board was fully tested with the latest OP-TEE developer setup. Change-Id: I696c01742954d761fbad312cd1059e3ab01fa93c Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
This commit is contained in:
Johann Neuhauser
parent
a1a2b6d1e2
commit
eef485abb1
5 changed files with 535 additions and 0 deletions
120
fdts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi
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120
fdts/stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi
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@ -0,0 +1,120 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright (C) 2020, DH electronics - All Rights Reserved
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*
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* STM32MP15xx DHSOM configuration
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* 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
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* Reference used W634GU6NB15I from Winbond
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*
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* DDR type / Platform DDR3/3L
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* freq 533MHz
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* width 32
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* datasheet 0 = W634GU6NB15I / DDR3-1333
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* DDR density 8
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* timing mode optimized
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* address mapping : RBC
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* Tc > + 85C : J
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*/
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#define DDR_MEM_NAME "DDR3L 32bits 2x4Gb 533MHz"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x40000000
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#define DDR_MSTR 0x00040401
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#define DDR_MRCTRL0 0x00000010
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#define DDR_MRCTRL1 0x00000000
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#define DDR_DERATEEN 0x00000000
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#define DDR_DERATEINT 0x00800000
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#define DDR_PWRCTL 0x00000000
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#define DDR_PWRTMG 0x00400010
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#define DDR_HWLPCTL 0x00000000
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#define DDR_RFSHCTL0 0x00210000
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#define DDR_RFSHCTL3 0x00000000
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#define DDR_RFSHTMG 0x0040008B
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#define DDR_CRCPARCTL0 0x00000000
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#define DDR_DRAMTMG0 0x121B1214
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#define DDR_DRAMTMG1 0x000A041C
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#define DDR_DRAMTMG2 0x0608090F
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#define DDR_DRAMTMG3 0x0050400C
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#define DDR_DRAMTMG4 0x08040608
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#define DDR_DRAMTMG5 0x06060403
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#define DDR_DRAMTMG6 0x02020002
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#define DDR_DRAMTMG7 0x00000202
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#define DDR_DRAMTMG8 0x00001005
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#define DDR_DRAMTMG14 0x000000A0
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#define DDR_ZQCTL0 0xC2000040
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#define DDR_DFITMG0 0x02060105
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#define DDR_DFITMG1 0x00000202
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#define DDR_DFILPCFG0 0x07000000
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#define DDR_DFIUPD0 0xC0400003
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#define DDR_DFIUPD1 0x00000000
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#define DDR_DFIUPD2 0x00000000
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#define DDR_DFIPHYMSTR 0x00000000
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#define DDR_ODTCFG 0x06000600
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#define DDR_ODTMAP 0x00000001
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#define DDR_SCHED 0x00000C01
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#define DDR_SCHED1 0x00000000
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#define DDR_PERFHPR1 0x01000001
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#define DDR_PERFLPR1 0x08000200
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#define DDR_PERFWR1 0x08000400
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#define DDR_DBG0 0x00000000
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#define DDR_DBG1 0x00000000
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#define DDR_DBGCMD 0x00000000
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#define DDR_POISONCFG 0x00000000
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#define DDR_PCCFG 0x00000010
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#define DDR_PCFGR_0 0x00010000
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#define DDR_PCFGW_0 0x00000000
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#define DDR_PCFGQOS0_0 0x02100C03
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#define DDR_PCFGQOS1_0 0x00800100
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#define DDR_PCFGWQOS0_0 0x01100C03
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#define DDR_PCFGWQOS1_0 0x01000200
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#define DDR_PCFGR_1 0x00010000
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#define DDR_PCFGW_1 0x00000000
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#define DDR_PCFGQOS0_1 0x02100C03
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#define DDR_PCFGQOS1_1 0x00800040
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#define DDR_PCFGWQOS0_1 0x01100C03
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#define DDR_PCFGWQOS1_1 0x01000200
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#define DDR_ADDRMAP1 0x00080808
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#define DDR_ADDRMAP2 0x00000000
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#define DDR_ADDRMAP3 0x00000000
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#define DDR_ADDRMAP4 0x00001F1F
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#define DDR_ADDRMAP5 0x07070707
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#define DDR_ADDRMAP6 0x0F070707
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#define DDR_ADDRMAP9 0x00000000
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#define DDR_ADDRMAP10 0x00000000
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#define DDR_ADDRMAP11 0x00000000
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#define DDR_PGCR 0x01442E02
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#define DDR_PTR0 0x0022AA5B
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#define DDR_PTR1 0x04841104
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#define DDR_PTR2 0x042DA068
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#define DDR_ACIOCR 0x10400812
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#define DDR_DXCCR 0x00000C40
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#define DDR_DSGCR 0xF200011F
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#define DDR_DCR 0x0000000B
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#define DDR_DTPR0 0x38D488D0
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#define DDR_DTPR1 0x098B00D8
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#define DDR_DTPR2 0x10023600
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#define DDR_MR0 0x00000840
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#define DDR_MR1 0x00000000
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#define DDR_MR2 0x00000248
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#define DDR_MR3 0x00000000
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#define DDR_ODTCR 0x00010000
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0DLLCR 0x40000000
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#define DDR_DX0DQTR 0xFFFFFFFF
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#define DDR_DX0DQSTR 0x3DB02000
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1DLLCR 0x40000000
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#define DDR_DX1DQTR 0xFFFFFFFF
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#define DDR_DX1DQSTR 0x3DB02000
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#define DDR_DX2GCR 0x0000CE81
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#define DDR_DX2DLLCR 0x40000000
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#define DDR_DX2DQTR 0xFFFFFFFF
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#define DDR_DX2DQSTR 0x3DB02000
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#define DDR_DX3GCR 0x0000CE81
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#define DDR_DX3DLLCR 0x40000000
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#define DDR_DX3DQTR 0xFFFFFFFF
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#define DDR_DX3DQSTR 0x3DB02000
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#include "stm32mp15-ddr.dtsi"
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7
fdts/stm32mp157c-dhcom-pdk2-fw-config.dts
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7
fdts/stm32mp157c-dhcom-pdk2-fw-config.dts
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@ -0,0 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright (c) 2022 DH electronics GmbH
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*/
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#define DDR_SIZE 0x40000000 /* 1GB */
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#include "stm32mp15-fw-config.dtsi"
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26
fdts/stm32mp157c-dhcom-pdk2.dts
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26
fdts/stm32mp157c-dhcom-pdk2.dts
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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
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* Copyright (C) 2022 DH electronics GmbH
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*
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* DHCOM STM32MP1 variant:
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* DHCM-STM32MP157C-C065-R102-F0819-SPI-E2-CAN2-SDR104-RTC-WBT-T-DSI-I-01D2
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* DHCOM PCB number: 587-200 or newer
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* PDK2 PCB number: 516-400 or newer
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*/
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/dts-v1/;
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#include "stm32mp157.dtsi"
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#include "stm32mp15xc.dtsi"
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#include "stm32mp15xx-dhcom-som.dtsi"
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#include "stm32mp15xx-dhcom-pdk2.dtsi"
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/ {
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model = "DH electronics STM32MP157C DHCOM Premium Developer Kit (2)";
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compatible = "dh,stm32mp157c-dhcom-pdk2", "dh,stm32mp157c-dhcom-som",
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"st,stm32mp157";
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};
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&cryp1 {
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status = "okay";
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};
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44
fdts/stm32mp15xx-dhcom-pdk2.dtsi
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44
fdts/stm32mp15xx-dhcom-pdk2.dtsi
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@ -0,0 +1,44 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
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* Copyright (C) 2022 DH electronics GmbH
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*/
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/ {
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aliases {
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serial0 = &uart4;
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serial1 = &usart3;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&usart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&usart3_pins_a>;
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status = "okay";
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};
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&usbotg_hs {
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dr_mode = "otg";
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pinctrl-0 = <&usbotg_hs_pins_a>;
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pinctrl-names = "default";
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phy-names = "usb2-phy";
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phys = <&usbphyc_port1 0>;
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vbus-supply = <&vbus_otg>;
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status = "okay";
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};
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&usbphyc {
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status = "okay";
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};
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&usbphyc_port0 {
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phy-supply = <&vdd_usb>;
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};
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&usbphyc_port1 {
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phy-supply = <&vdd_usb>;
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};
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338
fdts/stm32mp15xx-dhcom-som.dtsi
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338
fdts/stm32mp15xx-dhcom-som.dtsi
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@ -0,0 +1,338 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
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* Copyright (C) 2022 DH electronics GmbH
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*/
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#include "stm32mp15-pinctrl.dtsi"
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#include "stm32mp15xxaa-pinctrl.dtsi"
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
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/ {
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memory@c0000000 {
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device_type = "memory";
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reg = <0xC0000000 0x40000000>;
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};
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};
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&bsec {
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board_id: board_id@ec {
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reg = <0xec 0x4>;
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st,non-secure-otp;
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};
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};
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&cpu0{
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cpu-supply = <&vddcore>;
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};
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&cpu1{
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cpu-supply = <&vddcore>;
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};
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&hash1 {
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status = "okay";
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_pins_a>;
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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status = "okay";
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pmic: stpmic@33 {
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compatible = "st,stpmic1";
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reg = <0x33>;
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interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "okay";
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regulators {
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compatible = "st,stpmic1-regulators";
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ldo1-supply = <&v3v3>;
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ldo2-supply = <&v3v3>;
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ldo3-supply = <&vdd_ddr>;
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ldo5-supply = <&v3v3>;
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ldo6-supply = <&v3v3>;
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pwr_sw1-supply = <&bst_out>;
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pwr_sw2-supply = <&bst_out>;
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vddcore: buck1 {
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regulator-name = "vddcore";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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vdd_ddr: buck2 {
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regulator-name = "vdd_ddr";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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vdd: buck3 {
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regulator-name = "vdd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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st,mask-reset;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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v3v3: buck4 {
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regulator-name = "v3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-over-current-protection;
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regulator-initial-mode = <0>;
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};
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vdda: ldo1 {
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regulator-name = "vdda";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <2900000>;
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regulator-always-on;
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};
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v2v8: ldo2 {
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regulator-name = "v2v8";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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};
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vtt_ddr: ldo3 {
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regulator-name = "vtt_ddr";
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regulator-always-on;
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regulator-over-current-protection;
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st,regulator-sink-source;
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};
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vdd_usb: ldo4 {
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regulator-name = "vdd_usb";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vdd_sd: ldo5 {
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regulator-name = "vdd_sd";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <2900000>;
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regulator-boot-on;
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};
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v1v8: ldo6 {
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regulator-name = "v1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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vref_ddr: vref_ddr {
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regulator-name = "vref_ddr";
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regulator-always-on;
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};
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bst_out: boost {
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regulator-name = "bst_out";
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};
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vbus_otg: pwr_sw1 {
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regulator-name = "vbus_otg";
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};
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vbus_sw: pwr_sw2 {
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regulator-name = "vbus_sw";
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regulator-active-discharge = <1>;
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};
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};
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};
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};
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&iwdg2 {
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timeout-sec = <32>;
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status = "okay";
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secure-status = "okay";
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};
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&pwr_regulators {
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vdd-supply = <&vdd>;
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vdd_3v3_usbfs-supply = <&vdd_usb>;
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};
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&qspi {
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pinctrl-names = "default";
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pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
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reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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flash0: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <108000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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&rcc {
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secure-status = "disabled";
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_MCU_PLL3P
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CLK_PLL12_HSE
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CLK_PLL3_HSE
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CLK_PLL4_HSE
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CLK_RTC_LSE
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CLK_MCO1_DISABLED
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CLK_MCO2_PLL4P
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>;
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st,clkdiv = <
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1 /*MPU*/
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0 /*AXI*/
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0 /*MCU*/
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1 /*APB1*/
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1 /*APB2*/
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1 /*APB3*/
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1 /*APB4*/
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2 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
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1 /*MCO2*/
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>;
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st,pkcs = <
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CLK_CKPER_HSE
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CLK_FMC_ACLK
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CLK_QSPI_ACLK
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CLK_ETH_PLL4P
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CLK_SDMMC12_PLL4P
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CLK_DSI_DSIPLL
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CLK_STGEN_HSE
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CLK_USBPHY_HSE
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CLK_SPI2S1_PLL3Q
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CLK_SPI2S23_PLL3Q
|
||||
CLK_SPI45_HSI
|
||||
CLK_SPI6_HSI
|
||||
CLK_I2C46_HSI
|
||||
CLK_SDMMC3_PLL4P
|
||||
CLK_USBO_USBPHY
|
||||
CLK_ADC_CKPER
|
||||
CLK_CEC_LSE
|
||||
CLK_I2C12_HSI
|
||||
CLK_I2C35_HSI
|
||||
CLK_UART1_HSI
|
||||
CLK_UART24_HSI
|
||||
CLK_UART35_HSI
|
||||
CLK_UART6_HSI
|
||||
CLK_UART78_HSI
|
||||
CLK_SPDIF_PLL4P
|
||||
CLK_FDCAN_PLL4R
|
||||
CLK_SAI1_PLL3Q
|
||||
CLK_SAI2_PLL3Q
|
||||
CLK_SAI3_PLL3Q
|
||||
CLK_SAI4_PLL3Q
|
||||
CLK_RNG1_LSI
|
||||
CLK_RNG2_LSI
|
||||
CLK_LPTIM1_PCLK1
|
||||
CLK_LPTIM23_PCLK3
|
||||
CLK_LPTIM45_LSE
|
||||
>;
|
||||
|
||||
/* VCO = 1300.0 MHz => P = 650 (CPU) */
|
||||
pll1: st,pll@0 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <0>;
|
||||
cfg = <2 80 0 0 0 PQR(1,0,0)>;
|
||||
frac = <0x800>;
|
||||
};
|
||||
|
||||
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
|
||||
pll2: st,pll@1 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <1>;
|
||||
cfg = <2 65 1 0 0 PQR(1,1,1)>;
|
||||
frac = <0x1400>;
|
||||
};
|
||||
|
||||
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
|
||||
pll3: st,pll@2 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <2>;
|
||||
cfg = <1 33 1 16 36 PQR(1,1,1)>;
|
||||
frac = <0x1a04>;
|
||||
};
|
||||
|
||||
/* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
|
||||
pll4: st,pll@3 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <3>;
|
||||
cfg = <1 49 5 11 11 PQR(1,1,1)>;
|
||||
};
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
||||
disable-wp;
|
||||
st,sig-dir;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&vdd_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1_b4_pins_a {
|
||||
/*
|
||||
* SD bus pull-up resistors:
|
||||
* - optional on SoMs with SD voltage translator
|
||||
* - mandatory on SoMs without SD voltage translator
|
||||
*/
|
||||
pins1 {
|
||||
bias-pull-up;
|
||||
};
|
||||
pins2 {
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
st,neg-edge;
|
||||
bus-width = <8>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
vqmmc-supply = <&v3v3>;
|
||||
mmc-ddr-3_3v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue