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feat(stm32mp1-fdts): add DDR support for STM32MP13
Add dedicated device tree files for STM32MP13. Add new DDR compatible for STM32MP13x. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Change-Id: Ib1bb9ad8cb2ab9f5f81549635d6604093aeb99d3
This commit is contained in:
Nicolas Le Bayon
Yann Gautier
parent
2bea35122d
commit
e6fddbc995
4 changed files with 304 additions and 0 deletions
184
fdts/stm32mp13-ddr.dtsi
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184
fdts/stm32mp13-ddr.dtsi
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@ -0,0 +1,184 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
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*/
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&ddr {
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st,mem-name = DDR_MEM_NAME;
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st,mem-speed = <DDR_MEM_SPEED>;
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st,mem-size = <DDR_MEM_SIZE>;
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st,ctl-reg = <
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DDR_MSTR
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DDR_MRCTRL0
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DDR_MRCTRL1
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DDR_DERATEEN
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DDR_DERATEINT
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DDR_PWRCTL
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DDR_PWRTMG
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DDR_HWLPCTL
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DDR_RFSHCTL0
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DDR_RFSHCTL3
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DDR_CRCPARCTL0
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DDR_ZQCTL0
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DDR_DFITMG0
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DDR_DFITMG1
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DDR_DFILPCFG0
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DDR_DFIUPD0
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DDR_DFIUPD1
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DDR_DFIUPD2
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DDR_DFIPHYMSTR
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DDR_ODTMAP
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DDR_DBG0
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DDR_DBG1
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DDR_DBGCMD
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DDR_POISONCFG
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DDR_PCCFG
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>;
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st,ctl-timing = <
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DDR_RFSHTMG
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DDR_DRAMTMG0
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DDR_DRAMTMG1
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DDR_DRAMTMG2
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DDR_DRAMTMG3
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DDR_DRAMTMG4
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DDR_DRAMTMG5
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DDR_DRAMTMG6
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DDR_DRAMTMG7
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DDR_DRAMTMG8
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DDR_DRAMTMG14
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DDR_ODTCFG
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>;
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st,ctl-map = <
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DDR_ADDRMAP1
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DDR_ADDRMAP2
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DDR_ADDRMAP3
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DDR_ADDRMAP4
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DDR_ADDRMAP5
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DDR_ADDRMAP6
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DDR_ADDRMAP9
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DDR_ADDRMAP10
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DDR_ADDRMAP11
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>;
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st,ctl-perf = <
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DDR_SCHED
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DDR_SCHED1
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DDR_PERFHPR1
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DDR_PERFLPR1
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DDR_PERFWR1
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DDR_PCFGR_0
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DDR_PCFGW_0
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DDR_PCFGQOS0_0
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DDR_PCFGQOS1_0
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DDR_PCFGWQOS0_0
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DDR_PCFGWQOS1_0
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>;
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st,phy-reg = <
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DDR_PGCR
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DDR_ACIOCR
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DDR_DXCCR
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DDR_DSGCR
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DDR_DCR
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DDR_ODTCR
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DDR_ZQ0CR1
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DDR_DX0GCR
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DDR_DX1GCR
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>;
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st,phy-timing = <
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DDR_PTR0
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DDR_PTR1
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DDR_PTR2
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DDR_DTPR0
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DDR_DTPR1
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DDR_DTPR2
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DDR_MR0
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DDR_MR1
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DDR_MR2
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DDR_MR3
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>;
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};
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#undef DDR_MEM_NAME
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#undef DDR_MEM_SPEED
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#undef DDR_MEM_SIZE
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#undef DDR_MSTR
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#undef DDR_MRCTRL0
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#undef DDR_MRCTRL1
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#undef DDR_DERATEEN
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#undef DDR_DERATEINT
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#undef DDR_PWRCTL
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#undef DDR_PWRTMG
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#undef DDR_HWLPCTL
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#undef DDR_RFSHCTL0
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#undef DDR_RFSHCTL3
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#undef DDR_RFSHTMG
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#undef DDR_CRCPARCTL0
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#undef DDR_DRAMTMG0
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#undef DDR_DRAMTMG1
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#undef DDR_DRAMTMG2
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#undef DDR_DRAMTMG3
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#undef DDR_DRAMTMG4
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#undef DDR_DRAMTMG5
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#undef DDR_DRAMTMG6
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#undef DDR_DRAMTMG7
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#undef DDR_DRAMTMG8
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#undef DDR_DRAMTMG14
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#undef DDR_ZQCTL0
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#undef DDR_DFITMG0
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#undef DDR_DFITMG1
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#undef DDR_DFILPCFG0
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#undef DDR_DFIUPD0
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#undef DDR_DFIUPD1
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#undef DDR_DFIUPD2
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#undef DDR_DFIPHYMSTR
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#undef DDR_ADDRMAP1
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#undef DDR_ADDRMAP2
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#undef DDR_ADDRMAP3
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#undef DDR_ADDRMAP4
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#undef DDR_ADDRMAP5
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#undef DDR_ADDRMAP6
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#undef DDR_ADDRMAP9
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#undef DDR_ADDRMAP10
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#undef DDR_ADDRMAP11
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#undef DDR_ODTCFG
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#undef DDR_ODTMAP
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#undef DDR_SCHED
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#undef DDR_SCHED1
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#undef DDR_PERFHPR1
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#undef DDR_PERFLPR1
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#undef DDR_PERFWR1
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#undef DDR_DBG0
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#undef DDR_DBG1
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#undef DDR_DBGCMD
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#undef DDR_POISONCFG
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#undef DDR_PCCFG
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#undef DDR_PCFGR_0
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#undef DDR_PCFGW_0
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#undef DDR_PCFGQOS0_0
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#undef DDR_PCFGQOS1_0
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#undef DDR_PCFGWQOS0_0
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#undef DDR_PCFGWQOS1_0
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#undef DDR_PGCR
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#undef DDR_PTR0
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#undef DDR_PTR1
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#undef DDR_PTR2
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#undef DDR_ACIOCR
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#undef DDR_DXCCR
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#undef DDR_DSGCR
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#undef DDR_DCR
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#undef DDR_DTPR0
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#undef DDR_DTPR1
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#undef DDR_DTPR2
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#undef DDR_MR0
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#undef DDR_MR1
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#undef DDR_MR2
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#undef DDR_MR3
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#undef DDR_ODTCR
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#undef DDR_ZQ0CR1
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#undef DDR_DX0GCR
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#undef DDR_DX1GCR
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100
fdts/stm32mp13-ddr3-1x4Gb-1066-binF.dtsi
Normal file
100
fdts/stm32mp13-ddr3-1x4Gb-1066-binF.dtsi
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@ -0,0 +1,100 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
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*
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* STM32MP135C DISCO BOARD configuration
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* 1x DDR3L 4Gb, 16-bit, 533MHz.
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* Reference used MT41K256M16TW-107 P from Micron
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*
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* DDR type / Platform DDR3/3L
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* freq 533MHz
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* width 16
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* datasheet 1
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* DDR density 4
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* timing mode optimized
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* Scheduling/QoS options : type = 6
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* address mapping : RBC
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* Tc > + 85C : N
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*/
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#define DDR_MEM_NAME "DDR3-1066 bin F 1x4Gb 533MHz v1.53"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x20000000
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#define DDR_MSTR 0x00040401
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#define DDR_MRCTRL0 0x00000010
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#define DDR_MRCTRL1 0x00000000
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#define DDR_DERATEEN 0x00000000
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#define DDR_DERATEINT 0x00800000
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#define DDR_PWRCTL 0x00000000
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#define DDR_PWRTMG 0x00400010
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#define DDR_HWLPCTL 0x00000000
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#define DDR_RFSHCTL0 0x00210000
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#define DDR_RFSHCTL3 0x00000000
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#define DDR_RFSHTMG 0x0081008B
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#define DDR_CRCPARCTL0 0x00000000
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#define DDR_DRAMTMG0 0x121B2414
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#define DDR_DRAMTMG1 0x000A041B
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#define DDR_DRAMTMG2 0x0607080F
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#define DDR_DRAMTMG3 0x0050400C
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#define DDR_DRAMTMG4 0x07040607
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#define DDR_DRAMTMG5 0x06060403
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#define DDR_DRAMTMG6 0x02020002
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#define DDR_DRAMTMG7 0x00000202
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#define DDR_DRAMTMG8 0x00001005
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#define DDR_DRAMTMG14 0x000000A0
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#define DDR_ZQCTL0 0xC2000040
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#define DDR_DFITMG0 0x02050105
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#define DDR_DFITMG1 0x00000202
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#define DDR_DFILPCFG0 0x07000000
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#define DDR_DFIUPD0 0xC0400003
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#define DDR_DFIUPD1 0x00000000
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#define DDR_DFIUPD2 0x00000000
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#define DDR_DFIPHYMSTR 0x00000000
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#define DDR_ADDRMAP1 0x00080808
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#define DDR_ADDRMAP2 0x00000000
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#define DDR_ADDRMAP3 0x00000000
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#define DDR_ADDRMAP4 0x00001F1F
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#define DDR_ADDRMAP5 0x07070707
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#define DDR_ADDRMAP6 0x0F070707
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#define DDR_ADDRMAP9 0x00000000
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#define DDR_ADDRMAP10 0x00000000
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#define DDR_ADDRMAP11 0x00000000
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#define DDR_ODTCFG 0x06000600
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#define DDR_ODTMAP 0x00000001
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#define DDR_SCHED 0x00000F01
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#define DDR_SCHED1 0x00000000
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#define DDR_PERFHPR1 0x00000001
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#define DDR_PERFLPR1 0x04000200
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#define DDR_PERFWR1 0x08000400
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#define DDR_DBG0 0x00000000
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#define DDR_DBG1 0x00000000
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#define DDR_DBGCMD 0x00000000
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#define DDR_POISONCFG 0x00000000
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#define DDR_PCCFG 0x00000010
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#define DDR_PCFGR_0 0x00000000
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#define DDR_PCFGW_0 0x00000000
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#define DDR_PCFGQOS0_0 0x00100009
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#define DDR_PCFGQOS1_0 0x00000020
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#define DDR_PCFGWQOS0_0 0x01100B03
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#define DDR_PCFGWQOS1_0 0x01000200
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#define DDR_PGCR 0x01442E02
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#define DDR_PTR0 0x0022AA5B
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#define DDR_PTR1 0x04841104
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#define DDR_PTR2 0x042DA068
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#define DDR_ACIOCR 0x10400812
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#define DDR_DXCCR 0x00000C40
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#define DDR_DSGCR 0xF200011F
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#define DDR_DCR 0x0000000B
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#define DDR_DTPR0 0x36D477D0
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#define DDR_DTPR1 0x098B00D8
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#define DDR_DTPR2 0x10023600
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#define DDR_MR0 0x00000830
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#define DDR_MR1 0x00000000
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#define DDR_MR2 0x00000208
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#define DDR_MR3 0x00000000
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#define DDR_ODTCR 0x00010000
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX1GCR 0x0000CE81
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#include "stm32mp13-ddr.dtsi"
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@ -403,6 +403,21 @@
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status = "disabled";
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};
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ddr: ddr@5a003000{
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compatible = "st,stm32mp13-ddr";
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reg = <0x5a003000 0x550>, <0x5a004000 0x234>;
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clocks = <&rcc AXIDCG>,
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<&rcc DDRC1>,
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<&rcc DDRPHYC>,
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<&rcc DDRCAPB>,
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<&rcc DDRPHYCAPB>;
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clock-names = "axidcg",
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"ddrc1",
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"ddrphyc",
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"ddrcapb",
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"ddrphycapb";
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};
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usbphyc: usbphyc@5a006000 {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -614,7 +614,12 @@ static inline uintptr_t tamp_bkpr(uint32_t idx)
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* Device Tree defines
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******************************************************************************/
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#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
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#if STM32MP13
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#define DT_DDR_COMPAT "st,stm32mp13-ddr"
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#endif
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#if STM32MP15
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#define DT_DDR_COMPAT "st,stm32mp1-ddr"
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#endif
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#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
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#define DT_NVMEM_LAYOUT_COMPAT "st,stm32-nvmem-layout"
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#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
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