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feat(stm32mp1-fdts): add DT files for STM32MP13
STM32MP13 is a single Cortex-A7 CPU, without co-processor. As for STM32MP15x SoC family, STM32MP15x SoCs come with different features, depending on SoC version. Each peripheral node is created. Some are left empty for the moment , and will be filled later on. Change-Id: I0166bb70dfa7f717e89e89883b059a5b873c4ef7 Signed-off-by: Yann Gautier <yann.gautier@st.com>
This commit is contained in:
Yann Gautier
parent
24d3da76d2
commit
3b99ab6e37
8 changed files with 817 additions and 0 deletions
97
fdts/stm32mp13-pinctrl.dtsi
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97
fdts/stm32mp13-pinctrl.dtsi
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@ -0,0 +1,97 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com>
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*/
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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&pinctrl {
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i2c4_pins_a: i2c4-0 {
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pins {
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pinmux = <STM32_PINMUX('E', 15, AF6)>, /* I2C4_SCL */
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<STM32_PINMUX('B', 9, AF6)>; /* I2C4_SDA */
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bias-disable;
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drive-open-drain;
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slew-rate = <0>;
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};
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};
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sdmmc1_b4_pins_a: sdmmc1-b4-0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
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<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
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slew-rate = <1>;
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drive-push-pull;
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bias-disable;
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};
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pins2 {
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pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
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slew-rate = <2>;
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drive-push-pull;
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bias-disable;
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};
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};
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sdmmc2_b4_pins_a: sdmmc2-b4-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
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<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
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<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
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<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
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slew-rate = <1>;
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drive-push-pull;
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bias-pull-up;
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};
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pins2 {
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pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
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slew-rate = <2>;
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drive-push-pull;
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bias-pull-up;
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};
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};
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uart4_pins_a: uart4-0 {
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pins1 {
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pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
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bias-disable;
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};
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};
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usart1_pins_a: usart1-0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
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<STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
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<STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
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bias-pull-up;
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};
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};
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uart8_pins_a: uart8-0 {
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pins1 {
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pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
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bias-pull-up;
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};
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};
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};
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606
fdts/stm32mp131.dtsi
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606
fdts/stm32mp131.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/clock/stm32mp13-clks.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/stm32mp13-resets.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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clocks = <&rcc CK_MPU>;
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clock-names = "cpu";
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nvmem-cells = <&part_number_otp>;
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nvmem-cell-names = "part_number";
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};
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};
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nvmem_layout: nvmem_layout@0 {
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compatible = "st,stm32-nvmem-layout";
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nvmem-cells = <&cfg0_otp>,
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<&part_number_otp>,
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<&monotonic_otp>,
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<&nand_otp>,
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<&nand2_otp>,
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<&uid_otp>,
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<&hw2_otp>;
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nvmem-cell-names = "cfg0_otp",
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"part_number_otp",
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"monotonic_otp",
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"nand_otp",
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"nand2_otp",
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"uid_otp",
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"hw2_otp";
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};
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clocks {
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clk_csi: clk-csi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <4000000>;
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};
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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};
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intc: interrupt-controller@a0021000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xa0021000 0x1000>,
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<0xa0022000 0x2000>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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usart3: serial@4000f000 {
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compatible = "st,stm32h7-uart";
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reg = <0x4000f000 0x400>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc USART3_K>;
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resets = <&rcc USART3_R>;
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status = "disabled";
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};
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uart4: serial@40010000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40010000 0x400>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc UART4_K>;
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resets = <&rcc UART4_R>;
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status = "disabled";
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};
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uart5: serial@40011000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40011000 0x400>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc UART5_K>;
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resets = <&rcc UART5_R>;
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status = "disabled";
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};
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uart7: serial@40018000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40018000 0x400>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc UART7_K>;
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resets = <&rcc UART7_R>;
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status = "disabled";
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};
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uart8: serial@40019000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40019000 0x400>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc UART8_K>;
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resets = <&rcc UART8_R>;
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status = "disabled";
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};
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usart6: serial@44003000 {
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compatible = "st,stm32h7-uart";
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reg = <0x44003000 0x400>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc USART6_K>;
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resets = <&rcc USART6_R>;
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status = "disabled";
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};
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usbotg_hs: usb-otg@49000000 {
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compatible = "st,stm32mp15-hsotg", "snps,dwc2";
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reg = <0x49000000 0x40000>;
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clocks = <&rcc USBO_K>;
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clock-names = "otg";
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resets = <&rcc USBO_R>;
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reset-names = "dwc2";
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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g-rx-fifo-size = <512>;
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g-np-tx-fifo-size = <32>;
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g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
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dr_mode = "otg";
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usb33d-supply = <&usb33>;
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status = "disabled";
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};
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usart1: serial@4c000000 {
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compatible = "st,stm32h7-uart";
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reg = <0x4c000000 0x400>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc USART1_K>;
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resets = <&rcc USART1_R>;
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status = "disabled";
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};
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usart2: serial@4c001000 {
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compatible = "st,stm32h7-uart";
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reg = <0x4c001000 0x400>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc USART2_K>;
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resets = <&rcc USART2_R>;
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status = "disabled";
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};
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i2c3: i2c@4c004000 {
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compatible = "st,stm32mp13-i2c";
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reg = <0x4c004000 0x400>;
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interrupt-names = "event", "error";
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interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>,
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<&intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc I2C3_K>;
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resets = <&rcc I2C3_R>;
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#address-cells = <1>;
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#size-cells = <0>;
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st,syscfg-fmp = <&syscfg 0x4 0x4>;
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i2c-analog-filter;
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status = "disabled";
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};
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i2c4: i2c@4c005000 {
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compatible = "st,stm32mp13-i2c";
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reg = <0x4c005000 0x400>;
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interrupt-names = "event", "error";
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interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
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<&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc I2C4_K>;
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resets = <&rcc I2C4_R>;
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#address-cells = <1>;
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#size-cells = <0>;
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st,syscfg-fmp = <&syscfg 0x4 0x8>;
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i2c-analog-filter;
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status = "disabled";
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};
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i2c5: i2c@4c006000 {
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compatible = "st,stm32mp13-i2c";
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reg = <0x4c006000 0x400>;
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interrupt-names = "event", "error";
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interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>,
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<&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc I2C5_K>;
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resets = <&rcc I2C5_R>;
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#address-cells = <1>;
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#size-cells = <0>;
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st,syscfg-fmp = <&syscfg 0x4 0x10>;
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i2c-analog-filter;
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status = "disabled";
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};
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rcc: rcc@50000000 {
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compatible = "st,stm32mp13-rcc", "syscon";
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reg = <0x50000000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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secure-interrupt-names = "wakeup";
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};
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pwr_regulators: pwr@50001000 {
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compatible = "st,stm32mp1,pwr-reg";
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reg = <0x50001000 0x10>;
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reg11: reg11 {
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regulator-name = "reg11";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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};
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reg18: reg18 {
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regulator-name = "reg18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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usb33: usb33 {
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regulator-name = "usb33";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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exti: interrupt-controller@5000d000 {
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compatible = "st,stm32mp13-exti", "syscon";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x5000d000 0x400>;
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};
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syscfg: syscon@50020000 {
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compatible = "st,stm32mp157-syscfg", "syscon";
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reg = <0x50020000 0x400>;
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clocks = <&rcc SYSCFG>;
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};
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vrefbuf: vrefbuf@50025000 {
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compatible = "st,stm32-vrefbuf";
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reg = <0x50025000 0x8>;
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <2500000>;
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clocks = <&rcc VREF>;
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status = "disabled";
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};
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hash: hash@54003000 {
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compatible = "st,stm32mp13-hash";
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reg = <0x54003000 0x400>;
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clocks = <&rcc HASH1>;
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resets = <&rcc HASH1_R>;
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status = "disabled";
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};
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rng: rng@54004000 {
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compatible = "st,stm32mp13-rng";
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reg = <0x54004000 0x400>;
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clocks = <&rcc RNG1_K>;
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resets = <&rcc RNG1_R>;
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status = "disabled";
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};
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fmc: memory-controller@58002000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "st,stm32mp1-fmc2-ebi";
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reg = <0x58002000 0x1000>;
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clocks = <&rcc FMC_K>;
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resets = <&rcc FMC_R>;
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status = "disabled";
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ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
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<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
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<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
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<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
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<4 0 0x80000000 0x10000000>; /* NAND */
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nand-controller@4,0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32mp1-fmc2-nfc";
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reg = <4 0x00000000 0x1000>,
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<4 0x08010000 0x1000>,
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<4 0x08020000 0x1000>,
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<4 0x01000000 0x1000>,
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<4 0x09010000 0x1000>,
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<4 0x09020000 0x1000>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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qspi: spi@58003000 {
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compatible = "st,stm32f469-qspi";
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||||
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
|
||||
reg-names = "qspi", "qspi_mm";
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc QSPI_K>;
|
||||
resets = <&rcc QSPI_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc1: mmc@58005000 {
|
||||
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x20253180>;
|
||||
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
|
||||
clocks = <&rcc SDMMC1_K>;
|
||||
clock-names = "apb_pclk";
|
||||
resets = <&rcc SDMMC1_R>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <120000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc2: mmc@58007000 {
|
||||
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x20253180>;
|
||||
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
|
||||
clocks = <&rcc SDMMC2_K>;
|
||||
clock-names = "apb_pclk";
|
||||
resets = <&rcc SDMMC2_R>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <120000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
crc1: crc@58009000 {
|
||||
compatible = "st,stm32f7-crc";
|
||||
reg = <0x58009000 0x400>;
|
||||
clocks = <&rcc CRC1>;
|
||||
};
|
||||
|
||||
usbh_ohci: usbh-ohci@5800c000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x5800c000 0x1000>;
|
||||
clocks = <&rcc USBH>;
|
||||
resets = <&rcc USBH_R>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh_ehci: usbh-ehci@5800d000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x5800d000 0x1000>;
|
||||
clocks = <&rcc USBH>;
|
||||
resets = <&rcc USBH_R>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
companion = <&usbh_ohci>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iwdg2: watchdog@5a002000 {
|
||||
compatible = "st,stm32mp1-iwdg";
|
||||
reg = <0x5a002000 0x400>;
|
||||
clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
|
||||
clock-names = "pclk", "lsi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphyc: usbphyc@5a006000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32mp1-usbphyc";
|
||||
reg = <0x5a006000 0x1000>;
|
||||
clocks = <&rcc USBPHY_K>;
|
||||
resets = <&rcc USBPHY_R>;
|
||||
vdda1v1-supply = <®11>;
|
||||
vdda1v8-supply = <®18>;
|
||||
status = "disabled";
|
||||
|
||||
usbphyc_port0: usb-phy@0 {
|
||||
#phy-cells = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
usbphyc_port1: usb-phy@1 {
|
||||
#phy-cells = <1>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
iwdg1: watchdog@5c003000 {
|
||||
compatible = "st,stm32mp1-iwdg";
|
||||
reg = <0x5c003000 0x400>;
|
||||
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
|
||||
clock-names = "pclk", "lsi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsec: efuse@5c005000 {
|
||||
compatible = "st,stm32mp15-bsec";
|
||||
reg = <0x5c005000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cfg0_otp: cfg0_otp@0 {
|
||||
reg = <0x0 0x2>;
|
||||
};
|
||||
part_number_otp: part_number_otp@4 {
|
||||
reg = <0x4 0x2>;
|
||||
};
|
||||
monotonic_otp: monotonic_otp@10 {
|
||||
reg = <0x10 0x4>;
|
||||
};
|
||||
nand_otp: cfg9_otp@24 {
|
||||
reg = <0x24 0x4>;
|
||||
};
|
||||
nand2_otp: cfg10_otp@28 {
|
||||
reg = <0x28 0x4>;
|
||||
};
|
||||
uid_otp: uid_otp@34 {
|
||||
reg = <0x34 0xc>;
|
||||
};
|
||||
hw2_otp: hw2_otp@48 {
|
||||
reg = <0x48 0x4>;
|
||||
};
|
||||
ts_cal1: calib@5c {
|
||||
reg = <0x5c 0x2>;
|
||||
};
|
||||
ts_cal2: calib@5e {
|
||||
reg = <0x5e 0x2>;
|
||||
};
|
||||
pkh_otp: pkh_otp@60 {
|
||||
reg = <0x60 0x20>;
|
||||
};
|
||||
mac_addr: mac_addr@e4 {
|
||||
reg = <0xe4 0xc>;
|
||||
st,non-secure-otp;
|
||||
};
|
||||
};
|
||||
|
||||
tamp: tamp@5c00a000 {
|
||||
reg = <0x5c00a000 0x400>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Break node order to solve dependency probe issue between
|
||||
* pinctrl and exti.
|
||||
*/
|
||||
pinctrl: pin-controller@50002000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32mp135-pinctrl";
|
||||
ranges = <0 0x50002000 0x8400>;
|
||||
interrupt-parent = <&exti>;
|
||||
st,syscfg = <&exti 0x60 0xff>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x0 0x400>;
|
||||
clocks = <&rcc GPIOA>;
|
||||
st,bank-name = "GPIOA";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1000 0x400>;
|
||||
clocks = <&rcc GPIOB>;
|
||||
st,bank-name = "GPIOB";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x400>;
|
||||
clocks = <&rcc GPIOC>;
|
||||
st,bank-name = "GPIOC";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x3000 0x400>;
|
||||
clocks = <&rcc GPIOD>;
|
||||
st,bank-name = "GPIOD";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x4000 0x400>;
|
||||
clocks = <&rcc GPIOE>;
|
||||
st,bank-name = "GPIOE";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x5000 0x400>;
|
||||
clocks = <&rcc GPIOF>;
|
||||
st,bank-name = "GPIOF";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x6000 0x400>;
|
||||
clocks = <&rcc GPIOG>;
|
||||
st,bank-name = "GPIOG";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x7000 0x400>;
|
||||
clocks = <&rcc GPIOH>;
|
||||
st,bank-name = "GPIOH";
|
||||
ngpios = <15>;
|
||||
gpio-ranges = <&pinctrl 0 112 15>;
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x8000 0x400>;
|
||||
clocks = <&rcc GPIOI>;
|
||||
st,bank-name = "GPIOI";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl 0 128 8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
21
fdts/stm32mp133.dtsi
Normal file
21
fdts/stm32mp133.dtsi
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32mp131.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
m_can1: can@4400e000 {
|
||||
reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
m_can2: can@4400f000 {
|
||||
reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
12
fdts/stm32mp135.dtsi
Normal file
12
fdts/stm32mp135.dtsi
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32mp133.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
};
|
||||
};
|
||||
5
fdts/stm32mp13xa.dtsi
Normal file
5
fdts/stm32mp13xa.dtsi
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
36
fdts/stm32mp13xc.dtsi
Normal file
36
fdts/stm32mp13xc.dtsi
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32mp13xa.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
cryp: crypto@54002000 {
|
||||
compatible = "st,stm32mp1-cryp";
|
||||
reg = <0x54002000 0x400>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc CRYP1>;
|
||||
resets = <&rcc CRYP1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
saes: saes@54005000 {
|
||||
compatible = "st,stm32-saes";
|
||||
reg = <0x54005000 0x400>;
|
||||
clocks = <&rcc SAES_K>;
|
||||
resets = <&rcc SAES_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pka: pka@54006000 {
|
||||
compatible = "st,stm32-pka64";
|
||||
reg = <0x54006000 0x2000>;
|
||||
clocks = <&rcc PKA>;
|
||||
resets = <&rcc PKA_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
5
fdts/stm32mp13xd.dtsi
Normal file
5
fdts/stm32mp13xd.dtsi
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
35
fdts/stm32mp13xf.dtsi
Normal file
35
fdts/stm32mp13xf.dtsi
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
#include "stm32mp13xd.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
cryp: crypto@54002000 {
|
||||
compatible = "st,stm32mp1-cryp";
|
||||
reg = <0x54002000 0x400>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc CRYP1>;
|
||||
resets = <&rcc CRYP1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
saes: saes@54005000 {
|
||||
compatible = "st,stm32-saes";
|
||||
reg = <0x54005000 0x400>;
|
||||
clocks = <&rcc SAES_K>;
|
||||
resets = <&rcc SAES_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pka: pka@54006000 {
|
||||
compatible = "st,stm32-pka64";
|
||||
reg = <0x54006000 0x2000>;
|
||||
clocks = <&rcc PKA>;
|
||||
resets = <&rcc PKA_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue