Moved common build options from Arm-specific file to common build
file.
Change-Id: If74b6223972ae3a6c11d9f9d2fbd8d2ee008b6e5
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
As the unit testing project uses the host machine GCC version to
compile, it is marking non-casted references as errors. This patch adds
the proper casting, so it compiles correctly for both Arm platforms and
host machines for unit testing.
Change-Id: Iee96e9117301ba28b6f164aac2cd36dc0f8b6be8
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
* changes:
feat(board/rdn2): enable base element RAM RAS support on RD-N2 platform
feat(plat/arm): add memory map entry for CPER memory region
feat(plat/arm): firmware first error handling support for base RAMs
feat(plat/arm): update common platform RAS implementation
feat(plat/sgi): remove RAS setup call from common code
refactor(plat/sgi): deprecate DMC-620 RAS support
fix(plat/common): register PLAT_SP_PRI only if not already registered
fix(plat/sgi): update PLAT_SP_PRI macro definition
fix(plat/arm): add RAS_FFH_SUPPORT check for RAS EHF priority
To enable firmware first support for base element RAMs on RD-N2 platform
this patch adds following support
- Includes SDEI header to enable SDEI feature on RD-N2 platform.
- Add TZC configuration for CPER memory region for RD-N2 platform
variants. This region is marked for non-secure access as OSPM and
firmware need to access this region.
- Defines all base element RAM errors for RD-N2 platform variants.
- Defines a platform RAS event map and respective RAS config data
structure.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ideaed598f4924f3b9836d4d7e9ef76b9b7580b48
In firmware-first error handling approach the firmware consumes the
hardware fault interrupt, processes the error and notifies the fault to
OSPM. Firmware also shares the error information with the OSPM using a
standard format called Common Platform Error Record (CPER). The CPER is
placed in reserved memory that is shared between OSPM and the firmware.
On RD-N2 platform variants carve out a reserved memory space for the
CPER buffer. This patch enables CPER memory map region on RD-N2 platform
variants.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ib2645c90d4dc975f57bb143795f61f74f4f81494
RD-N2 platform variants support base element RAM. The RAMs implement
ECC that detects ECC 1/2-bit errors and reports them via interrupts. The
error information is reported as part of error record frames defined for
base element RAMs.
This patch provides reference error handler implementation to handle
1/2-bit RAS errors that occur on base element RAM's. On error event the
error handler reads the error records information and forwards the event
to secure partition. Secure partition creates a CPER record from this
error information. Finally the handler notifies the OS about the RAS
error using the SDEI notification mechanism.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ic209c714de6cd2d4c845198b03724940a2e1c240
Refactor the RAS implementation to be used as common platform RAS
implementation for all the platforms. As part of refactoring this patch
extends support to configure interrupt as PPI interrupt type in addition
to currently supported SPI interrupts.
This patch defines a RAS config data structure to be defined by each
platform. The RAS config data structure carries the event map and size
information. Each platform code during initialization phase must define
this RAS config and register it with common platform RAS module.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I4019b31386a7e9c197bcc83bdca47876ee854d0f
In preparation of refactoring the support for platform error handling,
remove the call to RAS platform setup call from SGI specific common
code. This function will be called from platform code after the
refactoring.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: If4a87e0adf166b1c99bf5999f2f89efa6c7c6afc
Remove DMC-620 specific code from platform RAS implementation. DMC-620
RAS support is not supported on SGI and RD platforms. The rest of the
platform specific code maintained will be reused for supporting RAS
error handling on RD-N2 and later platforms.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ic03ae0e3298628330c5f7c25bafb0131f7b9d5b6
Build fails when RAS and SPM are enabled together and when PLAT_SP_PRI
EHF priority is equal to PLAT_RAS_PRI EHF priority.
So add checks to register SPM priority with the EHF framework only when
the priority is different from RAS priority or when RAS is not enabled
on the platform.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ie14f82d27c9835b24890cc4561a56821881cf0ec
PLAT_SP_PRI EHF priority is defined to be same as the PLAT_RAS_PRI EHF
priority. But PLAT_RAS_PRIORITY is defined only if RAS_FFH_SUPPORT is
enabled. This patch defines priority value for PLAT_SP_PRI if
RAS_FFH_SUPPORT is not enabled.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: Ib3747317d2ecc088fbbf1f5f283726a330454c93
For TF-A, there is no format specified for functional documentation.
For AMD-Xilinx platforms, following kernel-doc format for the functional
documentation to make sure AMD-xilinx documentation is align with
actual code.
For example use kernel-doc from linux to call:
<linux>/scripts/kernel-doc -man -v 1 >/dev/null file...
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Idcc9def408b6c8da35b36f67ef82fc00890e998c
Both march32-directive and march64-directive eventually generate the
same march option that will passed to compiler.
Merge this two separate directives to a common one as march-directive.
Change-Id: I220d2b782eb3b54e13ffd5b6a581d0e6da68756a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Previous implementation used common CSS interrupts, which do not match
the Morello platform interrupt map. Updated to configure Secure
interrupts according to the Morello TRM and InfraSYSDESIGN4.0
specification.
Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I783a472d92601d86f1844f0d035dd0d036b2bfca
* changes:
docs(msm8916): document new build options
feat(msm8916): allow selecting which UART to use
feat(msm8916): add SP_MIN port for AArch32
refactor(msm8916): detect cold boot in plat_get_my_entrypoint
feat(msm8916): add Test Secure Payload (TSP) port
build(msm8916): place bl32 directly after bl31
refactor(msm8916): separate common platform setup code
* changes:
fix(tsp): fix destination ID in direct request
fix(el3-spm): fix LSP direct message response
fix(el3-spm): improve direct messaging validation
Moved the Juno-specific build option from the common build option
file to the Arm build option file.
Change-Id: I0f53203f0cfca4a3baadab2cee4339c9694cfe8b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Ensure the TSP ID is set as the source ID in a direct request.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ia082fe5a1da6f2994072ec70c6ba818212a52f20
Ensure that the example LSP correctly sets the
sender/receiver field in a direct response.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I482c08d4657617adb00b0f3cf3c8ddc84f1bf7c8
Perform additional validation of the source and destination
IDs of direct messages.
Additionally track the sender of a direct request to allow
validating the target of the corresponding direct response.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I8d39d53a02b8333246f1500c79ba04f149459c16
In some build configurations TF-A can exceed the existing 256KB SRAM,
triggering a build failure. More recent versions of the base FVP allow
you to configure a larger Trusted SRAM of 512KB.
This change introduces the `FVP_TRUSTED_SRAM_SIZE` build option, which
allows you to explicitly specify how much of the Trusted SRAM to
utilise, e.g.:
FVP_TRUSTED_SRAM_SIZE=384
This allows previously-failing configurations to build successfully by
utilising more than the originally-allocated 256KB of the Trusted SRAM
while maintaining compatibility with older configurations/models that
only require/have 256KB.
Change-Id: I8344d3718564cd2bd53f1e6860e2fe341ae240b0
Signed-off-by: Chris Kay <chris.kay@arm.com>
Update the MSM8916 platform documentation with the new build options
introduced in the previous changes:
- AArch32 (BL32/SP_MIN)
- UART selection
While at it, also document the build options that allow changing the
memory addresses (PRELOADED_BL33_BASE, BL31_BASE, BL32_BASE).
Change-Id: I2370c8264982317693f69fda0b03a255f12bafe2
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
At the moment the msm8916 platform port always uses UART number 2 for
debug output. In some situations it is necessary to change this, either
because only the other UART is exposed on the board or for runtime
debugging, to avoid conflicting with the normal world.
Make the UART to use configurable using QTI_UART_NUM on the make
command line and also add QTI_RUNTIME_UART as an option to keep using
the UART after early boot. The latter is disabled by default since it
requires reserving the UART and related clocks inside the normal world.
Change-Id: I14725f954bbcecebcf317e8601922a3d00f2ec28
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Use the new shared msm8916 setup code to allow compiling the minimal
AArch32 Secure Payload (SP_MIN) as simple PSCI implementation.
AArch64 is preferred for the Cortex-A53 cores in MSM8916 but there are
some similar platforms with AArch32-only Cortex-A7 cores that can
benefit from this in future changes.
The AArch32 assembly implementation for msm8916_helpers.S and
uartdm_console.S is a direct port of the AArch64 implementation.
Only plat_get_my_entrypoint is slightly different because there is no
need to handle the "boot remapper" on cold boot for AArch32.
Change-Id: Idf160e86fb3e685fcedec3e051400e6273997b74
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
The msm8916 platform port needs to disable the TCM redirect to the L2
cache as early as possible during cold boot to avoid crashes. Right now
this is done in plat_reset_handler by checking if BL31 was started
through the "boot remapper", which redirects memory accesses around the
fixed CPU reset address (0x0) to the actual link address of BL31. On
AArch64 this is always the case during cold boot, since a CPU reset was
necessary to switch from AArch32 in the initial bootloader to AArch64.
On AArch32, SP_MIN starts running at the real link address immediately,
so the initial cold boot must be detected with a different approach.
To keep the AArch32 and AArch64 implementation of this functionality
consistent, move this functionality to plat_get_my_entrypoint, by
checking if the msm8916_entry_point is still zero or was already
updated for later warm boots by the PSCI code.
Also, avoid entering BL31 twice and instead add the BL31_BASE offset
to the return address in the link register. This allows preserving the
bootloader arguments in x0-x3 because they otherwise get lost.
Change-Id: I90286c6cacf23f44ed7930a3e7e33804ca63c391
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Use the new shared msm8916 setup code to easily allow compiling the
Test Secure Payload (TSP) for the msm8916 platform.
Unlike BL31, TSP only calls msm8916_platform_setup() but not
msm8916_configure() because this is already done in BL31.
Change-Id: I3225ef9e61387d49870e9759ffd5b899a8805961
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
At the moment there are two entirely separate memory regions for BL31
and BL32. However, since BL31 is very small (<= 128 KiB) there is
actually still plenty of space after BL31.
Drop the extra memory region for BL32 and place it directly after BL31
(i.e. BL31_LIMIT). If needed it is still possible to change it on the
make command line.
While at it, move the definitions to the bottom of the make file so
they come immediately before the related add_define calls.
Change-Id: I5184dcc2d89a92f1384508f973d56fd963e7befb
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
In preparation of adding BL32 support for the msm8916 platform
(AArch32/SP_MIN and TSP), separate the common platform setup code into
shared msm8916_setup.c and msm8916_config.c files which can be called
from both BL31 and BL32.
msm8916_setup.c contains the relevant shared code for BL31/SP_MIN/TSP,
while msm8916_config.c is cold boot configuration code that is only
relevant for BL31 and SP_MIN (but not TSP).
No functional change.
Change-Id: I055522d5ad8c03dfb8e09236dc47dd383a480e95
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Using one loop for the duplicate partition ID check is both simpler and
faster.
Change-Id: I0f6fa9ceb1aadf4383fa9be16605c39ad8643a43
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
This ensures that addresses shared using FF-A are 4K aligned, as
required by the specification.
Change-Id: I8f0a659a095fdb9391398757141d613ac9bf9b42
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>
Type cast the build time base and size argument to unsigned integer
and the limit derived from these two as unsigned long to avoid
size overflow issue during build.
For zynqmp platform, calculating the limit without typecasting results
in build error as follows
make -j DEBUG=0 RESET_TO_BL31=1 PLAT=zynqmp \
ZYNQMP_ATF_MEM_BASE=0x70000000 ZYNQMP_ATF_MEM_SIZE=0x10000000 \
XILINX_OF_BOARD_DTB_ADDR=0x100000 bl31
plat/xilinx/zynqmp/include/platform_def.h:51:62:
error: integer overflow in expression of type 'int' results
in '-2147483648' [-Werror=overflow]
51 | # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE)
Change-Id: Id093a50e748884d4fba65626e94f361f6c23cecc
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
The current implementation of macro L/LL/UL/ULL concatenates the input
with "L"/"LL"/"UL"/"ULL" respectively.
In the case where a macro is passed to L/LL/UL/ULL as input,
the input macro name is concatenated with, rather than expanding
the input macro and then concatenating it.
The implementation of L/LL/UL/ULL is modified to two level macro,
so as to concatenate to the expansion of a macro argument.
Change 5b33ad174a "Unify type of "cpu_idx" across PSCI module."
has modified the implementation of U() to two level macros without
changing the implementation of other macros.
Change-Id: Ie93d67dff5ce96223a3faf6c98b98fcda530fc34
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
