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fix(morello): configure platform specific secure SPIs

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Previous implementation used common CSS interrupts, which do not match
the Morello platform interrupt map. Updated to configure Secure
interrupts according to the Morello TRM and InfraSYSDESIGN4.0
specification.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I783a472d92601d86f1844f0d035dd0d036b2bfca
This commit is contained in:
Werner Lewis 2023-05-25 15:24:46 +01:00 • committed by Manish V Badarkhe
parent c4c7efe79e
commit 80f8769b26
1 changed files with 53 additions and 1 deletions
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54
plat/arm/board/morello/include/platform_def.h
View file

@ -163,7 +163,59 @@
#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
#define PLAT_MAX_PWR_LVL U(2)
#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
/* Interrupt handling constants */
#define MORELLO_IRQ_SEC_UART U(87)
#define MORELLO_IRQ_DISPLAY_TCU_EVENT_Q U(107)
#define MORELLO_IRQ_DISPLAY_TCU_CMD_SYNC U(111)
#define MORELLO_IRQ_DISPLAY_TCU_GLOBAL U(113)
#define MORELLO_IRQ_MMU_TCU1_EVENT_Q U(257)
#define MORELLO_IRQ_MMU_TCU1_CMD_SYNC U(258)
#define MORELLO_IRQ_MMU_TCU1_GLOBAL U(259)
#define MORELLO_IRQ_MMU_TCU2_EVENT_Q U(264)
#define MORELLO_IRQ_MMU_TCU2_CMD_SYNC U(265)
#define MORELLO_IRQ_MMU_TCU2_GLOBAL U(266)
#define MORELLO_IRQ_CLUSTER0_MHU U(349)
#define MORELLO_IRQ_CLUSTER1_MHU U(351)
#define MORELLO_IRQ_P0_REFCLK U(412)
#define MORELLO_IRQ_P1_REFCLK U(413)
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
ARM_G1S_IRQ_PROPS(grp), \
INTR_PROP_DESC(CSS_IRQ_MHU, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(MORELLO_IRQ_SEC_UART, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(MORELLO_IRQ_DISPLAY_TCU_EVENT_Q, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(MORELLO_IRQ_DISPLAY_TCU_CMD_SYNC, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(MORELLO_IRQ_DISPLAY_TCU_GLOBAL, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU1_EVENT_Q, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU1_CMD_SYNC, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU1_GLOBAL, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU2_EVENT_Q, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU2_CMD_SYNC, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(MORELLO_IRQ_MMU_TCU2_GLOBAL, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(MORELLO_IRQ_CLUSTER0_MHU, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(MORELLO_IRQ_CLUSTER1_MHU, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(MORELLO_IRQ_P0_REFCLK, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(MORELLO_IRQ_P1_REFCLK, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL)
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
#define MORELLO_DEVICE_BASE ULL(0x08000000)