Commit graph

7116 commits

Author SHA1 Message Date
Manish Pandey
a97e1f9747 Merge changes from topic "early_console" into integration
* changes:
  feat(stm32mp2): use early traces
  feat(st-bsec): use early traces
  refactor(st): replace STM32MP_EARLY_CONSOLE with EARLY_CONSOLE
  feat(console): introduce EARLY_CONSOLE
  feat(bl32): create an sp_min_setup function
2024-05-08 23:12:11 +02:00
Manish Pandey
10327628ca Merge "feat(stm32mp2): add ddr-fw parameter for fiptool" into integration 2024-05-08 23:08:44 +02:00
Manish Pandey
72ac981044 Merge changes from topic "css_refactor_arm" into integration
* changes:
  refactor(console): consolidate console runtime switch
  refactor(synquacer): console runtime switch on bl31 exit
  refactor(nxp): console runtime switch on bl31 exit
  refactor(nvidia): console runtime switch on bl31 exit
  refactor(hisilicon): console runtime switch on bl31 exit
  refactor(xilinx): console runtime switch on bl31 exit
  refactor(mediatek): console runtime switch on bl31 exit
  refactor(armada): console runtime switch on bl31 exit
  refactor(imx): console runtime switch on bl31 exit
  refactor(brcm): console runtime switch on bl31 exit
2024-05-08 22:25:08 +02:00
Manish V Badarkhe
69c4bf9ae3 Merge changes from topic "tc_refactor_dt_binding" into integration
* changes:
  refactor(tc): move SCMI nodes into the 'firmware' node
  refactor(tc): move MHUv2 property to tc2.dts
  refactor(tc): drop the 'mhu-protocol' property in DT binding
  refactor(tc): append properties in DT bindings
  refactor(tc): move SCMI clock DT binding into tc-base.dtsi
  refactor(tc): introduce a new file tc-fpga.dtsi
  refactor(tc): move out platform specific DT binding from tc-base.dtsi
  refactor(tc): move out platform specific code from tc_vers.dtsi
  refactor(tc): add platform specific DT files
  refactor(tc): rename 'tc_fvp.dtsi' to 'tc-fvp.dtsi'
  refactor(tc): introduce a new macro ADDRESSIFY()
2024-05-08 20:19:36 +02:00
Manish Pandey
4bd1e7bdc6 Merge changes from topic "add_s32g274ardb2_support" into integration
* changes:
  feat(s32g274a): enable BL31 stage
  feat(s32g274a): add S32G274ARDB2 board support
  feat(nxp-drivers): add Linflex driver
2024-05-08 17:16:50 +02:00
Salman Nabi
af3e8e63b4 refactor(console): consolidate console runtime switch
Refactor console_flush() and console_switch_state(CONSOLE_FLAG_RUNTIME)
to bl31_main(). This has been done per the recommendation in TF-A
mailing list. These calls need to be the last calls, after any runtime
initialization has been done, before BL31 exits.

All platforms that override the generic implementation of
bl31_plat_runtime_setup() have been refactored. The console_flush()
and console_switch_state() calls have been removed as they become
part of bl31_main() function.

Any platform that don't need to make any change to the generic (weak)
implementation of bl31_plat_runtime_setup() don't need to override it
in their platforms.

Change-Id: I6d04d6daa9353daeaa7e3df9e9adf6f322a917b8
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
2024-05-08 15:50:58 +02:00
Salman Nabi
92752355f5 refactor(synquacer): console runtime switch on bl31 exit
TF-A plans to move the console_flush() and
console_switch_state(CONOSLE_FLAG_RUNTIME) calls to bl31_main() just
before BL31 exits.

For now we are mimicking the generic implementation by calling flush
and changing the console state to runtime at the end of
bl31_plat_runtime_setup() for each platform. This is so that each
platform can test it prior to moving flush and switch to bl31_main().

This patch affects the synquacer SoC of the socionext platform.

Change-Id: I85a251e3d9732c5fb5010c3c8bb7323c4f57fa96
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
2024-05-08 15:50:58 +02:00
Salman Nabi
3e6fb87225 refactor(nxp): console runtime switch on bl31 exit
TF-A plans to move the console_flush() and
console_switch_state(CONOSLE_FLAG_RUNTIME) calls to bl31_main() just
before BL31 exits.

For now we are mimicking the generic implementation by calling flush
and changing the console state to runtime at the end of
bl31_plat_runtime_setup() for each platform. This is so that each
platform can test it prior to moving flush and switch to bl31_main().

This patch affects the nxp platform only.

Change-Id: Ic55334a4a69b57f3c18799da12f4f521ce9de423
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
2024-05-08 15:50:58 +02:00
Salman Nabi
c1fd8f9d7b refactor(nvidia): console runtime switch on bl31 exit
TF-A plans to move the console_flush() and
console_switch_state(CONOSLE_FLAG_RUNTIME) calls to bl31_main() just
before BL31 exits.

For now we are mimicking the generic implementation by calling flush
and changing the console state to runtime at the end of
bl31_plat_runtime_setup() for each platform. This is so that each
platform can test it prior to moving flush and switch to bl31_main().

This patch affects Nvidia platform only.

Change-Id: I78c148f50e8ee881e1816cab6eeea3765dc469e5
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
2024-05-08 15:50:58 +02:00
Salman Nabi
d51a63260f refactor(hisilicon): console runtime switch on bl31 exit
TF-A plans to move the console_flush() and
console_switch_state(CONOSLE_FLAG_RUNTIME) calls to bl31_main() just
before BL31 exits.

For now we are mimicking the generic implementation by calling flush
and changing the console state to runtime at the end of
bl31_plat_runtime_setup() for each platform. This is so that each
platform can test it prior to moving flush and switch to bl31_main().

This patch affects the Hisilicon SoCs (poplar, hikey, hikey960).

Change-Id: I0cbb0644377f663e880310362abb4308e24f0cef
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
2024-05-08 15:50:58 +02:00
Salman Nabi
48932c3c27 refactor(xilinx): console runtime switch on bl31 exit
Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch affects Xilinx SoCs only.

Change-Id: Iea4cf920934bbde4312f40c8c7b3e0f56a316e86
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
2024-05-08 15:50:58 +02:00
Salman Nabi
9edf08b177 refactor(mediatek): console runtime switch on bl31 exit
Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch affects the Mediatek platform only.

Change-Id: I83beee28ed856bc9b2f3131aa577be9bfa529028
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
2024-05-08 15:50:58 +02:00
Salman Nabi
88ab2261b3 refactor(armada): console runtime switch on bl31 exit
Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch only affects the Armada SoC of Marvell's platform.

Change-Id: I7082fdb8c5507cd1ce5915d67e61e638605982e0
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
2024-05-08 15:50:58 +02:00
Salman Nabi
d3c643c2dc refactor(imx): console runtime switch on bl31 exit
Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch affects the Freescale/NXP SoCs imx93, imx8qm and imx8qx.

Change-Id: Iece74579e1d15eeeb8279db0c53d74bce45545bd
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
2024-05-08 15:50:58 +02:00
Salman Nabi
46163ddddb refactor(brcm): console runtime switch on bl31 exit
Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch affects the Broadcom platform only.

Change-Id: I693f749bbf56911638b03e069659e86b95b1050e
Signed-off-by: Salman Nabi <salman.nabi@arm.com>
2024-05-08 15:50:58 +02:00
Manish Pandey
dd03806122 Merge changes from topic "fix_psci_osi" into integration
* changes:
  fix(psci): fix parent_idx in psci_validate_state_coordination
  fix(psci): mask the Last in Level nibble in StateId
2024-05-08 15:45:12 +02:00
Manish Pandey
2b67ee6d7c Merge "chore: rename hermes to neoverse-n3" into integration 2024-05-08 13:51:47 +02:00
Jayanth Dodderi Chidanand
0a9c244b05 fix(psci): mask the Last in Level nibble in StateId
In the ARM recommended StateID Encoding, the index for the power
level where the calling core is last to go idle use the last niblle
of the StateId.

Even if this nibble is necessary for OS-initiated mode, it can be
used by caller even when this OSI mode is not used.

In arm_validate_power_state() function, the StateId is compared with
content of arm_pm_idle_states[] build with the arm_make_pwrstate_lvl2
macro, without Last in Level information. So it is safe to mask this
nibble for ARM platform in all the cases, and that avoids issues with
caller with use the same StateId encoding with OSI mode activated or
not (in tftf tests for example, the input(power state) parameter =
(0x40001022) and the associated power state is 0x40000022).

Change-Id: I45e8e2b8f526fb61b94cf134d7d4aa3bac4c215d
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2024-05-08 10:09:07 +01:00
Manish V Badarkhe
ee9cfaccab Merge changes from topic "makefile-cleanup" into integration
* changes:
  build: improve diagnostics for unrecognized toolchain tools
  build(rzg): separate BL2 and BL31 SREC generation
  build(rcar): separate BL2 and BL31 SREC generation
  build: separate preprocessing from DTB compilation
  build: remove `MAKE_BUILD_STRINGS` function
2024-05-07 18:39:53 +02:00
Govindraj Raja
ba6b69494b chore: rename hermes to neoverse-n3
Rename hermes cpu to Neoverse-N3

Change-Id: I912d4c824c5004a8c1909c68fef77f1f5e202b8a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2024-05-07 08:51:27 -05:00
Manish V Badarkhe
531d923bac Merge "fix(tc): enable FEAT_MTE2" into integration 2024-05-07 14:58:18 +02:00
Manish Pandey
2a0ca84f47 Merge changes from topic "sm/feat_detect" into integration
* changes:
  refactor(cpufeat): restore functions in detect_arch_features
  refactor(cpufeat): add macro to simplify is_feat_xx_present
  chore: simplify the macro names in ENABLE_FEAT mechanism
2024-05-07 11:17:02 +02:00
Govindraj Raja
f7679d437d refactor(smccc): move pmf to vendor el3 calls
Move pmf support to vendor-specific EL3 Monitor Service Calls. Remove
pmf call count as it's not supported in vendor-specific el3 as per
SMCCC Documentation 1.5:
https://developer.arm.com/documentation/den0028/latest

Add a deprecation notice to inform PMF is moved from arm-sip range to
vendor-specific EL3 range. PMF support from arm-sip range will be
removed and will not available after TF-A 2.12 release.

Change-Id: Ie1e14aa601d4fc3db352cd5621d842017a18e9ec
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2024-05-06 09:42:11 -05:00
Govindraj Raja
273b898388 refactor(smccc): move debugfs to vendor el3 calls
Move debugfs to Vendor-Specific EL3 Monitor Service Calls.
Function Identifier for Vendor-Specific EL3 Monitor Service is '7' and
allocated subranges of Function identifiers to different services are:

0x87000000-0x8700FFFF-SMC32: Vendor-Specific EL3 Monitor Service Calls
0xC7000000-0xC700FFFF-SMC64: Vendor-Specific EL3 Monitor Service Calls

Amend Debugfs FID's to use this range and id.

Add a deprecation notice to inform debugfs moved from arm-sip range to
Vendor-Specific EL3 range. Debugfs support from arm-sip range will be
removed and will not be available after TF-A 2.12 release.

Reference to debugfs component level documentation:
https://trustedfirmware-a.readthedocs.io/en/latest/components/debugfs-design.html#overview

Change-Id: I97a50170178f361f70c95ed0049bc4e278de59d7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2024-05-06 09:42:11 -05:00
Govindraj Raja
5af143f293 refactor(fvp): move cpus with nomodel
Move CPUs which are not tested in CI under a new build option.
We have added some CPUs for which there is no FVP models available
yet to test. Move those CPUs under a new FVP build option.

Change-Id: I3da12d2f8d9c246b435b31adfac61c79dc1ab0cb
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2024-05-03 08:08:00 -05:00
Olivier Deprez
af58f6d4a5 Merge "build(fvp): make all builds unconditional" into integration 2024-05-03 13:11:33 +02:00
Sona Mathew
aaaf2cc313 refactor(cpufeat): add macro to simplify is_feat_xx_present
In this patch, we are trying to introduce the wrapper macro
CREATE_FEATURE_PRESENT to get the following capability and
align it for all the features:

-> is_feat_xx_present(): Does Hardware implement the feature.
-> uniformity in naming the function across multiple features.
-> improved readability

The is_feat_xx_present() is implemented to check if the hardware
implements the feature and does not take into account the
ENABLE_FEAT_XXX flag enabled/disabled in software.

- CREATE_FEATURE_PRESENT(name, idreg, shift, mask, idval)
The wrapper macro reduces the function to a single line and
creates the is_feat_xx_present function that checks the
id register based on the shift and mask values and compares
this against a determined idvalue.

Change-Id: I7b91d2c9c6fbe55f94c693aa1b2c50be54fb9ecc
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
2024-05-02 12:16:16 -05:00
Joanna Farley
48f1bc9f52 Merge "feat(zynqmp): remove unused pm_get_proc_by_node()" into integration 2024-05-02 10:13:54 +02:00
Joanna Farley
b109b00669 Merge "fix(xilinx): check proc variable before use" into integration 2024-05-02 09:28:03 +02:00
Ronak Jain
b03ba4801d feat(zynqmp): remove unused pm_get_proc_by_node()
The pm_get_proc_by_node() is not used anywhere. Hence remove the
same.

Change-Id: Ifd68dd524cae0a9f1684d943019563027859ccea
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
2024-05-02 09:21:45 +02:00
Manish Pandey
753c49d512 Merge "feat(mt8188): remove apusys kernel handler usage constraints" into integration 2024-05-01 22:08:11 +02:00
Govindraj Raja
0bd2075efc build(fvp): make all builds unconditional
commit@138221c2457b9d04101b84084c07d576b0eb5a51 reduced items that
should be build due to SRAM size limitations.

But newer models from 11.19 onwards support to set SRAM size greater
than 256KB. So remove all dependency and conditional builds for FVP.

Change-Id: I38684e100450b74fdda0d685775e2cbce92170b6
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2024-04-30 18:57:08 +02:00
Leo Yan
b3a9737ce0 refactor(tc): add platform specific DT files
Currently, the DT binding uses the file 'tc.dts' as a central place for
all TC platforms. And the variables (for different platforms, or FVP vs
FPGA, etc.) are maintained in 'tc_vers.dtsi'.

This patch renames 'tc.dts' to 'tc-base.dtsi' and creates an individual
.dts file for every platform. The purpose is to use 'tc-base.dtsi' for
maintaining common DT binding and every platform's specific definitions
will be moved into its own .dts file. This is a preparation for
sequential refactoring.

It changes to include the header files in platform DTS files but not in
the 'tc-base.dtsi'. This can allow 'tc-base.dtsi' is general enough and
platform DTS files covers platform specific defintions.

Change-Id: I034fb3f8836bcea36e8ad8ae01de41127693b0c6
Signed-off-by: Leo Yan <leo.yan@arm.com>
2024-04-30 14:20:18 +01:00
Leo Yan
154eb0a22f fix(tc): enable FEAT_MTE2
Commit c282384db ("refactor(mte): remove mte, mte_perm") removes the
option FEAT_MTE and introduces FEAT_MTE2 option. Afterwards, the
FEAT_MTE2 option is missed on the TC platform and the feature is
disabled. As a result, it causes the panic in secure world.

This patch enables the FEAT_MTE2 option for TC platform to allow the
secure world can access the MTE registers properly.

Change-Id: If697236aa59bf4fb374e0ff43b53455ac2154e9c
Fixes: c282384db ("refactor(mte): remove mte, mte_perm")
Signed-off-by: Leo Yan <leo.yan@arm.com>
2024-04-30 10:54:18 +01:00
Chris Kay
784092ee16 build(rzg): separate BL2 and BL31 SREC generation
This small change creates individual Make non-phony targets for the Bl2
and BL31 SREC binaries to avoid rebuilding them unnecessarily.

Change-Id: Ia8e5db0e4a968d4b379fdb66123b6a8f20933bf5
Signed-off-by: Chris Kay <chris.kay@arm.com>
2024-04-29 12:47:01 +00:00
Chris Kay
4d1289bd31 build(rcar): separate BL2 and BL31 SREC generation
This small change creates individual Make non-phony targets for the Bl2
and BL31 SREC binaries to avoid rebuilding them unnecessarily.

Change-Id: Ibb8880bb5c00a0956fc78d252fcc56391fbfe439
Signed-off-by: Chris Kay <chris.kay@arm.com>
2024-04-29 12:47:01 +00:00
Chris Kay
758ccb802d build: remove MAKE_BUILD_STRINGS function
This function causes the build message to be generated and compiled in
two different ways, with one way done inside `build_macros.mk` and the
other done inside `windows.mk`, mostly because it's done by generating
the C file on the command line.

We can instead replace this whole build message generation sequence with
a simple standard C compilation command and a normal C file.

Change-Id: I8bc136380c9585ddeec9a11154ee39ef70526f81
Signed-off-by: Chris Kay <chris.kay@arm.com>
2024-04-29 12:47:01 +00:00
Karl Li
0c77651fb4 feat(mt8188): remove apusys kernel handler usage constraints
It is expected that kernel can control the flow of the TF-A operations.
This patch remove the apusys kernel handler usage constraints, making
the operations all controlled on kernel side.

Signed-off-by: Karl Li <karl.li@mediatek.com>
Change-Id: Idc205a2cf23e1ff5f1920658a3b089c823f0288a
2024-04-29 16:56:32 +08:00
Alex Dobrescu
44ddee6f0a fix(tc): increase stack size when TRUSTED_BOARD_BOOT=0
The stack is too small for VERBOSE logging when secure world is disabled
as there is a recursive call when printing the translation table state
which causes a crash.

Changing the stack to the same value regardless of trusted boot.

Change-Id: I12298b33e47ae5206f74370262edce06b8a75d99
Signed-off-by: Alex Dobrescu <alex.dobrescu@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
2024-04-26 16:32:36 +01:00
Manish V Badarkhe
a1901c7d0d Merge changes from topic "rss_rse_rename" into integration
* changes:
  refactor(changelog): change all occurrences of RSS to RSE
  refactor(qemu): change all occurrences of RSS to RSE
  refactor(fvp): change all occurrences of RSS to RSE
  refactor(fiptool): change all occurrences of RSS to RSE
  refactor(psa): change all occurrences of RSS to RSE
  refactor(fvp): remove leftovers from rss measured boot support
  refactor(tc): change all occurrences of RSS to RSE
  docs: change all occurrences of RSS to RSE
  refactor(measured-boot): change all occurrences of RSS to RSE
  refactor(rse): change all occurrences of RSS to RSE
  refactor(psa): rename all 'rss' files to 'rse'
  refactor(tc): rename all 'rss' files to 'rse'
  docs: rename all 'rss' files to 'rse'
  refactor(measured-boot): rename all 'rss' files to 'rse'
  refactor(rss): rename all 'rss' files to 'rse'
2024-04-26 16:55:04 +02:00
Manish Pandey
f9d40b5c4b Merge changes from topic "hm/handoff" into integration
* changes:
  feat(handoff): add support for RESET_TO_BL2
  feat(arm): support FW handoff b/w BL1 & BL2
  feat(handoff): add TL source files to BL1
  feat(handoff): add TE's for BL1 handoff interface
  refactor(bl1): clean up bl2 layout calculation
  feat(arm): support FW handoff b/w BL2 & BL31
2024-04-26 16:22:38 +02:00
Harrison Mutai
f019c8013e feat(handoff): add support for RESET_TO_BL2
When BL2 is enabled as the entrypoint in the reset vector, none of the
TL initialisation ordinarily performed in BL1 will have been done. This
change ensures that BL2 has a secure TL to pass information onto BL31
through.

Change-Id: I553b0b7aac9390cd6a2d63471b81ddc72cc40a60
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2024-04-26 09:00:13 +00:00
Harrison Mutai
9c11ed7e3e feat(arm): support FW handoff b/w BL1 & BL2
Leverage the framework between BL1 and BL2. Migrate all handoff
structures to the TL.

Change-Id: I79ff3a319596b5656184cde10b5204b10a4d03bb
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2024-04-26 09:00:12 +00:00
Harrison Mutai
6a4da29058 refactor(bl1): clean up bl2 layout calculation
Layout calculation is spread out between core BL1 logic and common
platform code. Relocate these into common platform code so they are
organised logically.

Change-Id: I8b05403e41b800957a0367316cecd373d10bb1a4
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2024-04-26 09:00:12 +00:00
Harrison Mutai
a5566f65fd feat(arm): support FW handoff b/w BL2 & BL31
Add support for the firmware handoff framework between BL2 and BL31.
Create a transfer list in trusted SRAM, leveraging the larger SRAM sizes
in recent models. Load the HW_CONFIG as a TE along with entry point
parameters for BL31 execution.

Change-Id: I7c4c6e8353ca978a13520fb3e15fb2803f0f1d0e
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2024-04-26 09:00:12 +00:00
Manish Pandey
9a31b68bc8 Merge "fix(tc): missing device regions in spmc manifest" into integration 2024-04-26 10:25:00 +02:00
J-Alves
5e4711208d fix(tc): missing device regions in spmc manifest
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I847c9ec13c3d40dd9de8cf374a81fc6d23a8864c
2024-04-25 17:25:36 +01:00
Ghennadi Procopciuc
e73c3c3a6c feat(s32g274a): enable BL31 stage
Add BL31 prerequisites for the S32G274ARDB2 board to allow single-core
cold boot without MMU and PSCI services.

Change-Id: I8a10fd62f3cc9430083758043ea82e3803f61060
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
2024-04-25 11:22:53 +03:00
Ghennadi Procopciuc
8b81a39e28 feat(s32g274a): add S32G274ARDB2 board support
S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, accelerators for automotive networking and many other
peripherals.

The added support is minimal and only includes the BL2 stage, with no
MMU enabled. The FIP is preloaded by the BootROM in SRAM, and BL2 copies
BL31 and BL33 from FIP to their designated addresses.

Change-Id: Iedda23302768ab70d63787117c5f6f3c21eb9842
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
2024-04-25 11:22:53 +03:00
Rohit Mathew
8d6fb77a96 refactor(neoverse-rd): remove soc_css.mk from common makefile
The soc_css.mk file within the plat/arm/soc module currently implements
initialization functions for the PCIe controller and NIC400 within the
SOC specification. However, as none of the Neoverse reference design
platforms necessitate the initialization of PCIe or NIC400, remove the
soc_css.mk from the common makefile.

Additionally, empty initialization functions for PCIe and NIC400 are
added to satisfy the requirements of the plat/arm common code, which
expects these functions to be present.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ia431af62f48fc224962d64902dd3acfbf0b93935
2024-04-25 09:11:23 +01:00