* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fvp): change all occurrences of RSS to RSE
refactor(fiptool): change all occurrences of RSS to RSE
refactor(psa): change all occurrences of RSS to RSE
refactor(fvp): remove leftovers from rss measured boot support
refactor(tc): change all occurrences of RSS to RSE
docs: change all occurrences of RSS to RSE
refactor(measured-boot): change all occurrences of RSS to RSE
refactor(rse): change all occurrences of RSS to RSE
refactor(psa): rename all 'rss' files to 'rse'
refactor(tc): rename all 'rss' files to 'rse'
docs: rename all 'rss' files to 'rse'
refactor(measured-boot): rename all 'rss' files to 'rse'
refactor(rss): rename all 'rss' files to 'rse'
The title for RD-N1-Edge was written as "RD-N1 Edge" in the changelog
file. This has been corrected to "RD-N1-Edge" to pedantically reflect
the proper name for the platform.
Change-Id: I17a0f8745117674482e7c668109d821c81e35d1d
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
As RD-V1-MC would need a dedicated scope for use, define the scope
'rdv1mc' under the subsection within Neoverse-RD platforms.
Change-Id: I5fd53ce89815e355b595fe7ff066386842b7af03
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
As RD-V1 would need a dedicated scope for use, define the scope
'rdv1' under the subsection within Neoverse-RD platforms.
Change-Id: I035499e1ce85d6efd54ac4fe74ff6185367a07aa
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
As SGI-575 would need a dedicated scope for use, define the scope
'sgi575' under the subsection within Neoverse-RD platforms.
Change-Id: I872dc3bceace5c3358cde24fff1c4c17207ec962
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
As sgi has migrated to neoverse_rd, the scope variables would need
update. Therefore, remove the deprecated 'sgi' scope variable and
introduce the new scope variable 'neoverse-rd' to be used for any common
platform changes associated with Neoverse Reference Design platforms.
Change-Id: I5052e4573bdc7df3e6f4257146d716edd2585452
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I66a6c87c158b14e18cba25ea6c6e0809e30008ca
* changes:
feat(rpi): add Raspberry Pi 5 support
fix(rpi): consider MT when calculating core index from MPIDR
refactor(rpi): move register definitions out of rpi_hw.h
refactor(rpi): add platform macro for the crash UART base address
refactor(rpi): split out console registration logic
refactor(rpi): move more platform-specific code into common
The Raspberry Pi 5 is a single-board computer based on BCM2712 that
contains four Arm Cortex-A76 cores.
This change introduces minimal BL31 support with PSCI that has been
validated to boot Linux and a private EDK2 build.
It's a drop-in replacement for the custom TF-A armstub now included in
the EEPROM images.
Change-Id: Id72a0370f54e71ac97c3daa1bacedacb7dec148f
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
To cover the DICE related works such as
DICE Protection Environment (DPE) integration
with the measurd boot framework.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I9769b7bddbd1d269705ebff1d15870ab928fd8ef
* changes:
build: remove the `NM` variable
build: prefer `gcc-ar` over `ar`
build: add `--no-warn-rwx-segments` when linking with GCC
build: always use the C compiler to assemble
build: always use the C compiler to preprocess
fix(rcar): fix implicit rule invocations in tools
The ROM library is the only component in the repository that compiles
assembly files using the assembler directly. This change migrates it to
the C compiler instead, like the rest of the project.
Change-Id: I6c50660eeb9be2ca8dcb0e626c37c197466b0fa1
Signed-off-by: Chris Kay <chris.kay@arm.com>
mbedtls/version.h needs to be included before the use of any
mbedtls config variables.
Fixes a build failure regression from commit a8eadc51a.
Change-Id: Idd955d7955b0a55ffd127f31053335542cb15e22
Signed-off-by: Henrik Nordstrom <henrik.nordstrom@addiva.se>
Added changelog for v2.10 release.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Id06263047fcc1ec60e82f85cd09e2e4bc95830f5
This reverts commit 0abbfab320.
Reason for revert: Changelog was based on rc0 tag but we got few more patches after that which were not captured.
Change-Id: I9829f2b6dc09f0bd5c538845cbae051f6e4c8a75
Added scope for MbedTLS PSA Crypto API implementation.
Change-Id: I0a7c6242841dfb94f6ca5e9174ffd520c5fe00fa
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Add new scope for the JTAG DCC (Debug Communication Channel).
Driver is available for quite some time at
drivers/arm/dcc/dcc_console.c.
Change-Id: I8be71dadb56bed2b64a26c8a009bda6bbc96240d
Signed-off-by: Michal Simek <michal.simek@amd.com>
The generic interrupt controller identifies an interrupt based on its
type whereas the GIC uses the notion of groups to identify an
interrupt.
This patch changes the name of the helper functions to use group
rather than type for handling interrupts. No functional change in this
patch.
Change-Id: If13ec65cc6c87c2da73a3d54b033f02635ff924a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Add transfer list APIs and firmware handoff build option.
Change-Id: I68a0ace22c7e50fcdacd101eb76b271d7b76d8ff
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Update the revision and variant information in the
errata ABI file for Cortex-A710, erratum ID - 2058056
to match the revision and variant in the cortex_a710.S
file.
Change-Id: I4b974ac1f94d770f3ae7c15c88f42380c944eb43
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
Aspeed AST2700 is a quad-core SoC with ARM Cortex-A35 integrated.
This patch adds the initial platform support for AST2700 and also
updates the documents.
Change-Id: I1796f7aae5ed2d1799e91fabb8949607959cd9b3
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Add support for tabulating static memory consumption data from ELF
binaries. This relies on static symbols, defined in the linker files,
that provide information about the memory ranges.
Change-Id: Ie19cd2b80a7b591607640feeb84c63266963ea4d
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
This patch adds the errata management firmware interface for lower ELs
to discover details about CPU erratum. Based on the CPU erratum
identifier the interface enables the OS to find the mitigation of an
erratum in EL3.
The ABI can only be present in a system that is compliant with SMCCCv1.1
or higher. This implements v1.0 of the errata ABI spec.
For details on all possible return values, refer the design
documentation below:
ABI design documentation:
https://developer.arm.com/documentation/den0100/1-0?lang=en
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
Change-Id: I70f0e2569cf92e6e02ad82e3e77874546232b89a
This patch adds a helper API to explicitly refresh SBSA secure watchdog
timer. Please refer section A.3 of the following spec:
https://developer.arm.com/documentation/den0029/latest/
Change-Id: I2d0943792aea0092bee1e51d74b908348587e66b
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
FEAT_SME2 is an extension of FEAT_SME and an optional feature
from v9.2. Its an extension of SME, wherein it not only
processes matrix operations efficiently, but also provides
outer-product instructions to accelerate matrix operations.
It affords instructions for multi-vector operations.
Further, it adds an 512 bit architectural register ZT0.
This patch implements all the changes introduced with FEAT_SME2
to ensure that the instructions are allowed to access ZT0
register from Non-secure lower exception levels.
Additionally, it adds support to ensure FEAT_SME2 is aligned
with the existing FEATURE DETECTION mechanism, and documented.
Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
This was omitted from the patch adding the feature.
Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: Ie7f2b63434a70320178be74fc3f165618aca8392
Arm v9.4 introduces support for Guarded Control Stack, providing
mitigations against some forms of RPO attacks and an efficient mechanism
for obtaining the current call stack without requiring a full stack
unwind. Enable access to this feature for EL2 and below, context
switching the newly added EL2 registers as appropriate.
Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.
Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: I691aa7c22e3547bb3abe98d96993baf18c5f0e7b
These include directives were missing from both `uuid.h` files.
Change-Id: I875dfda3e0985728277b72f0e7597dde5cf9d304
Signed-off-by: Chris Kay <chris.kay@arm.com>
The FEATURE_DETECTION functionality had some definitions in a header
file, although they were only used internally in the .c file.
Move them over there, since there are of no interest to other users.
Also use the opportuntiy to rename the less telling FEAT_STATE_[12]
names, and let the "0" case join the game. We use DISABLED, ALWAYS, and
CHECK now, so that the casual reader has some idea what those numbers
are supposed to mean.
feature_panic() becomes "static inline", since disabling all features
makes it unused, so the compiler complains otherwise.
Finally add a new category "cpufeat" to cover CPU feature related
changes.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: If0c8ba91ad22440260ccff383c33bdd055eefbdc
This patch adds the following changes to complete the existing
TRNG implementation:
1. Adds a feature specific scope for buildlog generation.
2. Updates the docs on the build flag "TRNG_SUPPORT" and its values.
3. Makefile update and improves the existing comments at few sections
for better understanding of the underlying logic.
Change-Id: I3f72f0ccd5c94005a2df87158cf23199d2160d37
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Add missing scopes from commits for the upcoming release.
Change-Id: I22e38fb0658e42b45591c82aa30e063f7a7edc86
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
