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feat(rpi): add Raspberry Pi 5 support
The Raspberry Pi 5 is a single-board computer based on BCM2712 that contains four Arm Cortex-A76 cores. This change introduces minimal BL31 support with PSCI that has been validated to boot Linux and a private EDK2 build. It's a drop-in replacement for the custom TF-A armstub now included in the EEPROM images. Change-Id: Id72a0370f54e71ac97c3daa1bacedacb7dec148f Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
This commit is contained in:
Mario Bălănică
parent
6744d07d94
commit
f834b64f88
8 changed files with 416 additions and 0 deletions
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@ -541,6 +541,9 @@ subsections:
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- title: Raspberry Pi 4
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scope: rpi4
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- title: Raspberry Pi 5
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scope: rpi5
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- title: Renesas
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scope: renesas
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@ -37,6 +37,7 @@ Platform Ports
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qti-msm8916
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rpi3
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rpi4
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rpi5
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rcar-gen3
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rz-g2
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rockchip
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78
docs/plat/rpi5.rst
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78
docs/plat/rpi5.rst
Normal file
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@ -0,0 +1,78 @@
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Raspberry Pi 5
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==============
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The `Raspberry Pi 5`_ is a single-board computer that contains four
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Arm Cortex-A76 cores.
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This port is a minimal BL31 implementation capable of booting 64-bit EL2
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payloads such as Linux and EDK2.
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**IMPORTANT NOTE**: This port isn't secure. All of the memory used is DRAM,
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which is available from both the Non-secure and Secure worlds. The SoC does
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not seem to feature a secure memory controller of any kind, so portions of
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DRAM can't be protected properly from the Non-secure world.
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Build
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------------------
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To build this platform, run:
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.. code:: shell
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CROSS_COMPILE=aarch64-linux-gnu- make PLAT=rpi5 DEBUG=1
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The firmware will be generated at ``build/rpi5/debug/bl31.bin``.
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The following build options are supported:
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- ``RPI3_DIRECT_LINUX_BOOT``: Enabled by default. Allows direct boot of the Linux
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kernel from the firmware.
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- ``PRELOADED_BL33_BASE``: Used to specify the fixed address of a BL33 binary
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that has been preloaded by earlier boot stages (VPU). Useful for bundling
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BL31 and BL33 in the same ``armstub`` image (e.g. TF-A + EDK2).
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- ``RPI3_PRELOADED_DTB_BASE``: This option allows to specify the fixed address of
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a DTB in memory. Can only be used if ``device_tree_address=`` is present in
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config.txt.
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- ``RPI3_RUNTIME_UART``: Indicates whether TF-A should use the debug UART for
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runtime messages or not. ``-1`` (default) disables the option, any other value
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enables it.
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Usage
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------------------
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Copy the firmware binary to the first FAT32 partition of a supported boot media
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(SD, USB) and append ``armstub=bl31.bin`` to config.txt, or just rename the
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file to ``armstub8-2712.bin``.
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No other config options or files are required by the firmware alone, this will
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depend on the payload you intend to run.
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For Linux, you must also place an appropriate DTB and kernel in the boot
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partition. This has been validated with a copy of Raspberry Pi OS.
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The VPU will preload a BL33 AArch64 image named either ``kernel_2712.img`` or
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``kernel8.img``, which can be overridden by adding a ``kernel=filename`` option
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to config.txt.
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Kernel and DTB load addresses are also chosen by the VPU and can be changed with
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``kernel_address=`` and ``device_tree_address=`` in config.txt. If TF-A was built
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with ``PRELOADED_BL33_BASE`` or ``RPI3_PRELOADED_DTB_BASE``, setting those config
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options may be necessary.
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By default, all boot stages print messages to the dedicated UART debug port.
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Configuration is ``115200 8n1``.
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Design
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------------------
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This port is largely based on the RPi 4 one.
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The boot process is essentially the same, the only notable difference being that
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all VPU blobs have been moved into EEPROM (former start4.elf & fixup4.dat). There's
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also a custom BL31 TF-A armstub included for PSCI, which can be replaced with this
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port.
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.. _Raspberry Pi 5: https://www.raspberrypi.com/products/raspberry-pi-5/
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23
plat/rpi/rpi5/include/plat.ld.S
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23
plat/rpi/rpi5/include/plat.ld.S
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@ -0,0 +1,23 @@
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/*
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* Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Stub linker script to provide the armstub8.bin header before the actual
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* code. If the GPU firmware finds a magic value at offset 240 in
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* armstub8.bin, it will put the DTB and kernel load address in subsequent
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* words. We can then read those values to find the proper NS entry point
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* and find our DTB more flexibly.
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*/
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MEMORY {
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PRERAM (rwx): ORIGIN = 0, LENGTH = 4096
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}
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SECTIONS
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{
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.armstub8 . : {
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*armstub8_header.o(.text*)
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KEEP(*(.armstub8))
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} >PRERAM
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}
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141
plat/rpi/rpi5/include/platform_def.h
Normal file
141
plat/rpi/rpi5/include/platform_def.h
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@ -0,0 +1,141 @@
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/*
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* Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <lib/utils_def.h>
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#include <plat/common/common_def.h>
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#include "rpi_hw.h"
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/* Special value used to verify platform parameters from BL2 to BL31 */
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#define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
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#define PLATFORM_STACK_SIZE ULL(0x1000)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
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#define RPI_PRIMARY_CPU U(0)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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/* Local power state for power domains in Run state. */
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#define PLAT_LOCAL_STATE_RUN U(0)
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/* Local power state for retention. Valid only for CPU power domains */
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#define PLAT_LOCAL_STATE_RET U(1)
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/*
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* Local power state for OFF/power-down. Valid for CPU and cluster power
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* domains.
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*/
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#define PLAT_LOCAL_STATE_OFF U(2)
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/*
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* Macros used to parse state information from State-ID if it is using the
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* recommended encoding for State-ID.
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*/
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#define PLAT_LOCAL_PSTATE_WIDTH U(4)
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#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1)
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_SHIFT U(6)
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#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
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/*
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* I/O registers.
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*/
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#define DEVICE0_BASE RPI_IO_BASE
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#define DEVICE0_SIZE RPI_IO_SIZE
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/*
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* Mailbox to control the secondary cores. All secondary cores are held in a
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* wait loop in cold boot. To release them perform the following steps (plus
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* any additional barriers that may be needed):
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*
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* uint64_t *entrypoint = (uint64_t *)PLAT_RPI3_TM_ENTRYPOINT;
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* *entrypoint = ADDRESS_TO_JUMP_TO;
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*
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* uint64_t *mbox_entry = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE;
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* mbox_entry[cpu_id] = PLAT_RPI3_TM_HOLD_STATE_GO;
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*
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* sev();
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*/
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/* The secure entry point to be used on warm reset by all CPUs. */
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#define PLAT_RPI3_TM_ENTRYPOINT 0x100
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#define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8)
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/* Hold entries for each CPU. */
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#define PLAT_RPI3_TM_HOLD_BASE (PLAT_RPI3_TM_ENTRYPOINT + \
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PLAT_RPI3_TM_ENTRYPOINT_SIZE)
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#define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8)
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#define PLAT_RPI3_TM_HOLD_SIZE (PLAT_RPI3_TM_HOLD_ENTRY_SIZE * \
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PLATFORM_CORE_COUNT)
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#define PLAT_RPI3_TRUSTED_MAILBOX_SIZE (PLAT_RPI3_TM_ENTRYPOINT_SIZE + \
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PLAT_RPI3_TM_HOLD_SIZE)
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#define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0)
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#define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1)
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#define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF ULL(2)
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/*
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* BL31 specific defines.
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*
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* Put BL31 at the top of the Trusted SRAM. BL31_BASE is calculated using the
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* current BL31 debug size plus a little space for growth.
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*/
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#define PLAT_MAX_BL31_SIZE ULL(0x80000)
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#define BL31_BASE ULL(0x1000)
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#define BL31_LIMIT ULL(0x80000)
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#define BL31_PROGBITS_LIMIT ULL(0x80000)
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#define SEC_SRAM_ID 0
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#define SEC_DRAM_ID 1
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/*
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* Other memory-related defines.
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*/
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#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40)
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#define MAX_MMAP_REGIONS 8
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#define MAX_XLAT_TABLES 4
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#define MAX_IO_DEVICES U(3)
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#define MAX_IO_HANDLES U(4)
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#define MAX_IO_BLOCK_DEVICES U(1)
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/*
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* Serial-related constants.
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*/
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#define PLAT_RPI_PL011_UART_BASE RPI4_PL011_UART_BASE
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#define PLAT_RPI_PL011_UART_CLOCK RPI4_PL011_UART_CLOCK
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#define PLAT_RPI_UART_BAUDRATE ULL(115200)
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#define PLAT_RPI_CRASH_UART_BASE PLAT_RPI_PL011_UART_BASE
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/*
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* System counter
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*/
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#define SYS_COUNTER_FREQ_IN_TICKS ULL(54000000)
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#endif /* PLATFORM_DEF_H */
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51
plat/rpi/rpi5/include/rpi_hw.h
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51
plat/rpi/rpi5/include/rpi_hw.h
Normal file
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/*
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* Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RPI_HW_H
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#define RPI_HW_H
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#include <lib/utils_def.h>
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/*
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* Peripherals
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*/
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#define RPI_IO_BASE ULL(0x1000000000)
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#define RPI_IO_SIZE ULL(0x1000000000)
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/*
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* ARM <-> VideoCore mailboxes
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*/
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#define RPI3_MBOX_BASE (RPI_IO_BASE + ULL(0x7c013880))
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/*
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* Power management, reset controller, watchdog.
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*/
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#define RPI3_PM_BASE (RPI_IO_BASE + ULL(0x7d200000))
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/*
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* Hardware random number generator.
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*/
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#define RPI3_RNG_BASE (RPI_IO_BASE + ULL(0x7d208000))
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/*
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* PL011 system serial port
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*/
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#define RPI4_PL011_UART_BASE (RPI_IO_BASE + ULL(0x7d001000))
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#define RPI4_PL011_UART_CLOCK ULL(44000000)
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/*
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* GIC interrupt controller
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*/
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#define RPI_HAVE_GIC
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#define RPI4_GIC_GICD_BASE (RPI_IO_BASE + ULL(0x7fff9000))
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#define RPI4_GIC_GICC_BASE (RPI_IO_BASE + ULL(0x7fffa000))
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#define RPI4_LOCAL_CONTROL_BASE_ADDRESS (RPI_IO_BASE + ULL(0x7c280000))
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#define RPI4_LOCAL_CONTROL_PRESCALER (RPI_IO_BASE + ULL(0x7c280008))
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#endif /* RPI_HW_H */
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107
plat/rpi/rpi5/platform.mk
Normal file
107
plat/rpi/rpi5/platform.mk
Normal file
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@ -0,0 +1,107 @@
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#
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# Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
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# Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include lib/xlat_tables_v2/xlat_tables.mk
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include drivers/arm/gic/v2/gicv2.mk
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PLAT_INCLUDES := -Iplat/rpi/common/include \
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-Iplat/rpi/rpi5/include
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PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/aarch64/pl011_console.S \
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plat/rpi/common/rpi3_common.c \
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plat/rpi/common/rpi3_console_pl011.c \
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${XLAT_TABLES_LIB_SRCS}
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BL31_SOURCES += lib/cpus/aarch64/cortex_a76.S \
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plat/rpi/common/aarch64/plat_helpers.S \
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plat/rpi/common/aarch64/armstub8_header.S \
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drivers/delay_timer/delay_timer.c \
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plat/common/plat_gicv2.c \
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plat/rpi/common/rpi4_bl31_setup.c \
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plat/rpi/rpi5/rpi5_setup.c \
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plat/rpi/common/rpi3_pm.c \
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plat/common/plat_psci_common.c \
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plat/rpi/common/rpi3_topology.c \
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${GICV2_SOURCES}
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# For now we only support BL31, using the kernel loaded by the GPU firmware.
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RESET_TO_BL31 := 1
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# All CPUs enter armstub8.bin.
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COLD_BOOT_SINGLE_CPU := 0
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# Tune compiler for Cortex-A76
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ifeq ($(notdir $(CC)),armclang)
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TF_CFLAGS_aarch64 += -mcpu=cortex-a76
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else ifneq ($(findstring clang,$(notdir $(CC))),)
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TF_CFLAGS_aarch64 += -mcpu=cortex-a76
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else
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TF_CFLAGS_aarch64 += -mtune=cortex-a76
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endif
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# Add support for platform supplied linker script for BL31 build
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$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
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# Enable all errata workarounds for Cortex-A76 r4p1
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ERRATA_A76_1946160 := 1
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ERRATA_A76_2743102 := 1
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# Add new default target when compiling this platform
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all: bl31
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# Build config flags
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# ------------------
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# Disable stack protector by default
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ENABLE_STACK_PROTECTOR := 0
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# Have different sections for code and rodata
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SEPARATE_CODE_AND_RODATA := 1
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# Hardware-managed coherency
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HW_ASSISTED_COHERENCY := 1
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USE_COHERENT_MEM := 0
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# Cortex-A76 is 64-bit only
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CTX_INCLUDE_AARCH32_REGS := 0
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# Platform build flags
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# --------------------
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# There is not much else than a Linux kernel to load at the moment.
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RPI3_DIRECT_LINUX_BOOT := 1
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# BL33 images can only be AArch64 on this platform.
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RPI3_BL33_IN_AARCH32 := 0
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# UART to use at runtime. -1 means the runtime UART is disabled.
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# Any other value means the default UART will be used.
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RPI3_RUNTIME_UART := 0
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# Use normal memory mapping for ROM, FIP, SRAM and DRAM
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RPI3_USE_UEFI_MAP := 0
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# Process platform flags
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# ----------------------
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$(eval $(call add_define,RPI3_BL33_IN_AARCH32))
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$(eval $(call add_define,RPI3_DIRECT_LINUX_BOOT))
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ifdef RPI3_PRELOADED_DTB_BASE
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$(eval $(call add_define,RPI3_PRELOADED_DTB_BASE))
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endif
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$(eval $(call add_define,RPI3_RUNTIME_UART))
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$(eval $(call add_define,RPI3_USE_UEFI_MAP))
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ifeq (${ARCH},aarch32)
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$(error Error: AArch32 not supported on rpi5)
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endif
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ifneq ($(ENABLE_STACK_PROTECTOR), 0)
|
||||
PLAT_BL_COMMON_SOURCES += drivers/rpi3/rng/rpi3_rng.c \
|
||||
plat/rpi/common/rpi3_stack_protector.c
|
||||
endif
|
||||
12
plat/rpi/rpi5/rpi5_setup.c
Normal file
12
plat/rpi/rpi5/rpi5_setup.c
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <rpi_shared.h>
|
||||
|
||||
void plat_rpi_bl31_custom_setup(void)
|
||||
{
|
||||
/* Nothing to do here yet. */
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue