RK3566/RK3568 is a Quad-core soc and Cortex-a55 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4. suspend/resume system
5. reset system
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I8b98a4d07664de26bd6078f63664cbc3d9c1c68c
This patch fixes fill_l1_tbl() function bug
for RME_GPT_MAX_BLOCK build option set to 0
disabling filling L1 tables with Contiguous
descriptors.
Change-Id: I3eedd6c1bb55b7c207bb3630d1ab2fda8f72eb17
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Today, the PM_IOCTL and PM_QUERY_DATA APIs are there to maintain
backward compatibility. Now, the usage of these APIs on the Linux
side and the firmware side is updated. Hence remove the deprecated
PM_IOCTL and PM_QUERY_DATA EEMI API from the TF-A to make TF-A pass
through.
Note: Only use the newer kernel to access the deprecated features in
this patch. Otherwise, the system may not function correctly.
Change-Id: I23effb7ff62e7f83563c2b422ea64a0289fd880f
Signed-off-by: Ronak Jain <ronak.jain@amd.com>
MAP_DEVICE0 for internal (register) space access settings
flag MT_NS was changed to MT_SECURE to enable access
to the TSGEN register, otherwise it brings to MCR violation,
because access to the TSGEN register is locked and enabled
for secure only
Change-Id: Id2fe90d30342706c58064161360d8be6e0d5616b
Signed-off-by: Margarita Glushkin <rutigl@gmail.com>
The Makefile rule for the libwrappers object files places a dependency
on a timestamp file. This timestamp file is created by the recipe that
generates the libwrappers sources, and was presumably introduced to
indicate to Make that all of the source files are generated
simultaneously by that rule.
Instead, we can use a grouped target rule, which uses `&:` instead of
`:`. This communicates to Make that all of the targets listed are
generated at once.
To demonstrate, the following two Makefile rules differ in their
behaviour:
a.x b.x c.x: # targets may be updated independently
... # generate a.x, b.x and c.x
a.x b.x c.x &: # all targets are updated at once
... # generate a.x, b.x and c.x
While both recipes do generate all three files, only the second rule
communicates this fact to Make. As such, Make can reason that if one of
the files is up to date then all of them are, and avoid re-running the
rule for any generated file that it has not already run it for.
Change-Id: I10b49eb72b5276c7f9bd933900833b03a61cff2f
Signed-off-by: Chris Kay <chris.kay@arm.com>
The `romlib_generator.py` script may generate duplicate wrapper sources,
which is undesirable when using them to generate Makefile rules as Make
will warn about duplicated targets.
This change sorts the wrapper sources returned from this script, which
has the effect of also de-duplicating them.
Change-Id: I109607ef94f77113a48cc0d6e07877efd1971dbc
Signed-off-by: Chris Kay <chris.kay@arm.com>
Preprocessor definitions that are passed to armlink are currently not
correctly escaped, resulting in the shell trying to parse the
parentheses contained in some of the preprocessor definitions:
```
LD build/tegra/t210/release/bl31/bl31.elf
/bin/sh: 1: Syntax error: "(" unexpected
```
This change ensures that these preprocessor definitions are adequately
escaped for the shell.
Change-Id: I9d2c60fa60c0aa00770417a68f900e9fb84b4669
Signed-off-by: Chris Kay <chris.kay@arm.com>
This patch updates GPT library design documentation
with the changes introduced by patches which add
support for large GPT mappings and configuration of
memory size protected by bitlock.
Change-Id: I1f97fa8f003deb07a5f32b7237c1927581a788c8
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Add an `stdout-path' property into the `chosen' node of the Foundation
FVPs Devicetrees.
This gives a default console to the Linux kernel when "console=" is not
specified on the kernel command line, which is useful when booting with
U-Boot in UEFI for example.
Change-Id: I27d5f7f9416bd42b7401b1a57ae64bfee2524204
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
'cpu_partnumber' variable part of 'em_cpu_list' actually contains the
cpu midr value and not the actual part number. The part number is
extracted from midr value in 'non_arm_interconnect_errata' function.
So 'cpu_partnumber' is misleading and the actual value is midr, thus
rename it to 'cpu_midr'.
Change-Id: I4bfe71ce24542d508e2bcf39a1097724d14c4511
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
* changes:
feat(tc): add MHUv3 addresses between RSS and AP
feat(tc): specify MHU version based on platform
feat(tc): bind SCMI over MHUv3 for TC3
feat(tc): add MHUv3 DT binding for TC3
feat(tc): add MHUv3 doorbell support on TC3
refactor(tc): change tc_scmi_plat_info to single structure
As per the GPU integration guide, adding the PBHA INT overrides to
influence the GPU allocation policy for the System Level Cache (SLC).
This commit uses SLC policy #23, which is the Arm SLC cache policy
number for GPUs. The cache policy #23 may not be optimal for all
workloads, although it outperforms other policies on the tested data
sets.
Change-Id: I19ddbcf52a2f01af0ab6dfd7cc25b2e438b9014a
Signed-off-by: Angel Rodriguez Garcia <angel.rodriguezgarcia@arm.com>
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
* FEAT_MPAM related EL2 registers are placed explicitly outside
the EL2 context in the cpu_context_t structure.
* With EL2 registers now coupled with dependent features, this
patch moves them to the el2_context structure "el2_sysregs_t".
* Further, converting the assembly context-offset entries into a
c structure. It relies on garbage collection of the linker
removing unreferenced structures from memory, as well as aiding
in readability and future maintenance.
Change-Id: Ib784bc8d2fbe35a8a47a569426d8663282ec06aa
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
* changes:
feat(imx8mp): optionally take params from BL2
feat(imx8mn): optionally take params from BL2
feat(imx8mm): optionally take params from BL2
feat(imx93): optionally take params from BL2
feat(imx): add helper to take params from BL2
- Update SVP EMI-MPU region ID from 4 to 5 for resolving
the issue of duplicate region ID used by the DSP.
- For SVP EMI-MPU region, modify domain 1 and domain 6 APC from
FORBIDDEN to SEC_RW.
- Correct the calculation for the end address of SVP DRAM region.
- Add region 0 and region 1 for BL31 and BL32 memory protection.
- Add clear region protection API for SVP region.
Change-Id: Iaea348ad9be629e8a81cf579b148c6df66015b42
Signed-off-by: Haohao Sun <haohao.sun@mediatek.corp-partner.google.com>
- Reduce core0 memory usage from 41MB to 8MB.
- Increase core1 memory to 160MB to fulfill user-specific features.
Change-Id: I35547e2ac928945c244883d2333f921ce578bbd1
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
The flag STM32MP15_OPTEE_RSV_SHM was disabled and mark deprecated.
Remove the corresponding code.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I948af3e1de4b89815c967a63abe64f285c405ecc
Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.11.0
Change-Id: I34c7b342549781057da1b18116500f110bc3f5ad
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Juan Pablo Conde <JuanPablo.Conde@arm.com>
Enable full-HD resolution (1920x1080p60) for the FVP model, and add
checking for the passed resolution parameter.
Change-Id: I5e37ae79b5ceac088a18d5acf00ff4a557bb56aa
Signed-off-by: Sergio Alves <sergio.dasilvalves@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
TC3 is upgraded to MHUv3. This patch adds the address of the MHU
channel to be used by TF-A for communications with the RSS.
Change-Id: I1bf5d72dc92bcd9d0509ba806095b24293875e85
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Platforms older than TC2 contain MHUv2 well as newer platforms contain
MHUv3. Set the Makefile variable accordingly.
Change-Id: I00b83a34908cdbf7d1d9ac39728e3fa6ef449d2c
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
TC2 and TC3 have different the scmi shared memory regions and MHU
parameters, this patch appends the properties in scmi node for TC2 and
TC3 respectively.
Change-Id: Ifd001f780b575987877b4be36eb755a9dbe57e60
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
MHUv3's device tree is different from MHUv2's. Add support MHUv3 DT
binding for TC3 while keeping TC2 as-is.
Change-Id: Ib2f55d3a64a4cfe2ea9e62fe39d27ed54a2ca007
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Enables the doorbell channels in MHUv3 for TC3.
Change-Id: Ib4f47df3e54f9182939ea6c1d8bc1a66a3c03094
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Currently, as the Total Compute system uses a single channel for MHU,
it's useless to define the structure 'tc_scmi_plat_info' as an array.
Change it as a single structure.
Change-Id: Iaa7c853327e7f5e67ccc14d12c5f0ef68d75dfd7
Signed-off-by: Leo Yan <leo.yan@arm.com>
Since DPE support is experimental, move the build option for
the DPE to the experimental section.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I2e18947d37c52a0151b5ac656098dbae51254956
This patch adds support in GPT library for configuration
of the memory block size protected by one bit of 'bitlock'
structure. Build option 'RME_GPT_BITLOCK_BLOCK' defines the
number of 512MB blocks covered by each bit. This numeric
parameter must be a power of 2 and can take the values from
0 to 512. Setting this value to 0 chooses a single spinlock
for all GPT L1 table entries. The default value is set to 1
which corresponds to 512MB per bit.
Change-Id: I710d178072894a3ef40daebea701f74d19e8a3d7
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Add the latest instrumentation data as of v2.11-rc0, remove data for
v2.9.
Change-Id: I8c055278d732220a9be88978ed63d27e453b7f2f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
