This change adjusts the Dependabot settings for the LTS branches such
that Dependabot does not open pull requests for changes which anything
more substantial than patch updates (typically security fixes).
Change-Id: Icc203038e8069e723926849a33c3e8784b544053
Signed-off-by: Chris Kay <chris.kay@arm.com>
We have one entry per CPU features but most of the time we just add
CPU feature and its not touched again, so considering to generalize
anything with FEAT_XXXX additions to use `cpufeat` as subsection scope.
Also, some time we don't add a scope for CPU feature this causes problem
while generating release notes as CPU feature additions ends up in wrong
section.
Change-Id: Ibc80f6cdab9ae10ec3af1485640f46771b382da0
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
To ease release note preparation, add some missing scope in the
changelog.yaml file.
Change-Id: I9426cf7b90455a487c4653c3fc9a6a718c13df7b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
The STM32MP2 family has 3 different types of SoCs (STM32MP25, STM32MP23
and STM32MP21). For the moment only STM32MP25 is partly supported in
TF-A. Add a dedicated subsections for STM32MP25. The other ones will be
added later. The same is done for FDTS scope.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Ia18824a7b649bcd1ffa631e3aa0ecb3fd0b2d038
In order to avoid separate platform definitions when not using the
default timer functions, it is better to move these functions out of the
header file and into the source files, so that they can be built if
needed.
Move timer functions from delay_timer.h into generic_delay_timer.c. Add
them as callback functions which are then called in delay_timer.c.
Change-Id: I96a1eac8948b1a7b1e481899b67a083db4c9b97d
Signed-off-by: Abhi Singh <abhi.singh@arm.com>
Create a new platform for the RD-1 AE automotive FVP.
This platform contains:
* Neoverse-V3AE, Arm9.2-A application processor
* A GICv4-compatible GIC-720AE
* 128 MB of SRAM, of which 1 MB is reserved for TF-A
and BL2 runs at ELmax (EL3).
Additionally, this commit updates the maintainers.rst file and
the changelog.yaml to add scope for RD-1 AE variants.
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Signed-off-by: Divin Raj <divin.raj@arm.com>
Signed-off-by: Rahul Singh <rahul.singh@arm.com>
Change-Id: I9ae64b3f05a52653ebd1d334b15b7f21821264e2
Update the test files to eliminate the use of preprocessor macros,
as the tool now requires processed output. The documentation has
also been revised accordingly.
Additionally, remove the Device Tree Source test files that were
added to test the #ifdef conditions.
Change-Id: I13a682db20e5e44170fc25a2e2dbedd45b9c7321
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
From a context management perspective, we refer to SVE and FP state
as SIMD. SVE can be considered as a superset of FP/NEON functionality
and there is a architectural dependency between the two due to the fact
that FP registers occupy the bottom 128 bits of SVE Z vector registers.
This patch introduces a new data structure to hold the FP state of a CPU
as needed for context management operations during world switch events.
It will evolve in next patches to capture the SVE state as well.
Having this unified data structure is necessary for us to implement
SIMD context management while catering to various build configurations.
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: If2a9a7526883780df49bbd3dade2f09f7c3d95ae
Transfer List Compiler is a command line tool that enables the static
generation of TL's compliant with version 0.9 of the firmware handoff
specification. The intent of this tool is to support information passing
via the firmware handoff framework to bootloaders that run without
preceding images (i.e. `RESET_TO_BL31`).
It currently allows for TL's to be statically generated from blobs of
data, and modified by removing/adding TE's. Future work will provide
support for TL generation from configuration file.
Change-Id: Iff670842e34c9ad18eac935248ee2aece43dc533
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Co-authored-by: Charlie Bareham <charlie.bareham@arm.com>
This patch disables trapping to EL3 when the FEAT_FGT2
specific trap registers are accessed by setting the
SCR_EL3.FGTEn2 bit
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I6d2b614affb9067b2bc3d7bf0ae7d169d031592a
This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3613af1dd8cb8c0d3c33dc959f170846c0b9695a
This is a small change to split up the generation of the RZ/G layout
images into unique targets. This is predominantly for cleanliness
reasons - Make current doesn't know about the `.bin` and `.srec`
binaries generated by the `.elf` target.
Change-Id: I81251ac647b85c5eec8f910ddc841a5a32b49e67
Signed-off-by: Chris Kay <chris.kay@arm.com>
This is a small change to split up the generation of the R-Car layout
images into unique targets. This is predominantly for cleanliness
reasons - Make current doesn't know about the `.bin` and `.srec`
binaries generated by the `.elf` target.
Change-Id: I624bc0c62e99cead66a6d6e25ff016aecf6b985a
Signed-off-by: Chris Kay <chris.kay@arm.com>
Arm has decided to rename RD-Fremont to RD-V3 to align with its
existing product lineup, such as RD-V1, RD-V2, etc. This change
replaces all occurences of "Fremont" with "V3" in file names and
contents.
Change-Id: I302103492f962a7ac74854633ad68701b2a7f420
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>
This change avoids generating a build message source file on the shell,
instead using the `__DATE__` and `__TIME__` macros directly.
Change-Id: Ida537d4c3e550f2fbbd977472ed6573491d17c23
Signed-off-by: Chris Kay <chris.kay@arm.com>
The S32CC is an umbrella for S32G2, S32G3 and S32R45 SoCs; therefore,
this clock driver will be used for all of these families.
Change-Id: Iede5371b212b67cf494a033c62fbfdcbe9b1a879
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal NET platform. System starts with AMD PLM
firmware which loads TF-A(bl31) to memory, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.
Change-Id: I5065b1b7ec4ee58e77dc4096747758480c84009c
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
As RD-Fremont and its variants would need a dedicated scope for use,
define the scope 'rdfremont' under the subsection within Neoverse-RD
platforms.
Change-Id: I7066824a33edd893e187ec397298b49392ac35da
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.11.0
Change-Id: I34c7b342549781057da1b18116500f110bc3f5ad
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Juan Pablo Conde <JuanPablo.Conde@arm.com>
* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fvp): change all occurrences of RSS to RSE
refactor(fiptool): change all occurrences of RSS to RSE
refactor(psa): change all occurrences of RSS to RSE
refactor(fvp): remove leftovers from rss measured boot support
refactor(tc): change all occurrences of RSS to RSE
docs: change all occurrences of RSS to RSE
refactor(measured-boot): change all occurrences of RSS to RSE
refactor(rse): change all occurrences of RSS to RSE
refactor(psa): rename all 'rss' files to 'rse'
refactor(tc): rename all 'rss' files to 'rse'
docs: rename all 'rss' files to 'rse'
refactor(measured-boot): rename all 'rss' files to 'rse'
refactor(rss): rename all 'rss' files to 'rse'
S32G274ARDB2 is a development board to showcase the capabilities of the
S32G2 SoC. It includes 4 ARM Cortex-A53 cores running at 1.0GHz, 4GBs
of DDR, accelerators for automotive networking and many other
peripherals.
The added support is minimal and only includes the BL2 stage, with no
MMU enabled. The FIP is preloaded by the BootROM in SRAM, and BL2 copies
BL31 and BL33 from FIP to their designated addresses.
Change-Id: Iedda23302768ab70d63787117c5f6f3c21eb9842
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Bogdan Roman <bogdan-gabriel.roman@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
The title for RD-N1-Edge was written as "RD-N1 Edge" in the changelog
file. This has been corrected to "RD-N1-Edge" to pedantically reflect
the proper name for the platform.
Change-Id: I17a0f8745117674482e7c668109d821c81e35d1d
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
As RD-V1-MC would need a dedicated scope for use, define the scope
'rdv1mc' under the subsection within Neoverse-RD platforms.
Change-Id: I5fd53ce89815e355b595fe7ff066386842b7af03
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
As RD-V1 would need a dedicated scope for use, define the scope
'rdv1' under the subsection within Neoverse-RD platforms.
Change-Id: I035499e1ce85d6efd54ac4fe74ff6185367a07aa
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
As SGI-575 would need a dedicated scope for use, define the scope
'sgi575' under the subsection within Neoverse-RD platforms.
Change-Id: I872dc3bceace5c3358cde24fff1c4c17207ec962
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
As sgi has migrated to neoverse_rd, the scope variables would need
update. Therefore, remove the deprecated 'sgi' scope variable and
introduce the new scope variable 'neoverse-rd' to be used for any common
platform changes associated with Neoverse Reference Design platforms.
Change-Id: I5052e4573bdc7df3e6f4257146d716edd2585452
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I66a6c87c158b14e18cba25ea6c6e0809e30008ca
* changes:
feat(rpi): add Raspberry Pi 5 support
fix(rpi): consider MT when calculating core index from MPIDR
refactor(rpi): move register definitions out of rpi_hw.h
refactor(rpi): add platform macro for the crash UART base address
refactor(rpi): split out console registration logic
refactor(rpi): move more platform-specific code into common
The Raspberry Pi 5 is a single-board computer based on BCM2712 that
contains four Arm Cortex-A76 cores.
This change introduces minimal BL31 support with PSCI that has been
validated to boot Linux and a private EDK2 build.
It's a drop-in replacement for the custom TF-A armstub now included in
the EEPROM images.
Change-Id: Id72a0370f54e71ac97c3daa1bacedacb7dec148f
Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
To cover the DICE related works such as
DICE Protection Environment (DPE) integration
with the measurd boot framework.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I9769b7bddbd1d269705ebff1d15870ab928fd8ef
* changes:
build: remove the `NM` variable
build: prefer `gcc-ar` over `ar`
build: add `--no-warn-rwx-segments` when linking with GCC
build: always use the C compiler to assemble
build: always use the C compiler to preprocess
fix(rcar): fix implicit rule invocations in tools
The ROM library is the only component in the repository that compiles
assembly files using the assembler directly. This change migrates it to
the C compiler instead, like the rest of the project.
Change-Id: I6c50660eeb9be2ca8dcb0e626c37c197466b0fa1
Signed-off-by: Chris Kay <chris.kay@arm.com>
mbedtls/version.h needs to be included before the use of any
mbedtls config variables.
Fixes a build failure regression from commit a8eadc51a.
Change-Id: Idd955d7955b0a55ffd127f31053335542cb15e22
Signed-off-by: Henrik Nordstrom <henrik.nordstrom@addiva.se>
Added changelog for v2.10 release.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Id06263047fcc1ec60e82f85cd09e2e4bc95830f5
This reverts commit 0abbfab320.
Reason for revert: Changelog was based on rc0 tag but we got few more patches after that which were not captured.
Change-Id: I9829f2b6dc09f0bd5c538845cbae051f6e4c8a75
Added scope for MbedTLS PSA Crypto API implementation.
Change-Id: I0a7c6242841dfb94f6ca5e9174ffd520c5fe00fa
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Add new scope for the JTAG DCC (Debug Communication Channel).
Driver is available for quite some time at
drivers/arm/dcc/dcc_console.c.
Change-Id: I8be71dadb56bed2b64a26c8a009bda6bbc96240d
Signed-off-by: Michal Simek <michal.simek@amd.com>
The generic interrupt controller identifies an interrupt based on its
type whereas the GIC uses the notion of groups to identify an
interrupt.
This patch changes the name of the helper functions to use group
rather than type for handling interrupts. No functional change in this
patch.
Change-Id: If13ec65cc6c87c2da73a3d54b033f02635ff924a
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
