Commit graph

11034 commits

Author SHA1 Message Date
Yann Gautier
936f29f6b5 feat(stm32mp13-fdts): use STM32MP_DDR_S_SIZE in fw-config
Align with STM32MP15 file, use the macro STM32MP_DDR_S_SIZE, instead of
an hard-coded value.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ib31bed1ffe89ff221fab1884a2db729ce1e21846
2022-08-17 17:25:45 +02:00
Yann Gautier
4c07deb53e fix(stm32mp13-fdts): cleanup DT files
Instead of adding all peripheral nodes in SoC DT files, and then
removing them with BL2 overlay file, just remove them from SoC files.
And remove peripherals that are not used in TF-A on STM32MP13.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I0c408d29b55cb94644c92539460fc62485781223
2022-08-17 17:24:30 +02:00
Yann Gautier
c9a4cb552c fix(stm32mp13-fdts): update SDMMC max frequency
On STM32MP13, the max frequency for IOs is 130MHz, update the SDMMC
max-frequency property with this value. This is an alignment with
Linux DT file.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: If4b364f53f87d4b5d276a976af486a3bf083f49b
2022-08-17 17:18:25 +02:00
Yann Gautier
c7ac7d65a7 fix(stm32mp13-fdts): align sdmmc pins with kernel
Update the pinctrl nodes for sdmmc instances in stm32mp13-pinctrl.dtsi
file to align with Linux. The boards DT files then need to be updated
accordingly.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4e1f3cf78794bfb7bbe53cfc7e88623c7e79855d
2022-08-17 17:18:25 +02:00
Madhukar Pappireddy
afbb10abdc Merge changes from topic "st-mmc-updates" into integration
* changes:
  feat(st-sdmmc2): define FIFO size
  feat(st-sdmmc2): make reset property optional
  feat(st): enable MMC_FLAG_SD_CMD6 for SD-cards
  feat(st-sdmmc2): manage CMD6
  feat(mmc): manage SD Switch Function for high speed mode
2022-08-17 16:33:10 +02:00
Madhukar Pappireddy
51d52c7923 Merge changes from topic "st-etzpc-cleanup" into integration
* changes:
  refactor(stm32mp15-fdts): remove ETZPC status
  refactor(st-drivers): do not rely on DT in etzpc_init
2022-08-17 16:32:55 +02:00
Yann Gautier
b46f74d4e6 feat(st-sdmmc2): define FIFO size
Instead of using hard-coded values in stm32_sdmmc2_read() function,
use a defined SDMMC_FIFO_SIZE, which is 64 on STM32MP1.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I1ace0a28fbddae474379f0187371b9c360ceb7b3
2022-08-16 15:58:22 +02:00
Yann Gautier
8324b16cd5 feat(st-sdmmc2): make reset property optional
Although not recommended, the reset property could be made optional.
This way the driver will probe even if no reset property is provided
in an sdmmc node in DT. This reset is already optional in Linux.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I6e63ff00118d9497f505d6379982334dd62686ca
2022-08-16 15:58:22 +02:00
Yann Gautier
53d5b8ff50 feat(st): enable MMC_FLAG_SD_CMD6 for SD-cards
This flag allows switching to High-Speed mode on SD-cards.
The gain is ~44ms when using SP_min, and ~55ms with OP-TEE.

Change-Id: Ic396c6a14201580b5e5627e6174b85b437b87cae
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-08-16 15:58:22 +02:00
Yann Gautier
3deebd4ccf feat(st-sdmmc2): manage CMD6
For SD-cards, CMD6 is used to switch functions, like setting high speed
mode. As it has another meaning for eMMC, and may not work on standard
capacity SD-cards, it must be checked with MMC_IS_SD_HC flag.
As ACMD6 is also used, and will have the same index, a check on
CMD/ACMD commands is done: a boolean is stored depending on previous
command. It is set to true if CMD55 is issued, for other commands
it is set to false.

Change-Id: I6c2b9c7637656f858601ec075de1cb5f57af271a
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-08-16 15:58:22 +02:00
Yann Gautier
e5b267bba1 feat(mmc): manage SD Switch Function for high speed mode
On SD-cards, Switch Function Command (CMD6) is used to switch
functions, like setting High Speed mode. It is useful for high capacity
cards to double frequency (from 25MHz by default to 50MHz).
If the SD-card is High Capacity, a CMD6 is issued after filling the
device information. If High Speed mode is supported and the switch is
OK, then the max_bus_freq can be set to 50MHz. The driver set_ios()
function should then be called to update peripheral configuration,
especially clock prescaler.

Change-Id: I2d6807aa7f9440d2b2f907a747cd3b47a2ba1545
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-08-16 15:58:22 +02:00
Julius Werner
958b839664 Merge "refactor(bl31): introduce vendor extend rodata section" into integration 2022-08-16 02:12:01 +02:00
Madhukar Pappireddy
a36af977f0 Merge changes from topic "st-clk-cleanup" into integration
* changes:
  refactor(st-clock): code size optimization
  refactor(st-clock): remove unused PLL field
2022-08-15 22:38:59 +02:00
Madhukar Pappireddy
6a5022278b Merge "fix(errata): workaround for Neoverse-V1 erratum 1618635" into integration 2022-08-11 22:51:42 +02:00
Joanna Farley
53be5274ff Merge "fix(build): discard sections also with SEPARATE_NOBITS_REGION" into integration 2022-08-11 22:27:21 +02:00
Bipin Ravi
5d75d71570 Merge "fix(build): disable default PIE when linking" into integration 2022-08-11 19:08:51 +02:00
Madhukar Pappireddy
8f23476e39 Merge "feat(bl): add interface to query TF-A semantic ver" into integration 2022-08-11 18:02:30 +02:00
Samuel Holland
64207f858f fix(build): discard sections also with SEPARATE_NOBITS_REGION
Some linker sections are discarded since 511046eaa2 ("BL31: discard
.dynsym .dynstr .hash sections to make ENABLE_PIE work"). However, that
logic was placed inside a preprocessor condition, so it only applied to
the !SEPARATE_NOBITS_REGION case. Move the /DISCARD/ block down so it
applies in all cases.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I6604609f2321a2a9c32a25721a697c320108a974
2022-08-10 20:23:12 -05:00
Samuel Holland
7b59241845 fix(build): disable default PIE when linking
Commit f7ec31db2d ("Disable PIE compilation option") allowed building a
non-relocatable firmware with a default-PIE toolchain by disabling PIE
at compilation time. This prevents the compiler from generating
relocations against a GOT.

However, when a default-PIE GCC is used as the linker, the final binary
will still be a PIE, containing an (unused) GOT and dynamic symbol
table. These structures do not affect execution, but they waste space in
the firmware binary. Disable PIE at link time to recover this space.

Change-Id: I2be7ac9c1a957f6db8d75efe6e601e9a5760a925
Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-08-10 20:23:12 -05:00
Bipin Ravi
f924258da7 Merge "fix(bl31): pass the EA bit to 'delegate_sync_ea'" into integration 2022-08-10 15:45:55 +02:00
Yann Gautier
33223c3ade refactor(stm32mp15-fdts): remove ETZPC status
The ETZPC is always secure, and the driver does no more rely on
secure-status (and status) DT property. Remove them from the SoC
DT file.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I5f1d3534679553d79e6866396cd70e21a595ef6a
2022-08-10 10:00:16 +02:00
Yann Gautier
e9ff3486d3 refactor(st-drivers): do not rely on DT in etzpc_init
The ETZPC peripheral is always secure, and has a fixed address,
given by STM32MP1_ETZPC_BASE. This is then not needed to check
that in DT.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ifb0779abaf830e1e5a469c72181c2b2726fb47b5
2022-08-10 10:00:03 +02:00
Gabriel Fernandez
3ff1ff4047 refactor(st-clock): code size optimization
Clock name is not used and can be removed for code size optimization.

Change-Id: I75f6a1828e4374004e31a7ce13fa6885c52bbac3
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
2022-08-10 09:56:32 +02:00
Gabriel Fernandez
b44f5acf5d refactor(st-clock): remove unused PLL field
The divn_max field is unused, remove it.

Change-Id: I971912bcc035f16963d98dfa88782c8aed4415f2
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
2022-08-10 09:56:32 +02:00
Olivier Deprez
1631f9c75c Merge "feat(sve): support full SVE vector length" into integration 2022-08-09 15:25:57 +02:00
Leon Chen
8a68e8648b refactor(bl31): introduce vendor extend rodata section
The purpose of including vendor extend plat.ld.rodata.inc
linker script is for compactly collecting vendor rodata in
intrinsic rodata section.
If vendors define a standalone section and assign the section
placed after __RW_END__, the raw bindry(bl31.bin) will include
bss section with zero value and increase binary size.

Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I46dd8b02bfb26af1dcca27f61b3ea29ca74bbbd6
2022-08-09 11:39:11 +02:00
Joanna Farley
4a0d8632dd Merge "docs(juno): fix broken link" into integration 2022-08-08 09:54:02 +02:00
Arthur She
89e4cea14a docs(juno): fix broken link
The URL of the Juno Getting Started Guide has been changed.
Fix the broken link.

Signed-off-by: Arthur She <arthur.she@linaro.org>
Change-Id: I55697f2f1f787c32d1ea7dfcf9eda619906cdb5d
2022-08-08 09:27:59 +02:00
Joanna Farley
000e25bf6f Merge "fix(versal): use only one space for indentation" into integration 2022-08-08 00:00:44 +02:00
Joanna Farley
0da574c1c8 Merge changes from topic "xilinx-versal-coding-style" into integration
* changes:
  fix(versal): fix code indentation issues
  fix(versal): fix macro coding style issues
2022-08-07 23:59:52 +02:00
Juan Pablo Conde
14a6fed5ac fix(errata): workaround for Neoverse-V1 erratum 1618635
Neoverse-V1 erratum 1618635 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.
The workaround is done through the instruction patching
mechanism, which is performed by a write sequence of
IMPLEMENTATION DEFINED registers.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781/latest/

Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I53e406735cd3a2a930fdc72ebce3bbed97100168
2022-08-05 15:56:30 -04:00
Lauren Wehrmeister
73b73b1af6 Merge "fix: make TF-A use provided OpenSSL binary" into integration 2022-08-04 17:29:24 +02:00
Michal Simek
dee5885913 fix(versal): use only one space for indentation
Trivial patch to remove additional space.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ifa33dee81243c0b21ca0f13b8e4d575646818162
2022-08-04 14:08:32 +02:00
Salome Thirot
e95abc4c01 fix: make TF-A use provided OpenSSL binary
Currently Tf-A uses whatever openssl binary is on the system to sign
images. However if OPENSSL_DIR is specified in the build flags this can
lead to linking issues as the system binary can end up being linked
against shared libraries provided in OPENSSL_DIR/lib if both binaries
(the system's and the on in OPENSSL_DIR/bin) are the same version.
This patch ensures that the binary used is always the one given by
OPENSSL_DIR to avoid those link issues.

Signed-off-by: Salome Thirot <salome.thirot@arm.com>
Change-Id: Ib534e06ebc8482e4391e376d3791a87968de4a99
2022-08-04 10:45:46 +01:00
Michal Simek
72583f92e6 fix(versal): fix code indentation issues
Next line should be aligned with the previous code.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I20d82ba5fa70fa252341b62e57fac265241f3391
2022-08-04 09:21:12 +02:00
Michal Simek
80806aa123 fix(versal): fix macro coding style issues
Use only one space between #define and macro name.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ieb9bdd5bcfa56bd265df72692a09c7340fe132cb
2022-08-04 09:21:07 +02:00
Varun Wadekar
df56e9d199 fix(bl31): pass the EA bit to 'delegate_sync_ea'
During a synchronous exception, the 'enter_lower_el_sync_ea' handler
tests the ESR_EL3 EA bit and calls 'report_unhandled_exception', if
it is not set.

EA = 0 and IFSC = SEA, seems to be a contradiction. EA provides further
classification of a synchronous abort. A synchronous abort is determined
by the IFSC value on an instruction fetch synchronous abort. As a result,
EA will never be set to 1 on an instruction fetch synchronous abort and
'report_unhandled_exception' should not be called.

This patch removes this behavior to allow the platform to handle the
exception.

Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3f004447ad4316d81649063e1ffb3ac644c83ede
2022-08-03 12:01:36 +01:00
laurenw-arm
dddf4283b0 feat(bl): add interface to query TF-A semantic ver
Adding interface for stand-alone semantic version of TF-A
for exporting to RSS attestation, and potentially other areas
as well.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ib4a2c47aa1e42a3b850185e674c90708a05cda53
2022-08-02 16:04:23 -05:00
Bipin Ravi
17e76b5eb7 Merge "feat(plat/qti): fix to support cpu errata" into integration 2022-08-02 21:25:24 +02:00
Lauren Wehrmeister
c152276829 Merge changes from topic "st_fip_uuid" into integration
* changes:
  feat(stm32mp1): retrieve FIP partition by type UUID
  feat(guid-partition): allow to find partition by type UUID
  refactor(stm32mp1): update PLAT_PARTITION_MAX_ENTRIES
2022-08-01 16:45:49 +02:00
Joanna Farley
342a65fb21 Merge "feat(zynqmp): protect eFuses from non-secure access" into integration 2022-08-01 12:05:18 +02:00
Joanna Farley
2461654189 Merge changes from topic "xlnx_misra" into integration
* changes:
  fix(versal): resolve misra 10.1 warnings
  fix(versal): resolve the misra 4.6 warnings
2022-08-01 12:04:04 +02:00
Venkatesh Yadav Abbarapu
19f92c4cfe fix(versal): resolve misra 10.1 warnings
MISRA Violation: MISRA-C: 2012 R.10.1
-The operand to the operator does not have an essentially
unsigned type.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I4873a620086dfd6f636fe730165a9d13a29e9652
2022-07-31 14:08:53 +05:30
Venkatesh Yadav Abbarapu
f7c48d9e30 fix(versal): resolve the misra 4.6 warnings
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ieff90b5311a3bde8a2cb302ca81c23eeee6d235a
2022-07-31 14:07:11 +05:30
Vesa Jääskeläinen
d0b7286e48 feat(zynqmp): protect eFuses from non-secure access
When configuration option ZYNQMP_SECURE_EFUSES is defined then Xilinx
ZynqMP's PS eFuses can only be accesses from secure state.

This enables eFuses to be reserved and protected only for security use
cases for example in OP-TEE.

Change-Id: I866905e35ce488f50f5f6e1b4667b08a9fa2386d
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
2022-07-29 23:57:18 +03:00
Saurabh Gorecha
6cc743cf0f feat(plat/qti): fix to support cpu errata
fix to support ARM CPU errata based on core used.

Signed-off-by: Saurabh Gorecha <quic_sgorecha@quicinc.com>
Change-Id: If1a438f98f743435a7a0b683a32ccf14164db37e
2022-07-29 18:15:32 +05:30
Joanna Farley
8b06f0a280 Merge "fix(xilinx): miscellaneous fixes for xilinx platforms" into integration 2022-07-28 18:37:45 +02:00
Venkatesh Yadav Abbarapu
bfc514f103 fix(xilinx): miscellaneous fixes for xilinx platforms
This patch gathers miscellaneous minor fixes to the xilinx
platforms like tabs for indentation and misra 10.1 warnings.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I4cdb89ffec7d5abc64e065ed5b5e5d10b30ab9f9
2022-07-28 08:57:59 +05:30
Madhukar Pappireddy
1d867c14cb Merge "fix(ufs): add retries to ufs_read_capacity" into integration 2022-07-27 16:06:43 +02:00
Madhukar Pappireddy
7cf105f8fc Merge "fix(ufs): point utrlbau to header instead of upiu" into integration 2022-07-27 15:58:39 +02:00